KR920020715A - 불휘발성 기억장치 - Google Patents

불휘발성 기억장치 Download PDF

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Publication number
KR920020715A
KR920020715A KR1019920005638A KR920005638A KR920020715A KR 920020715 A KR920020715 A KR 920020715A KR 1019920005638 A KR1019920005638 A KR 1019920005638A KR 920005638 A KR920005638 A KR 920005638A KR 920020715 A KR920020715 A KR 920020715A
Authority
KR
South Korea
Prior art keywords
nonvolatile memory
drain regions
channel formation
source
gate
Prior art date
Application number
KR1019920005638A
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English (en)
Other versions
KR100201451B1 (ko
Inventor
아끼히로 나사무라
Original Assignee
오가 노리오
소니 가부시기가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 오가 노리오, 소니 가부시기가이샤 filed Critical 오가 노리오
Publication of KR920020715A publication Critical patent/KR920020715A/ko
Application granted granted Critical
Publication of KR100201451B1 publication Critical patent/KR100201451B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

내용 없음

Description

불휘발성 기억장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 실시예의 개략구성단면도.
제2도는 실시예의 레이아웃도.

Claims (1)

  1. 데이터선의 출력단자와 접지단자의 사이에 복수의 소스ㆍ드레인 영역을 직렬로 형성하고, 또한 각 소스ㆍ드레인영역간 상에 플로팅게이트와 콘트롤게이트를 적층하여 이루어지는 복수의 불휘발성 기억소자와, 상기 각 콘트롤게이트의 상면에 게이트절연막을 통해 채널형성영역을 형성하고, 또한 당해 각 채널 형성영역의 양측과 상기 각 소스ㆍ드레인영역에 접속하여 이루어지는 박막트랜지스터용의 소스ㆍ드레인영역을 통해 채널형성영역의 양측에 형성한 박막트랜지스터에 의해 이루어지는 것을 특징으로 하는 불휘발성 기억장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920005638A 1991-04-05 1992-04-04 불휘발성 기억장치 KR100201451B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP03102110A JP3114229B2 (ja) 1991-04-05 1991-04-05 不揮発性記憶装置
JP91-102110 1991-04-05

Publications (2)

Publication Number Publication Date
KR920020715A true KR920020715A (ko) 1992-11-21
KR100201451B1 KR100201451B1 (ko) 1999-06-15

Family

ID=14318666

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920005638A KR100201451B1 (ko) 1991-04-05 1992-04-04 불휘발성 기억장치

Country Status (3)

Country Link
US (1) US5338956A (ko)
JP (1) JP3114229B2 (ko)
KR (1) KR100201451B1 (ko)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2817500B2 (ja) * 1992-02-07 1998-10-30 日本電気株式会社 不揮発性半導体記憶装置
JPH06188394A (ja) * 1992-12-22 1994-07-08 Nec Corp 半導体記憶装置
JPH0745730A (ja) * 1993-02-19 1995-02-14 Sgs Thomson Microelettronica Spa ２レベルのポリシリコンｅｅｐｒｏｍメモリ・セル並びにそのプログラミング方法及び製造方法、集積されたｅｅｐｒｏｍ記憶回路、ｅｅｐｒｏｍメモリ・セル及びそのプログラミング方法
JP3192861B2 (ja) * 1994-03-14 2001-07-30 株式会社東芝 不揮発性半導体記憶装置
US5604141A (en) * 1994-03-15 1997-02-18 National Semiconductor Corporation Method for forming virtual-ground flash EPROM array with reduced cell pitch in the X direction
US5488579A (en) * 1994-04-29 1996-01-30 Motorola Inc. Three-dimensionally integrated nonvolatile SRAM cell and process
US5650960A (en) * 1994-05-18 1997-07-22 United Microelectronics Corporation Polysilicon programming memory cell
US5452250A (en) * 1994-06-14 1995-09-19 International Business Machines, Inc. Non-volatile register system utilizing thin-film floating-gate amorphous transistors
US5622881A (en) * 1994-10-06 1997-04-22 International Business Machines Corporation Packing density for flash memories
DE19531629C1 (de) * 1995-08-28 1997-01-09 Siemens Ag Verfahren zur Herstellung einer EEPROM-Halbleiterstruktur
JP3639028B2 (ja) * 1996-02-06 2005-04-13 株式会社東芝 半導体装置及びその製造方法
KR100207504B1 (ko) * 1996-03-26 1999-07-15 윤종용 불휘발성 메모리소자, 그 제조방법 및 구동방법
US5679591A (en) * 1996-12-16 1997-10-21 Taiwan Semiconductor Manufacturing Company, Ltd Method of making raised-bitline contactless trenched flash memory cell
US6127224A (en) 1997-12-31 2000-10-03 Stmicroelectronics, S.R.L. Process for forming a non-volatile memory cell with silicided contacts
US6022770A (en) * 1998-03-24 2000-02-08 International Business Machines Corporation NVRAM utilizing high voltage TFT device and method for making the same
CN1728392A (zh) * 2004-07-29 2006-02-01 上海华虹Nec电子有限公司 多层氧化可一次编程器件
US7282420B2 (en) * 2005-05-03 2007-10-16 Hynix Semiconductor Inc. Method of manufacturing a flash memory device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4476475A (en) * 1982-11-19 1984-10-09 Northern Telecom Limited Stacked MOS transistor
US4667217A (en) * 1985-04-19 1987-05-19 Ncr Corporation Two bit vertically/horizontally integrated memory cell
JP2685770B2 (ja) * 1987-12-28 1997-12-03 株式会社東芝 不揮発性半導体記憶装置
US4939690A (en) * 1987-12-28 1990-07-03 Kabushiki Kaisha Toshiba Electrically erasable programmable read-only memory with NAND cell structure that suppresses memory cell threshold voltage variation
JP2567025B2 (ja) * 1988-03-31 1996-12-25 株式会社東芝 半導体集積回路
US4996669A (en) * 1989-03-08 1991-02-26 Kabushiki Kaisha Toshiba Electrically erasable programmable read-only memory with NAND memory cell structure
JP3060680B2 (ja) * 1990-11-30 2000-07-10 日本電気株式会社 不揮発性半導体記憶装置

Also Published As

Publication number Publication date
US5338956A (en) 1994-08-16
KR100201451B1 (ko) 1999-06-15
JPH04309263A (ja) 1992-10-30
JP3114229B2 (ja) 2000-12-04

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