CN1728392A - 多层氧化可一次编程器件 - Google Patents

多层氧化可一次编程器件 Download PDF

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Publication number
CN1728392A
CN1728392A CNA2004100532955A CN200410053295A CN1728392A CN 1728392 A CN1728392 A CN 1728392A CN A2004100532955 A CNA2004100532955 A CN A2004100532955A CN 200410053295 A CN200410053295 A CN 200410053295A CN 1728392 A CN1728392 A CN 1728392A
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CN
China
Prior art keywords
programmable device
multiple layers
transistor
capacitive
available once
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2004100532955A
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English (en)
Inventor
姚泽强
徐向明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Hua Hong NEC Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Hua Hong NEC Electronics Co Ltd filed Critical Shanghai Hua Hong NEC Electronics Co Ltd
Priority to CNA2004100532955A priority Critical patent/CN1728392A/zh
Priority to US11/192,269 priority patent/US20060022255A1/en
Publication of CN1728392A publication Critical patent/CN1728392A/zh
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices

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  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)

Abstract

本发明公开了一种多层氧化可一次编程器件，在晶体管和电容侧分别采用不同的栅氧化厚度。本发明既可以提高电容耦合效率，又会大大减小芯片的面积。本发明适用于半导体集成电路及分离元器件。

Description

多层氧化可一次编程器件
技术领域
本发明涉及半导体器件，特别是涉及一种多层氧化可一次编程器件。
背景技术
在单层多晶硅一次可编程器件(Single-Poly OTP Device)设计中，如何达到提高电容型晶体管的耦合效率，以提高编程效果，是OTP(one time programmable可一次编程)器件设计中需要解决的关键问题。
现有技术中，单层多晶硅一次可编程器件设计，在整个OTP器件的晶体管和电容侧均采用相同厚度的氧化层。《A Single PolyEEPROM Cell Structure for Use in Standard CMOS Processes》(IEEEJOURNAL OF SOLID-STATECIRCUITS，VOL.24，NO.4，AUGUST1989)、《Cell and Circuit Design for Single-Poly EPROM》(IEEEJOURNAL OF SOLID-STATECIRCUITS，VOL.29，NO.3，March，1994)等文献就披露了这种结构形式的单层多晶硅一次可编程器件。
这种OTP器件，由于晶体管及电容两侧的氧化层厚度相同，因而大多都以增大芯片面积来提高电容耦合效率。因此会使芯片的面积增加。
发明内容
本发明要解决的技术问题是提供一种多层氧化可一次编程器件，它既可以提高电容耦合效率，又会大大减小芯片的面积。
为解决上述技术问题，本发明采用的技术方案是：在OTP器件的晶体管侧和电容侧分别采用两种不同厚度的栅氧化膜，晶体管侧采用厚栅氧区，电容侧采用薄栅氧区。
由于本发明在晶体管和电容侧分别采用不同的栅氧化厚度，从而可以提高电容侧耦合效率，进而改善器件编程效率和大大减小芯片面积。另外，在Multi-Oxide CMOS(多层氧化CMOS)集成工艺中非常容易实现。
附图说明
附图是本发明多层氧化可一次编程器件的结构示意图。
其中：1表示厚栅氧区    2表示薄栅氧区    3表示Poly(多晶硅)

Claims (1)

1.一种多层氧化可一次编程器件，其特征在于：在OTP器件的晶体管侧和电容侧分别采用两种不同厚度的栅氧化膜，在晶体管侧采用厚栅氧区，在电容侧采用薄栅氧区。
CNA2004100532955A 2004-07-29 2004-07-29 多层氧化可一次编程器件 Pending CN1728392A (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CNA2004100532955A CN1728392A (zh) 2004-07-29 2004-07-29 多层氧化可一次编程器件
US11/192,269 US20060022255A1 (en) 2004-07-29 2005-07-29 Multi-oxide OTP device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNA2004100532955A CN1728392A (zh) 2004-07-29 2004-07-29 多层氧化可一次编程器件

Publications (1)

Publication Number Publication Date
CN1728392A true CN1728392A (zh) 2006-02-01

Family

ID=35731146

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2004100532955A Pending CN1728392A (zh) 2004-07-29 2004-07-29 多层氧化可一次编程器件

Country Status (2)

Country Link
US (1) US20060022255A1 (zh)
CN (1) CN1728392A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101452937B (zh) * 2007-11-30 2012-06-20 上海华虹Nec电子有限公司 一次可编程非挥发性存储器芯片单元及其制备方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7868370B2 (en) * 2008-04-14 2011-01-11 Macronix International Co., Ltd. Single gate nonvolatile memory cell with transistor and capacitor
US7999296B2 (en) 2008-04-14 2011-08-16 Macronix International Co., Ltd. Single gate nonvolatile memory cell with transistor and capacitor
US10109639B1 (en) * 2017-06-09 2018-10-23 International Business Machines Corporation Lateral non-volatile storage cell

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3114229B2 (ja) * 1991-04-05 2000-12-04 ソニー株式会社 不揮発性記憶装置
US5761121A (en) * 1996-10-31 1998-06-02 Programmable Microelectronics Corporation PMOS single-poly non-volatile memory structure
US5761126A (en) * 1997-02-07 1998-06-02 National Semiconductor Corporation Single-poly EPROM cell that utilizes a reduced programming voltage to program the cell

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101452937B (zh) * 2007-11-30 2012-06-20 上海华虹Nec电子有限公司 一次可编程非挥发性存储器芯片单元及其制备方法

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US20060022255A1 (en) 2006-02-02

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