KR910013738A - BiCMOS TTL레벨 구동장치 - Google Patents

BiCMOS TTL레벨 구동장치 Download PDF

Info

Publication number
KR910013738A
KR910013738A KR1019890020225A KR890020225A KR910013738A KR 910013738 A KR910013738 A KR 910013738A KR 1019890020225 A KR1019890020225 A KR 1019890020225A KR 890020225 A KR890020225 A KR 890020225A KR 910013738 A KR910013738 A KR 910013738A
Authority
KR
South Korea
Prior art keywords
transistor
turned
bicmos
vin
ttl level
Prior art date
Application number
KR1019890020225A
Other languages
English (en)
Other versions
KR920010212B1 (ko
Inventor
최명준
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019890020225A priority Critical patent/KR920010212B1/ko
Priority to US07/594,828 priority patent/US5103119A/en
Priority to GB9022335A priority patent/GB2239750B/en
Priority to JP2273520A priority patent/JPH0738582B2/ja
Priority to FR9012675A priority patent/FR2656749B1/fr
Priority to DE4032733A priority patent/DE4032733A1/de
Priority to IT02177990A priority patent/IT1243456B/it
Publication of KR910013738A publication Critical patent/KR910013738A/ko
Application granted granted Critical
Publication of KR920010212B1 publication Critical patent/KR920010212B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/088—Transistor-transistor logic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H03K19/017518—Interface arrangements using a combination of bipolar and field effect transistors [BIFET]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
    • H03K17/0412—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit
    • H03K17/04126—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit in bipolar transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
    • H03K17/0412—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit
    • H03K17/0414—Anti-saturation measures
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H03K17/615—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors in a Darlington configuration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/001—Arrangements for reducing power consumption in bipolar transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/013—Modifications for accelerating switching in bipolar transistor circuits
    • H03K19/0136—Modifications for accelerating switching in bipolar transistor circuits by means of a pull-up or down element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0036—Means reducing energy consumption

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
  • Acyclic And Carbocyclic Compounds In Medicinal Compositions (AREA)
  • Traffic Control Systems (AREA)

Abstract

내용 없음.

Description

BiCMOS TTL 레벨 구동장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명 BiCMOS TTL 레벨 구동장치의 회로도이다.

Claims (5)

  1. BiCMOS 공정을 위하여 구성되는 TTL 논리회로 장치에 있어서, 상기 TTL 논리회로장치의 입력단(VIN)에 연결되어 후단에 연결되는 제1 스위칭부(2)의 누설전류 방지신호 및 후단에 연결되는 제2 스위칭부의 포화전압상태를 방지하는 포화방지 회로부(1)와, 포화방지회로부(1)에 연결되어 후단에 구성되는 제1 스위칭부(2) 및 제2 스위칭부(4)와의 제어신호를 인가하는 제어부와, 구성되는 BiCMOS TTL 레벨출력구동장치.
  2. 제1항에 있어서, 상기 포화방지회로부(1)는, 전원(VCC)에 연결된 다이오드(D1),(D2)와, 상기 다이오드(D2)에 연결되고 입력단(VIN)의 입력신호에 따라 구동되는 PMOS 트랜지스터(P1)와, 상기 PMOS 트랜지스터(P1)에 연결되고, 상기 입력단(VIN)에 게이트가 연결되어 턴오프상태를 유지하는 NMOS 트랜지스터(N1)와,로 구성되는 BiCMOS TTL 레벨출력구동장치.
  3. 제1항에 있어서, 상기 제어부는, 상기 포화방지회로부(1)의 PMOS 트랜지스터(P1)가 턴온됨에 따라 턴온되는 트랜지스터(Q7)와, 상기 트랜지스터(Q7)의 에미터측과 연결되어 상기 트랜지스터(Q7)의 턴온가능한 바이어스전압을 상승하게 하는 다이오드(D3)와, 로 구성되는 BiCMOS TTL 레벨출력구동장치.
  4. 제1항에 있어서, 상기 제1 스위칭부(2)는 입력측(VIN)에 연결되는 인버터(I1)와, 상기 인버터(I1)의 신호에 따라 구동하여 누설전류를 방지하는 PMOS 트랜지스터(P2)와, 상기 PMOS 트랜지스터(P1)에 연결되어 상기 제어부(3)의 트랜지스터(Q7)가 턴오프됨에 따라 턴온상태가 되는 트랜지스터(Q5),(Q6)와, 상기 트랜지스터(Q6)의 베이스에 연결되어 상기 포화방지회로부(1)의 신호에 따라 구동되는 누설전류방지용 NMOS 트랜지스터(N2)와, 로 구성되는 BiCMOS TTL 레벨출력구동장치.
  5. 제1항에 있어서, 상기 제2 스위칭부(4)는 상기 제어부(3) 트랜지스터(Q7)가 턴온됨에 따라 턴온되는 트랜지스터(Q8)와, 상기 트랜지스터(Q8)의 베이스측 및 입력단(VIN)에 연결되어 입력신호에 따라 구동되는 NMOS 트랜지스터(N3)와, 로 구성된 BiCMOS TTL 레벨구동장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890020225A 1989-12-29 1989-12-29 바이씨모스 ttl레벨 출력구동회로 KR920010212B1 (ko)

Priority Applications (7)

Application Number Priority Date Filing Date Title
KR1019890020225A KR920010212B1 (ko) 1989-12-29 1989-12-29 바이씨모스 ttl레벨 출력구동회로
US07/594,828 US5103119A (en) 1989-12-29 1990-10-09 Ttl-level bicmos driver
GB9022335A GB2239750B (en) 1989-12-29 1990-10-15 Driver circuit
JP2273520A JPH0738582B2 (ja) 1989-12-29 1990-10-15 ＢｉＣＭＯＳ ＴＴＬレベル駆動回路
FR9012675A FR2656749B1 (fr) 1989-12-29 1990-10-15 Dispositif a transistors bicmos pour la commande de circuits logiques ttl.
DE4032733A DE4032733A1 (de) 1989-12-29 1990-10-15 Ttl-pegel-bicmos-treiber
IT02177990A IT1243456B (it) 1989-12-29 1990-10-18 Pilota bicmos di livello ttl

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890020225A KR920010212B1 (ko) 1989-12-29 1989-12-29 바이씨모스 ttl레벨 출력구동회로

Publications (2)

Publication Number Publication Date
KR910013738A true KR910013738A (ko) 1991-08-08
KR920010212B1 KR920010212B1 (ko) 1992-11-21

Family

ID=19294274

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890020225A KR920010212B1 (ko) 1989-12-29 1989-12-29 바이씨모스 ttl레벨 출력구동회로

Country Status (7)

Country Link
US (1) US5103119A (ko)
JP (1) JPH0738582B2 (ko)
KR (1) KR920010212B1 (ko)
DE (1) DE4032733A1 (ko)
FR (1) FR2656749B1 (ko)
GB (1) GB2239750B (ko)
IT (1) IT1243456B (ko)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920010212B1 (ko) 1989-12-29 1992-11-21 삼성전자 주식회사 바이씨모스 ttl레벨 출력구동회로
DE69411312T2 (de) * 1993-04-19 1999-02-11 Philips Electronics Nv BiCMOS Ausgangstreiberschaltung
JP3881337B2 (ja) * 2003-12-26 2007-02-14 ローム株式会社 信号出力回路及びそれを有する電源電圧監視装置
KR101683877B1 (ko) * 2009-10-23 2016-12-07 엘지이노텍 주식회사 전원 공급 보호 장치
US8623749B2 (en) * 2010-12-20 2014-01-07 Diodes Incorporated Reduction of stored charge in the base region of a bipolar transistor to improve switching speed

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4441068A (en) * 1981-10-22 1984-04-03 Kollmorgen Technologies Corporation Bipolar linear current source driver amplifier for switching loads
JPH0783252B2 (ja) * 1982-07-12 1995-09-06 株式会社日立製作所 半導体集積回路装置
US4472647A (en) * 1982-08-20 1984-09-18 Motorola, Inc. Circuit for interfacing with both TTL and CMOS voltage levels
DE3280350D1 (de) * 1982-08-25 1991-09-26 Ibm Deutschland Transistor-leistungsverstaerker mit verringerten schaltzeiten.
JPH0693626B2 (ja) * 1983-07-25 1994-11-16 株式会社日立製作所 半導体集積回路装置
JPS60141016A (ja) * 1983-12-28 1985-07-26 Nec Corp 出力回路
JPS60141011A (ja) * 1983-12-28 1985-07-26 Nec Corp コレクタ飽和抑制回路
JPS60177723A (ja) * 1984-02-24 1985-09-11 Hitachi Ltd 出力回路
JPS62171226A (ja) * 1986-01-22 1987-07-28 Nec Corp 出力回路
US4703203A (en) * 1986-10-03 1987-10-27 Motorola, Inc. BICMOS logic having three state output
JPS63193720A (ja) * 1987-02-06 1988-08-11 Toshiba Corp 論理回路
JPS63202126A (ja) * 1987-02-17 1988-08-22 Toshiba Corp 論理回路
JPH01114214A (ja) * 1987-10-28 1989-05-02 Nec Corp 出力回路
US4857776A (en) * 1987-11-20 1989-08-15 Tandem Computers Incorporated True TTL output translator-driver with true ECL tri-state control
US4810903A (en) * 1987-12-14 1989-03-07 Motorola, Inc. BICMOS driver circuit including submicron on chip voltage source
US4970414A (en) * 1989-07-07 1990-11-13 Silicon Connections Corporation TTL-level-output interface circuit
KR920010212B1 (ko) 1989-12-29 1992-11-21 삼성전자 주식회사 바이씨모스 ttl레벨 출력구동회로

Also Published As

Publication number Publication date
DE4032733C2 (ko) 1992-11-05
JPH0738582B2 (ja) 1995-04-26
GB9022335D0 (en) 1990-11-28
IT1243456B (it) 1994-06-10
DE4032733A1 (de) 1991-08-08
GB2239750A (en) 1991-07-10
KR920010212B1 (ko) 1992-11-21
US5103119A (en) 1992-04-07
GB2239750B (en) 1994-09-07
JPH03216017A (ja) 1991-09-24
FR2656749A1 (fr) 1991-07-05
FR2656749B1 (fr) 1993-12-24
IT9021779A0 (it) 1990-10-18
IT9021779A1 (it) 1992-04-18

Similar Documents

Publication Publication Date Title
KR100210716B1 (ko) 반도체 집적 회로 장치
KR970017598A (ko) 반도체 장치 및 그 제어 회로
KR930003556A (ko) 점진적 턴-온 특성의 cmos 구동기
KR950010340A (ko) 정 전류 발생 장치
KR930009268A (ko) 고속이면서 저 전력의 전압 모드 차동 드라이버 회로
US4996449A (en) Output circuit having high speed operation and low power dissipation
KR960012722A (ko) 출력 버퍼 회로
KR910013738A (ko) BiCMOS TTL레벨 구동장치
KR940025181A (ko) BiCMOS 출력 구동 회로
KR940003187A (ko) 시모스(cmos) 3-스테이트 버퍼회로 및 그 제어방법
KR960009401A (ko) 비교기 회로
KR880006850A (ko) 3스테이트 부설 상보형 mos집적회로
KR920020511A (ko) 출력 버퍼 회로
KR940004833A (ko) 씨엠오에스(cmos)회로의 래치업 저감출력 드라이버 및 래치업 저감방법
KR940010531A (ko) 전력 전압보다 작은 진폭을 갖는 입력 신호를 위한 버퍼 회로
KR880012013A (ko) 3상태 출력회로
KR890011195A (ko) 증폭회로
KR910010866A (ko) Bi-CMOS회로
US5365124A (en) BiCMOS logic circuit
KR920001844A (ko) 플립플롭 회로 및 그 로직 상태 제공 방법
KR910010874A (ko) 출력회로
KR970022418A (ko) 전류구동 능력이 큰 게이트 드라이버회로
IT1313719B1 (it) Stadio d'uscita per circuiti comparatori ad alta velocita'
KR100190378B1 (ko) 고속 스위칭 드라이버
KR880009470A (ko) 스위칭 전원

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20071101

Year of fee payment: 16

LAPS Lapse due to unpaid annual fee