KR910013567A - 이형상의 소자분리영역의 접합구조를 가지는 반도체장치 - Google Patents

이형상의 소자분리영역의 접합구조를 가지는 반도체장치 Download PDF

Info

Publication number
KR910013567A
KR910013567A KR1019900021990A KR900021990A KR910013567A KR 910013567 A KR910013567 A KR 910013567A KR 1019900021990 A KR1019900021990 A KR 1019900021990A KR 900021990 A KR900021990 A KR 900021990A KR 910013567 A KR910013567 A KR 910013567A
Authority
KR
South Korea
Prior art keywords
isolation region
junction structure
device isolation
semiconductor device
heteromorphic
Prior art date
Application number
KR1019900021990A
Other languages
English (en)
Other versions
KR940001391B1 (ko
Inventor
시게루 모리타
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR910013567A publication Critical patent/KR910013567A/ko
Application granted granted Critical
Publication of KR940001391B1 publication Critical patent/KR940001391B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

내용 없음.

Description

이형상의 소자분리영역의 접합구조를 가지는 반도체장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도(a)는 본 발명의 제1실시예에 따른 소자분리영역의 접합점을 위에서 본 정면도,
제1도(b)는 제1도(a)의 소자분리영역의 접합점의 단면도를 비스듬하게 위에서 본 사시도.

Claims (3)

  1. 반도제기판상에 형성된 제1소자분리영역(11,21,31)과, 상기 반도체기판상에 제1소자분리영역과 접합하도록 형성됨과 더불어 그 제1소자분리영역에 대해서 충분히 미세한 제2 소자분리영역(12,22,32)의 접합점에 있어서, 상기 제1 소자분리영역의 단부를 이루는 한쪽과 상기 미세한 소자분리영역의 한쪽이 형성하는 소자영역을 끼운 사이각이 둔각인 것을 특징으로 하는 이형상의 소자분리영역의 접합구조를 가지는 반도체장치.
  2. 제1항에 있어서, 상기 제1소자분리영역이 로코스법에 의해서 형성되는 로코스 소자분리영역과, 상기 제2소자분리영역이 매립법에 의해서 형성되는 매립 소자분리영역으로 이루어진 것을 특징으로 하는 이형상의 소자분리영역의 접합구조를 가지는 반도체장치.
  3. 제1항에 있어서, 상기 제1 소자분리영역의 단부 및 상기 제2 소자 분리영역의 단부가 적어도 한쪽이 만곡(21a,31a)으로 형성되어 접합되고 그 쪽의 접합으로서 형성되는 사이각이 둔각인 것을 특징으로 하는 이형상의 소자분리층의 접합구조를 가지는 반도체 장치.
    ※ 참고사항 : 최초출된 내용에 의하여 공개하는 것임.
KR1019900021990A 1989-12-27 1990-12-27 이형상의 소자분리영역의 접합구조를 가지는 반도체장치 KR940001391B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP1-336657 1989-12-27
JP89-336657 1989-12-27
JP1336657A JPH0810691B2 (ja) 1989-12-27 1989-12-27 異形状の素子分離領域の接合構造を有する半導体装置

Publications (2)

Publication Number Publication Date
KR910013567A true KR910013567A (ko) 1991-08-08
KR940001391B1 KR940001391B1 (ko) 1994-02-21

Family

ID=18301438

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900021990A KR940001391B1 (ko) 1989-12-27 1990-12-27 이형상의 소자분리영역의 접합구조를 가지는 반도체장치

Country Status (3)

Country Link
US (1) US5148258A (ko)
JP (1) JPH0810691B2 (ko)
KR (1) KR940001391B1 (ko)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5834360A (en) * 1996-07-31 1998-11-10 Stmicroelectronics, Inc. Method of forming an improved planar isolation structure in an integrated circuit
JP5431638B2 (ja) * 2006-10-27 2014-03-05 ローム株式会社 半導体集積回路
JP6055240B2 (ja) * 2012-08-29 2016-12-27 ラピスセミコンダクタ株式会社 半導体装置及びその製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4929992A (en) * 1985-09-18 1990-05-29 Advanced Micro Devices, Inc. MOS transistor construction with self aligned silicided contacts to gate, source, and drain regions
JPS62263658A (ja) * 1986-05-12 1987-11-16 Toshiba Corp 半導体装置およびその製造方法
JPH01181468A (ja) * 1988-01-08 1989-07-19 Toshiba Corp 半導体装置

Also Published As

Publication number Publication date
JPH0810691B2 (ja) 1996-01-31
KR940001391B1 (ko) 1994-02-21
US5148258A (en) 1992-09-15
JPH03198336A (ja) 1991-08-29

Similar Documents

Publication Publication Date Title
KR910019269A (ko) 반도체 수광소자
KR920015588A (ko) 광 반도체장치
KR940008112A (ko) 트랜지스터 및 그 제조 방법
KR960039290A (ko) 반도체 장치
KR850000803A (ko) 반도체 장치
KR920008954A (ko) 반도체 장치
KR840002162A (ko) 반도체 장치(半導體裝置)
KR920007254A (ko) 반도체장치
KR850001642A (ko) 증폭기 회로
KR920005380A (ko) 화합물반도체 장치
KR910013567A (ko) 이형상의 소자분리영역의 접합구조를 가지는 반도체장치
KR970060388A (ko) 반도체 장치 및 반도체 장치의 제조방법
KR910016061A (ko) 반도체장치 및 그 제조방법
KR870008392A (ko) 직교식 쌍극성 트랜지스터
KR880010495A (ko) 반도체장치의 제조방법
KR900004040A (ko) 반도체 집적회로 디바이스
KR910013565A (ko) 래터럴형 반도체장치
KR930015106A (ko) 제너 다이오드
SE9403722L (sv) Halvledaranordning
KR860001492A (ko) 다이오드 구조체
KR900001025A (ko) 반도체장치
KR920005343A (ko) 수직퓨즈장치
KR900017213A (ko) 반도체 장치
KR890005834A (ko) 반도체장치
KR910010662A (ko) 반도체장치의 패키지

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20030130

Year of fee payment: 10

LAPS Lapse due to unpaid annual fee