KR910010662A - 반도체장치의 패키지 - Google Patents

반도체장치의 패키지 Download PDF

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Publication number
KR910010662A
KR910010662A KR1019900018101A KR900018101A KR910010662A KR 910010662 A KR910010662 A KR 910010662A KR 1019900018101 A KR1019900018101 A KR 1019900018101A KR 900018101 A KR900018101 A KR 900018101A KR 910010662 A KR910010662 A KR 910010662A
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KR
South Korea
Prior art keywords
package
semiconductor device
external terminals
shield
shielding
Prior art date
Application number
KR1019900018101A
Other languages
English (en)
Other versions
KR940008341B1 (ko
Inventor
노부타카 마츠오카
요시오 야마모토
분시로 야마키
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR910010662A publication Critical patent/KR910010662A/ko
Application granted granted Critical
Publication of KR940008341B1 publication Critical patent/KR940008341B1/ko

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음

Description

반도체장치의 패키지
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는제1도의 반도체장치의 패키지에 더블밸런스드믹서회로(Double balanced mixer回路)를 내장시킨 구성을 나타낸 개략적 평면도.

Claims (6)

  1. 적어도 3개의 외부단자가 제1방향으로 연장설치되고, 이 제1방향에 대향한 제2방향에 적어도 3개의 외부단자가 연장설치된 반도체장치의 패키지에 있어서, 상기 외부단자의 적어도 1개는 접지되는 것으로, 상기 제1방향과 상기 제2방향으로 연장설치된 다른 외부단자간을 차폐시키는 차폐부(241, 242, 281, 282, 31, 351, 352, 401, 402)를 갖추고 있는 것을 특징으로 하는 반도체장치의 패키지.
  2. 제1항에 있어서, 상기 차폐부(241, 242, 281, 282, 31, 351, 352, 401, 402)는 상기 제1및 제2방향에 대하여 대략 수직방향으로 연장설치되어 있는 것을 특징으로 하는 반도체장치의 패키지.
  3. 제2항에 있어서, 상기 차폐부부(241, 242, 281, 282, 31, 351, 352, 401, 402)는 상기 제1및 제2방향에 대하여 대략 수직인 제3 및 이 제3방향과 반대인 제 4방향에 연장설치되어 있는 것을 특징으로 하는 반도체장치의 패키지.
  4. 제1항에 있어서, 상기 차폐부부(241, 242, 281, 282, 31, 351, 352, 401, 402)를 갖추고 있는 외부단자는 다른 인접하는 외부단자간을 차폐시키는 인접차폐부를 갖추고 있는 것을 특징으로 하는 반도체장치의 패키지.
  5. 제3항에 있어서, 상기 차폐부부(241, 242, 281, 282, 31, 351, 352, 401, 402)를 갖추고 있지 않은 외부단자의 서로 대향하는 대향면은 상기 제3 및 제4방향으로 연장설치된 상기 차폐부부(241, 242, 281, 282, 31, 351, 352, 401, 402)의 길이에 따라 설정가능한 것을 특징으로 하는 반도체장치의 패키지.
  6. 제5항에 있어서, 상기 차폐부부(241, 242, 281, 282, 31, 351, 352, 401, 402)를 갖추고 있지 않은 외부단자의 서로 대향하는 대향면은 상기 차폐부(241, 242, 281, 282, 31, 351, 352, 401, 402)에 의해 차폐되지 않은 부분이 절제되는 것을 특징으로 하는 반도체장치의 패키지.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900018101A 1989-11-09 1990-11-09 반도체장치의 패키지 KR940008341B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1290064A JPH03151659A (ja) 1989-11-09 1989-11-09 半導体装置の外囲器
JP01-290064 1989-11-09

Publications (2)

Publication Number Publication Date
KR910010662A true KR910010662A (ko) 1991-06-29
KR940008341B1 KR940008341B1 (ko) 1994-09-12

Family

ID=17751324

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900018101A KR940008341B1 (ko) 1989-11-09 1990-11-09 반도체장치의 패키지

Country Status (2)

Country Link
JP (1) JPH03151659A (ko)
KR (1) KR940008341B1 (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995002313A1 (en) * 1993-07-06 1995-01-19 Kabushiki Kaisha Toshiba Heat dissipating sheet

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5723309B2 (ko) * 1972-06-13 1982-05-18
JPS5957464A (ja) * 1982-09-27 1984-04-03 Mitsubishi Electric Corp 半導体装置
JPS6237952A (ja) * 1985-08-12 1987-02-18 Matsushita Electronics Corp 半導体装置

Also Published As

Publication number Publication date
KR940008341B1 (ko) 1994-09-12
JPH03151659A (ja) 1991-06-27

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