KR890015512A - Fet 논리 회로 - Google Patents

Fet 논리 회로 Download PDF

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Publication number
KR890015512A
KR890015512A KR1019890002739A KR890002739A KR890015512A KR 890015512 A KR890015512 A KR 890015512A KR 1019890002739 A KR1019890002739 A KR 1019890002739A KR 890002739 A KR890002739 A KR 890002739A KR 890015512 A KR890015512 A KR 890015512A
Authority
KR
South Korea
Prior art keywords
fet
logic circuit
fet logic
constant current
signal transfer
Prior art date
Application number
KR1019890002739A
Other languages
English (en)
Other versions
KR920004906B1 (ko
Inventor
기이찌 야마시따
게이이찌 기따무라
노부오 고데라
야스시 하쯔따
히로유끼 다나까
Original Assignee
미다 가쓰기게
가부시끼가이샤 히다찌 세이사꾸쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 미다 가쓰기게, 가부시끼가이샤 히다찌 세이사꾸쇼 filed Critical 미다 가쓰기게
Publication of KR890015512A publication Critical patent/KR890015512A/ko
Application granted granted Critical
Publication of KR920004906B1 publication Critical patent/KR920004906B1/ko

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09432—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors with coupled sources or source coupled logic
    • H03K19/09436—Source coupled field-effect logic [SCFL]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

내용 없음

Description

FET 논리 회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명의 1실시예를 도시한 접속도. 제 3 도, 제 4 도 및 제 5 도는 각각 본 발명의 다른 실시예를 도시한 접속도.

Claims (2)

  1. FET, 다이오드 및 저항으로 형성되는 FET논리 회로에 있어서, 기본 논리회로와 출력단자를 여러단의 FET 소스플로워 회로에 접속하고, 또한 상기 소스플로워회로의 신호 전달용 FET 및 정전류원용 FET의 각 게이트 폭 Wg1n과 Wg2n의 비율은 n+1Wg2n/Wg1n으로 설정하는 것을 특징으로 하는 FET 논리회로.
  2. 특허청구의 범위 제 1 항에 있어서, 상기 신호전달용 FET와 정전류원용 FET 사이에 여러개의 FET 또는 다이오드를 접속하는 것을 특징으로 하는 FET 논리회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890002739A 1988-03-16 1989-03-06 Fet 논리회로 KR920004906B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP63060385A JP2574859B2 (ja) 1988-03-16 1988-03-16 Ｆｅｔ論理回路
JP88-60385 1988-03-16
JP63-60385 1988-03-16

Publications (2)

Publication Number Publication Date
KR890015512A true KR890015512A (ko) 1989-10-30
KR920004906B1 KR920004906B1 (ko) 1992-06-22

Family

ID=13140629

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890002739A KR920004906B1 (ko) 1988-03-16 1989-03-06 Fet 논리회로

Country Status (3)

Country Link
US (1) US4968904A (ko)
JP (1) JP2574859B2 (ko)
KR (1) KR920004906B1 (ko)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07101839B2 (ja) * 1989-10-06 1995-11-01 東芝マイクロエレクトロニクス株式会社 ソースカップルドｆｅｔロジック形論理回路
JPH03173289A (ja) * 1989-12-01 1991-07-26 Toshiba Corp 最大値／最小値回路
DE4007212A1 (de) * 1990-03-07 1991-09-12 Siemens Ag Integrierbare transistorschaltung zur abgabe logischer pegel
JPH04127467A (ja) * 1990-06-04 1992-04-28 Mitsubishi Electric Corp 半導体集積回路装置
US5182473A (en) * 1990-07-31 1993-01-26 Cray Research, Inc. Emitter emitter logic (EEL) and emitter collector dotted logic (ECDL) families
JPH04278719A (ja) * 1991-03-06 1992-10-05 Toshiba Corp ソース電極結合形論理回路
JP3315178B2 (ja) * 1993-02-19 2002-08-19 三菱電機株式会社 レベルシフト回路
JPH07326936A (ja) * 1994-06-02 1995-12-12 Mitsubishi Electric Corp 差動増幅器
JPH08204536A (ja) * 1995-01-20 1996-08-09 Fujitsu Ltd インタフェース回路及びレベル変換回路
US5789941A (en) * 1995-03-29 1998-08-04 Matra Mhs ECL level/CMOS level logic signal interfacing device
US5920203A (en) * 1996-12-24 1999-07-06 Lucent Technologies Inc. Logic driven level shifter
US6469562B1 (en) * 2000-06-26 2002-10-22 Jun-Ren Shih Source follower with Vgs compensation

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5999819A (ja) * 1982-11-27 1984-06-08 Hitachi Ltd 入力インタ−フエイス回路
US4743782A (en) * 1984-11-09 1988-05-10 Honeywell Inc. GaAs level-shift logic interface circuit
US4728821A (en) * 1985-04-19 1988-03-01 Digital Equipment Corporation Source follower current mode logic cells
US4716311A (en) * 1985-04-25 1987-12-29 Triquint Direct coupled FET logic with super buffer output stage
DE3582802D1 (de) * 1985-10-15 1991-06-13 Ibm Leseverstaerker zur verstaerkung von signalen auf einer vorgespannten leitung.
EP0226678B1 (en) * 1985-12-24 1989-04-26 Fujitsu Limited Logic circuit
FR2594610A1 (fr) * 1986-02-18 1987-08-21 Labo Electronique Physique Dispositif semiconducteur du type reseau de portes prediffuse pour circuits a la demande
US4812683A (en) * 1987-05-19 1989-03-14 Gazelle Microcircuits, Inc. Logic circuit connecting input and output signal leads
US4812676A (en) * 1987-12-21 1989-03-14 Digital Equipment Corporation Current mode logic switching circuit having a Schmitt trigger
US4831284A (en) * 1988-03-22 1989-05-16 International Business Machines Corporation Two level differential current switch MESFET logic

Also Published As

Publication number Publication date
US4968904A (en) 1990-11-06
JPH01235416A (ja) 1989-09-20
KR920004906B1 (ko) 1992-06-22
JP2574859B2 (ja) 1997-01-22

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