KR890011019A - 반도체장치 - Google Patents

반도체장치 Download PDF

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Publication number
KR890011019A
KR890011019A KR1019880017269A KR880017269A KR890011019A KR 890011019 A KR890011019 A KR 890011019A KR 1019880017269 A KR1019880017269 A KR 1019880017269A KR 880017269 A KR880017269 A KR 880017269A KR 890011019 A KR890011019 A KR 890011019A
Authority
KR
South Korea
Prior art keywords
conductive layer
bit line
semiconductor device
bit
cell
Prior art date
Application number
KR1019880017269A
Other languages
English (en)
Other versions
KR930000599B1 (ko
Inventor
시즈오 사와다
마사키 오기하라
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
다케다이 마사다카
도시바 마이콤 엔지니어링 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바, 다케다이 마사다카, 도시바 마이콤 엔지니어링 가부시키가이샤 filed Critical 아오이 죠이치
Publication of KR890011019A publication Critical patent/KR890011019A/ko
Application granted granted Critical
Publication of KR930000599B1 publication Critical patent/KR930000599B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음

Description

반도체장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명의 실시예에 따른 제조공정을 도시한 구성도.
제 2 도 및 제 3 도는 본 발명에 따른 셀어레이배치예를 도시한 구성설명도.

Claims (4)

  1. 비트선이 비트선콘택트를 매개하여 트랜지스터 및 캐패시터로 형성된 다이나믹억세스메모리의 셀에 접속되는 반도체장치에 있어서, 2개 이상의 비트선콘택트를 통하여 접속되는 제 1 도전층과, 이 제 1 도전층상에 형성된 콘택트호울을 통해 상기 제 1 도전층과 접속되는 제 2 도전층을 구비한 것을 특징으로 하는 반도체장치.
  2. 제 1 항에 있어서, 상기 제 2 도전층으로서, 1개의 감기증폭기에 접속되는 비트선쌍중 한쪽 비트선을 구성하며 모든 셀에 접속되고 있는 제 2 도전층을 사용하는 것을 특징으로 하는 반도체장치.
  3. 제 2 항에 있어서, 상기 비트선으로서, 비트선방향의 셀열 사이에 배치된 비트선(112)을 사용하는 것을 특징으로 하는 반도체장치.
  4. 제 1 항 내지 제 3 항중 어느 한 항에 있어서, 상기 제 1 도전층으로서, 다결정실리콘으로 형성되어 있는 제 1 도전층(109)을 사용하는 것을 특징으로 하는 반도체장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880017269A 1987-12-22 1988-12-22 반도체장치 KR930000599B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP62324478A JPH06105773B2 (ja) 1987-12-22 1987-12-22 半導体装置
JP87-324478 1987-12-22
JP62-324478 1987-12-22

Publications (2)

Publication Number Publication Date
KR890011019A true KR890011019A (ko) 1989-08-12
KR930000599B1 KR930000599B1 (ko) 1993-01-25

Family

ID=18166252

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880017269A KR930000599B1 (ko) 1987-12-22 1988-12-22 반도체장치

Country Status (3)

Country Link
US (1) US5111275A (ko)
JP (1) JPH06105773B2 (ko)
KR (1) KR930000599B1 (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW203146B (ko) * 1991-03-15 1993-04-01 Gold Star Co

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60116167A (ja) * 1983-11-29 1985-06-22 Toshiba Corp 半導体記憶装置及びその製造方法
JPS60152058A (ja) * 1984-01-20 1985-08-10 Toshiba Corp 半導体記憶装置
JPH0618257B2 (ja) * 1984-04-28 1994-03-09 富士通株式会社 半導体記憶装置の製造方法
JPS6159866A (ja) * 1984-08-31 1986-03-27 Hitachi Ltd Ｍｏｓ形ダイナミツクメモリおよびその製造方法
JPS61183952A (ja) * 1985-02-09 1986-08-16 Fujitsu Ltd 半導体記憶装置及びその製造方法
JPS62122268A (ja) * 1985-11-22 1987-06-03 Fuji Photo Film Co Ltd 固体撮像素子
US4801989A (en) * 1986-02-20 1989-01-31 Fujitsu Limited Dynamic random access memory having trench capacitor with polysilicon lined lower electrode
DE3780840T2 (de) * 1986-03-03 1993-03-25 Fujitsu Ltd Einen rillenkondensator enthaltender dynamischer speicher mit wahlfreiem zugriff.
US4707457A (en) * 1986-04-03 1987-11-17 Advanced Micro Devices, Inc. Method for making improved contact for integrated circuit structure
JPS6338252A (ja) * 1986-08-04 1988-02-18 Fujitsu Ltd ダイナミツクランダムアクセスメモリセルの形成方法
JPS6367771A (ja) * 1986-09-09 1988-03-26 Mitsubishi Electric Corp 半導体記憶装置
JP2559397B2 (ja) * 1987-03-16 1996-12-04 株式会社日立製作所 半導体集積回路装置及びその製造方法
JPS63268258A (ja) * 1987-04-24 1988-11-04 Nec Corp 半導体装置
JPS63281457A (ja) * 1987-05-13 1988-11-17 Hitachi Ltd 半導体メモリ
US4859619A (en) * 1988-07-15 1989-08-22 Atmel Corporation EPROM fabrication process forming tub regions for high voltage devices

Also Published As

Publication number Publication date
US5111275A (en) 1992-05-05
KR930000599B1 (ko) 1993-01-25
JPH01165160A (ja) 1989-06-29
JPH06105773B2 (ja) 1994-12-21

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