KR880001052A - 세라믹 다층 회로판 및 반도체 모듈 - Google Patents

세라믹 다층 회로판 및 반도체 모듈 Download PDF

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KR880001052A
KR880001052A KR870005624A KR870005624A KR880001052A KR 880001052 A KR880001052 A KR 880001052A KR 870005624 A KR870005624 A KR 870005624A KR 870005624 A KR870005624 A KR 870005624A KR 880001052 A KR880001052 A KR 880001052A
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ceramic
multilayer circuit
wiring conductor
conductor layer
layer
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KR930000881B1 (ko
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노부유끼 우시후사
히로이찌 시노하라
고우세이 나가야마
사또루 오기하라
다사오 소가
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미다 가쓰시게
가부시기 가이샤 히다찌 세이사꾸쇼
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    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C3/00—Glass compositions
    • C03C3/04—Glass compositions containing silica
    • C03C3/062—Glass compositions containing silica with less than 40% silica by weight
    • C03C3/064—Glass compositions containing silica with less than 40% silica by weight containing boron
    • C03C3/066—Glass compositions containing silica with less than 40% silica by weight containing boron containing zinc
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C3/00—Glass compositions
    • C03C3/04—Glass compositions containing silica
    • C03C3/076—Glass compositions containing silica with 40% to 90% silica, by weight
    • C03C3/089—Glass compositions containing silica with 40% to 90% silica, by weight containing boron
    • C03C3/091—Glass compositions containing silica with 40% to 90% silica, by weight containing boron containing aluminium
    • C03C3/093—Glass compositions containing silica with 40% to 90% silica, by weight containing boron containing aluminium containing zinc or zirconium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49158—Manufacturing circuit on or in base with molding of insulated base
    • Y10T29/4916—Simultaneous circuit manufacturing

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Compositions Of Oxide Ceramics (AREA)

Abstract

내용 없음

Description

세라믹 다층 회로판 및 반도체 모듈
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 및 제2도는 본 발명의 일실시예를 나타내는 반도체 모듈의 종단면도이다.

Claims (12)

  1. 세라믹층 및 배선 도체층을 교대로 적층한 세라믹 다층 회로판에 있어서, 상기 세라믹 층은 이의 열팽창 계수가 배선 도체의 열팽창 계수보다 낮고 도체층의 열팽창 계수의 1/2이상이며, 상기배선 도체층의 융점 이하의 온도에서 연화하는 유리로부터 형성된 것을 특징으로 하는 세라믹 다층 회로판.
  2. 제1항에 있어서, 세라믹 층은 이의 열 팽창계수가 7.2×10-6/℃이하이고, 1MHZ에서의 비유전율은 4.5이며, 배선 도체층은 금 또는 은 또는 동중 어느 것으로 부터 형성된 세라믹 다층회로판.
  3. 제1항에 있어서, 세라믹 층은 각기 중량으로 S1o220 내지 95%와 Al2O325%이하,MgO 15 내지 25%, B2O350%이하, ZnO 15내지 25%, CaO 10 내지 25% 및 Li2O|4내지 20% 중에서 선택된 적어도 1종을 함유하고 배선도체층의 융점 이하의 온도에서 연화하는 유리로부터 형성된 세라믹 다층 회로판.
  4. 제1항에 있어서, 세라믹층은 이의 열팽창 계수가 배선 도체층의 열팽창 계수보다 낮고, 배선도체층 열팽창 계수의 1/2이상이며, 배선도체층의 융점 이하의 온도에서 연화하는 유리에 분산된 입경 100㎛이하의 중공실리카로된 세라믹 다층 회로판.
  5. 제4항에 있어서, 중공 실리카 미소구의 함량은 세라믹 층의 35내지 60 용적 %인 세라믹 다층 회로판.
  6. 세라믹 캐리어 기판에 반도체 소자를 탑재하고, 이기판을 탑재한 세라믹 다층 회로판으로된 반도체 모듈에 있어서, 캐리어 기판 및 다층 회로판은 각기 세라믹 층 및 배선 도체층이 교대로 적층되어 있고, 세라믹 층은 이의 열팽창 계수가 배선 도체층의 열팽창 계수보다 낮고, 배선 도체층 열팽창 계수의 1/2이상이며, 세라믹층은 배선 도체층의 융점이하의 온도에서 연화하는 유리로 된 것을 특징으로 하는 반도체 모듈.
  7. 제6항에 있어서, 세라믹 캐리어 기판 및 반도체 소자는 땜납범프로 접속하고, 상기땜납 범프는 유리 수지로 피복된 것인 반도체 모듈.
  8. 제7항에 있어서, 유기수지는 수지 100중량부, 고무입자 5 내지 10중량부 및 세라믹 분말 35 내지 60용적 %를 함유 하는 반도체 모듈.
  9. 제8항에 있어서, 고무 입자는 폴리부타디엔 및 실리콘 고무중에서 선택된 1종 이상으로 되고 세라믹 분말은 석영, 실리콘 카바이드, 실리콘 니트리드, 탄산칼슘 및 베릴륨을 함유한 실리콘 카바이드중에서 선택된 1종 이상으로된 반도체 모듈.
  10. 각기 중량으로 SiO220 내지 95%와 Al2O325%이하, Mgo 15 내지 25%, B2O350%이하, ZnO 15 내지 25%, CaO 10 내지 25% 및 Li2O 4 내지 20% 중에서 선택된 1종 이상을 함유하는 조성을 갖는 세라믹 다층회로판용 비정질 유리 분말.
  11. 제10항에 있어서, 중공 실리카(미소구)의 함유량을 소성후 세라믹 층의 35 내지 65용적%가 되도록 하는 세마릭 다층 회로판용 비정질 유리 분말.
  12. 제10항에 있어서, 960℃이하의 온도에서 연화하는 세라믹 다층 회로판용 비정질 유리 분말.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019870005624A 1986-06-06 1987-06-03 세라믹 다층 회로판 및 반도체 모듈 KR930000881B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP86-130136 1986-06-06
JP61130136A JPS62287658A (ja) 1986-06-06 1986-06-06 セラミックス多層回路板
JP130136 1986-06-16

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KR880001052A true KR880001052A (ko) 1988-03-31
KR930000881B1 KR930000881B1 (ko) 1993-02-08

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US (2) US4821142A (ko)
JP (1) JPS62287658A (ko)
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US4821142A (en) 1989-04-11
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