JPH0544190B2 - - Google Patents

Info

Publication number
JPH0544190B2
JPH0544190B2 JP1242082A JP24208289A JPH0544190B2 JP H0544190 B2 JPH0544190 B2 JP H0544190B2 JP 1242082 A JP1242082 A JP 1242082A JP 24208289 A JP24208289 A JP 24208289A JP H0544190 B2 JPH0544190 B2 JP H0544190B2
Authority
JP
Japan
Prior art keywords
ceramic
multilayer circuit
circuit board
thermal expansion
ceramic multilayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1242082A
Other languages
English (en)
Japanese (ja)
Other versions
JPH02119164A (ja
Inventor
Nobuyuki Ushifusa
Koichi Shinohara
Kosei Nagayama
Satoru Hagiwara
Tasao Soga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1242082A priority Critical patent/JPH02119164A/ja
Publication of JPH02119164A publication Critical patent/JPH02119164A/ja
Publication of JPH0544190B2 publication Critical patent/JPH0544190B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4673Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
    • H05K3/4676Single layer compositions

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
JP1242082A 1989-09-20 1989-09-20 半導体モジユール Granted JPH02119164A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1242082A JPH02119164A (ja) 1989-09-20 1989-09-20 半導体モジユール

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1242082A JPH02119164A (ja) 1989-09-20 1989-09-20 半導体モジユール

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP61130136A Division JPS62287658A (ja) 1986-06-06 1986-06-06 セラミックス多層回路板

Publications (2)

Publication Number Publication Date
JPH02119164A JPH02119164A (ja) 1990-05-07
JPH0544190B2 true JPH0544190B2 (ko) 1993-07-05

Family

ID=17084023

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1242082A Granted JPH02119164A (ja) 1989-09-20 1989-09-20 半導体モジユール

Country Status (1)

Country Link
JP (1) JPH02119164A (ko)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5214006A (en) * 1991-02-05 1993-05-25 Indresco Inc. Cement-free silicon carbide monoliths
TW201842008A (zh) * 2017-03-15 2018-12-01 日商住友電木股份有限公司 樹脂片、疊層樹脂片及樹脂組成物

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55128899A (en) * 1979-03-23 1980-10-06 Ibm Method of fabricating glass ceramic structure
JPS5815264A (ja) * 1981-07-21 1983-01-28 Nec Corp マルチチツプパツケ−ジ
JPS5843553A (ja) * 1981-09-08 1983-03-14 Nec Corp マルチチツプlsiパツケ−ジ
JPS58137294A (ja) * 1982-02-09 1983-08-15 株式会社日立製作所 電気的相互接続パツケ−ジの製造方法
JPS59107596A (ja) * 1982-12-13 1984-06-21 株式会社日立製作所 セラミツク多層配線回路板
JPS6010698A (ja) * 1983-06-29 1985-01-19 日本電気株式会社 多層配線基板およびその製造方法
JPS6027191A (ja) * 1983-07-25 1985-02-12 株式会社日立製作所 ガラスセラミツクス多層配線基板の積層法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55128899A (en) * 1979-03-23 1980-10-06 Ibm Method of fabricating glass ceramic structure
JPS5815264A (ja) * 1981-07-21 1983-01-28 Nec Corp マルチチツプパツケ−ジ
JPS5843553A (ja) * 1981-09-08 1983-03-14 Nec Corp マルチチツプlsiパツケ−ジ
JPS58137294A (ja) * 1982-02-09 1983-08-15 株式会社日立製作所 電気的相互接続パツケ−ジの製造方法
JPS59107596A (ja) * 1982-12-13 1984-06-21 株式会社日立製作所 セラミツク多層配線回路板
JPS6010698A (ja) * 1983-06-29 1985-01-19 日本電気株式会社 多層配線基板およびその製造方法
JPS6027191A (ja) * 1983-07-25 1985-02-12 株式会社日立製作所 ガラスセラミツクス多層配線基板の積層法

Also Published As

Publication number Publication date
JPH02119164A (ja) 1990-05-07

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