JPS59151443A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS59151443A
JPS59151443A JP58025858A JP2585883A JPS59151443A JP S59151443 A JPS59151443 A JP S59151443A JP 58025858 A JP58025858 A JP 58025858A JP 2585883 A JP2585883 A JP 2585883A JP S59151443 A JPS59151443 A JP S59151443A
Authority
JP
Japan
Prior art keywords
package
conductor
solder
conductor pins
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58025858A
Other languages
English (en)
Inventor
Masahiro Sugimoto
杉本　正浩
Tetsushi Wakabayashi
哲史 若林
Kiyoshi Muratake
村竹　清
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58025858A priority Critical patent/JPS59151443A/ja
Priority to EP84300895A priority patent/EP0117111B1/en
Priority to DE8484300895T priority patent/DE3484540D1/de
Publication of JPS59151443A publication Critical patent/JPS59151443A/ja
Priority to US07/006,347 priority patent/US4724472A/en
Pending legal-status Critical Current

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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 （ａ）　　発明の技術分野 本発明は半導体装置、特に高密度実装が可能な半導体装
置の構造に関する。
（ｂｌ　　従来技術と問題点 近年、ＩＣやＬＳＩなどの半導体集積回路を収容する容
器としてリードレスパッケージが用いられている。この
パッケージは通常の外部リードを有する型のパッケージ
と同じく内部にＩＣチップを収納してワイヤーボンデン
グされている。そのため、汎用化された組立法を採るこ
とができ、且つ外部リードの代わり□に接続用の導体パ
ッドが設けられてコンパクトな構造となっており、別名
をチップ′キャリヤと呼ばれている。
従うて、このようなパッケージは回路基板（プリント基
板）上で他のパッケージより一層高密度実装することが
できＪ≠のために重宝がられて各方面で利用が活発化し
ている構造である。
第１図はこのパッケージ１を回路基板２に装着した一実
施例の構造−面図を示乙て゛おり、１１は　・ＩＣＣチ
ンブ、１２は導体パッド、１３はキャップ。
１４は放熱板で、本例は発□熱量の大きいＩＣの構造を
示したものである。また、第２図は第１図に示すパッケ
ージ１の回路基板２側がら見た平面図を示しており、図
示の□ように多数の導体パッド１２が設けられていて、
パッド数は例えばＬＳＩでは２００〜３００個にも及ぶ
゛多数個となる。このようなリードレスパンケージは、
第１図に示すように回路基板２に設ばられた接続用電極
２１とパッケージ１の導体パン″Ｆ′１２とが半田３（
半田の厚みは約５０μｍ）で接合され、回路基板に装着
される。
ところで、第１図のように装着すると、回路の動作中に
熱シラツクが加わった場合に、半田接合部分で欠損が生
じることがある。欠損とは半田３にクラックが入つそ外
れたり、ある％Ｎは回路基板２から接続用電極２１が剥
離したりすることで、かような欠損は、回路基板２に形
成された電子回路の動作を不能にする致命傷になること
は言うまでもない、この欠損の主因は回路基板２がエポ
キシやポリイミドなどの有機樹□脂製であって熱膨張率
が大きく、一方のパッケージ、１はセラミック製で熱膨
張率が小さいため、半田接合部分にストレス（歪）が加
わって破壊されるものである。
この場合、回路基板２をパッケージ１と同じ材質のセラ
ミック基板にすれば、ストレスがなくなって破壊されな
いが、セラミック基板は誘電率が高い為に電子回路の動
作を遅延させる悪影響があって好ましくなく、特殊な場
合を除いてはセラミック基板は殆ど用いられない。
（ｃｌ　　発明の目的 本発明は上記の問題点を解消させるための半導体装置を
提案するものである。
（ｃｌｌ　　発明の構成 その目的は、半導体素子を収容するパッケージの外面に
形成され鼻複数の導体パッド□と、該導体パッドに鑞づ
けされ、且つ被接続外部導体に当接して接続されるよう
にした導体ピンまたは導体ボールを具備してなる半導体
装置によって達成することができる。
ｉｅ＋　　発明の実施例゛ 以下９図面を参照して実施例によって詳細に説明する。
第３図は本発明にかかる一実施例の断面図で、図示のよ
うにパッケージ１のすべての導体パッド１２に導体ピン
４を鑞づけしておく。かくして、第４図に示すように回
路基板２の接続用電極２１と導体ピン４とを半田づけす
る。そうすれば、回路基板２上の電子回路を動作させた
り中止したりして、加熱と冷却とが繰り返され熱シラ１
ンクが加わっても、導体パッドと電極との接続部分で欠
損を生じることはなくなる。
第５図はその接続部分の拡大図を示している。
パッケージ１の導体パッド１２はセラミック基板を積層
し焼結する際にメタライズ層として形成されるが、この
メタライズｉｉ←導体ピン４を銀鑞５で鑞づけしておき
、表面をニッケルと金で鍍金したものとする。そして、
導体パッド１ｚの広さを０．２〜０．２５目角とすれば
、これに長さ０．５〜１．５鶴、直径０．１〜０．２ｆ
ｉ程度の導体ピンを鑞づけし、導体ヂンと回路基板２の
電極２１とは半田６で接合する。一方、電極２１は銅層
に半田鍍金されたものである。また、導体ピンはコバー
ル９．タングステン、モリブデンまたは銅合金などのバ
ネ材で作成される。このような構造にすれば、ストレス
はこのビンで吸収されるから熱ストレスによる破壊は防
止される。
、次に、第６図は本発明にかかる他の実施例の断面図で
、パッケージ１のすべての導体、パッド１２に導体ボー
ル７が鑞づけしてあり、導体ボール７の直径は０．２１
程度、その材質は銅、銀、金またはそれらの合金で、柔
らかい材料牽用いる。パッケージ１と回路基板２との接
続図は図示していないが、第７図に接続部分の拡大図を
示している。
パッケージ１の導体パッド１２に導体ボール７を鑞づけ
し、導体ピンと回路基板２の電極２１とは半田６で接合
する。このような構造にすれば、ストレスは上記例と同
様にこの導体ボールで吸収することができる。
上記の実施例は発熱量の大きいＩＣの例であるが、ロジ
ック回路用など一般のＩＣは第８図に示すようなパッケ
ージ裏面全体に導体パッド１２が設けられており、これ
に図示のように導体ピン４を鑞づけした構造、あるいは
導体ボール７を鑞づけした構造にすれば同様にストレス
を除去して破壊を防止することができる。
（ｆ）　　発明の効果□ 以上の説明から明らかなように、本発明によればパッケ
ージ外面に形成された導体パッドに導体ピンあるいは導
体ボールを取りつけて熱シロツクの緩衝帯とするために
、熱ショックにより半田接合部が欠損することなく、電
子回路の信頼性が向上するものである。
【図面の簡単な説明】
第１図は従来のパッケージを回路基板に装着した構造断
面図例、第２図はそのパッケージの平面図、第３図、第
６図および第８図は本発明にかかるパッケージの断面図
、第４図は本発明のパッケージを回路基板に装着した構
造断面図、第５図および第７図は接続部分の拡大図であ
る。 図中、ｌはパッケージ、２は回路基板、３．６は半田、
４は導体ビン、５は銀鑞、７は導体ボール、１２は導体
パッド、２１は接ｉ用の電極を示している。 第８図 手続補正書輸発） 昭和　　　年　　　月　　　　１１ ５９．３．２８ 庁長官殿 、の表示 夕と年特許願第２タ？タ？シ２ ２、発明の名称半導体装置 する者 ｔとの関係　　　　　特許出馳人 住所　神奈川県用崎市中原区１−／１・１１１中１０１
５番地（５２２）名称富士通株式会社 浬　　人　　　　　住所　神奈川県用崎市中原区１−小
Ｉ川す０１５洛地本願の特許請求の範囲を次のとおり補
正する。 「半導体素子を収容するパッケージの外面に形成された
複数の導体パッドと、該導体パッドに立設さ体ピンを具
備してなることを特徴とする半導体装置。」２− １８５−

Claims (1)

    【特許請求の範囲】
  1. 半導体素子を収容するパッケージの外面に形成された複
    数の導体バッドと、該導体バッドに鑞づけされ、且つ被
    接続外部導体に当接して接続されるようにした導体ビン
    または導体ボールを具備してなることを特徴とする半導
    体装置。
JP58025858A 1983-02-17 1983-02-17 半導体装置 Pending JPS59151443A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP58025858A JPS59151443A (ja) 1983-02-17 1983-02-17 半導体装置
EP84300895A EP0117111B1 (en) 1983-02-17 1984-02-13 Semiconductor device assembly
DE8484300895T DE3484540D1 (de) 1983-02-17 1984-02-13 Halbleiteranordnungszusammenbau.
US07/006,347 US4724472A (en) 1983-02-17 1987-01-14 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58025858A JPS59151443A (ja) 1983-02-17 1983-02-17 半導体装置

Publications (1)

Publication Number Publication Date
JPS59151443A true JPS59151443A (ja) 1984-08-29

Family

ID=12177513

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58025858A Pending JPS59151443A (ja) 1983-02-17 1983-02-17 半導体装置

Country Status (4)

Country Link
US (1) US4724472A (ja)
EP (1) EP0117111B1 (ja)
JP (1) JPS59151443A (ja)
DE (1) DE3484540D1 (ja)

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JPH0363943U (ja) * 1989-10-26 1991-06-21
KR100416838B1 (ko) * 2001-06-29 2004-02-05 주식회사 하이닉스반도체 반도체의 패키지장치 및 그 방법

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JPH01217993A (ja) * 1988-02-26 1989-08-31 Hitachi Ltd 半導体装置
JP2509285B2 (ja) * 1988-03-18 1996-06-19 富士通株式会社 半導体装置の試験方法
JPH0756887B2 (ja) * 1988-04-04 1995-06-14 株式会社日立製作所 半導体パッケージ及びそれを用いたコンピュータ
JP2548602B2 (ja) * 1988-04-12 1996-10-30 株式会社日立製作所 半導体実装モジュール
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JPH0363943U (ja) * 1989-10-26 1991-06-21
KR100416838B1 (ko) * 2001-06-29 2004-02-05 주식회사 하이닉스반도체 반도체의 패키지장치 및 그 방법

Also Published As

Publication number Publication date
EP0117111A2 (en) 1984-08-29
EP0117111B1 (en) 1991-05-08
US4724472A (en) 1988-02-09
DE3484540D1 (de) 1991-06-13
EP0117111A3 (en) 1986-03-26

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