KR840003921A - 반도체 장치와 그 제조방법 - Google Patents

반도체 장치와 그 제조방법 Download PDF

Info

Publication number
KR840003921A
KR840003921A KR1019830000433A KR830000433A KR840003921A KR 840003921 A KR840003921 A KR 840003921A KR 1019830000433 A KR1019830000433 A KR 1019830000433A KR 830000433 A KR830000433 A KR 830000433A KR 840003921 A KR840003921 A KR 840003921A
Authority
KR
South Korea
Prior art keywords
tab
leads
package body
semiconductor device
lead
Prior art date
Application number
KR1019830000433A
Other languages
English (en)
Other versions
KR900001989B1 (ko
Inventor
마사치가 마스다 (외 1)
Original Assignee
미쓰다 가쓰시게
가부시기 가이샤 히다찌 세이사꾸쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP57016232A external-priority patent/JPS58134452A/ja
Priority claimed from JP57016233A external-priority patent/JPS58134453A/ja
Application filed by 미쓰다 가쓰시게, 가부시기 가이샤 히다찌 세이사꾸쇼 filed Critical 미쓰다 가쓰시게
Publication of KR840003921A publication Critical patent/KR840003921A/ko
Priority to KR1019900000785A priority Critical patent/KR900001988B1/ko
Application granted granted Critical
Publication of KR900001989B1 publication Critical patent/KR900001989B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

내용 없음

Description

반도체 장치와 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제도1는 본 발명 하나의 실시예에 따른 반도체 장치의 사시도,
제3도는 제2도에 도시한 반도체 장치의 일부를 잘라내고 표시한 사시도이다.

Claims (14)

  1. 4각형의 패케이지 본체와, 상기 패케이지 본체의 4개변의 각각에서 돌출되는 다수개의 리이드와, 그리고 상기 패케이지 본체의 최소한 1개의 모서리에 설치된 각 제거부(角除去部)와, 그리고 또 상기 각 제거부로부터 돌출되는 리이드와를 갖는 반도체 장치.
  2. 상기의 패케이지 본체의 4개변의 각각으로부터 돌출되는 다수개의 리이드와, 각 제거부로부터 돌출되는 리이드는 패케이지 본체의 중심에 대하여 대칭이 되도록 배치되어 있는 것을 특징으로 하는 특허청범위 1의 반도체 장치.
  3. 상기의 패케이지 본체가 레진으로 되어 있는 것을 특징으로 하는 특허청구범위 1의 반도체 장치.
  4. 상기 패케이지 본체의 4개변의 각각으로부터 돌출되는 다수개의 리이드와 각 제거부로부터 돌출되는 리이드는 단이지게 절곡되어 있는 것을 특징으로 하는 특허청구 1범 위의반도체 장치.
  5. 반도체 소자펠렛을 고착하는 탭과, 상기 탭의 주위에 배치되어 있는 다수개의 리이드와, 그리고 상기 탭과 다수개의 리이드를 연결하는 4각형 모양의 댐과, 그리고 또 상기의 댐. 다수개의 리이드ㆍ탭들을 일체가 되게 지지하는 프레임과, 또 상기의 4각형 모양의 댐의 인덱스 형성부에 배치된 리이드를 갖는 것을 특징으로 하는 리이드 프레임.
  6. 상기 인덱스 형성부에 배치되어 있는 리이드는 상기의 탭 근방까지 연장되어 있는 것을 특징으로 하는 특허청구 범위 5의 리이드 프레임.
  7. 상기의 탭에 4각형 모양인 것을 특징으로 하는 특허청구범위 5의 리이드 프레임.
  8. 중앙에 배치되고 반도체 소자를 고착하는 탭과, 이 탭의 주변에 배치된 다수개의 리이드와, 그리고 패케이지 본체의 인덱스부에 해당하는 부위에 배치된 리이드와를 갖는 것을 특징으로 하는 리이드 프레임
  9. 상기의 패케이지 본체의 인덱스부에 해당하는 부위는 4각형으로 형성되는 패케이지 본체의 1개의 모서리 부분에 설치된 각 제거부에 해당하는 위치인 것을 특징으로 하는 특허청구범위 8의 리이드 프레임.
  10. 상기의 탭은 4각형 모양인 것을 특징으로 하는 특허청구범위 8의 리이드 프레임.
  11. 반도체 소자를 고착하는 탭과, 이 탭의 주변에 배치된 다수개의 리이드와, 패케이지 본체의 인텍스에 해당하는 부위에 배치된 리이드와를 갖는 리이드 프레임을 준비하는 공정과, 상기의 탭위에다 반도체 소자를 고착하는 공정과, 그리고, 상기 반도체 소자와 다수개의 리이드를 전기적으로 접속하는 공정과 그리고, 또 상기의 탭, 반도체소자 다수개의 리이드의 일부분을 레진으로 몰딩하는 공정과에 의하여 되는 반도체 장치의 제조방법.
  12. 상기의 리이드 프레임은 금속의 얇은 판을 펀칭하여서 형성되는 것을 특징으로 하는 특허청구범위 11의 반도체 장치의 제조방법.
  13. 상기의 반도체 소자와 다수개의 리이드와의 사이를 와이어에 의하여 접속되는 것을 특징으로 하는 특허청구범위 11의 반도체 장치의 제조방법.
  14. 상기의 레진으로 몰딩을 한 다음에 댐의 절단을 하는 것을 특징으로 하는 특허청구범위 11의 반도체 기억장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019830000433A 1982-02-05 1983-02-04 반도체장치 KR900001989B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900000785A KR900001988B1 (ko) 1982-02-05 1990-01-24 반도체장치에 사용되는 리이드 프레임

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP57-16232 1982-02-05
JP57-16232-3 1982-02-05
JP57016232A JPS58134452A (ja) 1982-02-05 1982-02-05 半導体装置およびその製造方法
JP57-16233 1982-02-05
JP57016233A JPS58134453A (ja) 1982-02-05 1982-02-05 リ−ドフレ−ム

Publications (2)

Publication Number Publication Date
KR840003921A true KR840003921A (ko) 1984-10-04
KR900001989B1 KR900001989B1 (ko) 1990-03-30

Family

ID=26352512

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019830000433A KR900001989B1 (ko) 1982-02-05 1983-02-04 반도체장치

Country Status (7)

Country Link
KR (1) KR900001989B1 (ko)
DE (1) DE3303165C2 (ko)
GB (1) GB2115220B (ko)
HK (1) HK70787A (ko)
IT (1) IT1161869B (ko)
MY (1) MY8700616A (ko)
SG (1) SG36287G (ko)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60140742A (ja) * 1983-12-06 1985-07-25 フエアチアイルド　カメラ　アンド　インストルメント　コーポレーシヨン リードフレーム及びその実装方法
US4677526A (en) * 1984-03-01 1987-06-30 Augat Inc. Plastic pin grid array chip carrier
JP2634516B2 (ja) * 1991-10-15 1997-07-30 三菱電機株式会社 反転型ｉｃの製造方法、反転型ｉｃ、ｉｃモジュール
US6225685B1 (en) * 2000-04-05 2001-05-01 Advanced Micro Devices, Inc. Lead frame design for reduced wire sweep having a defined gap between tie bars and lead pins

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3926746A (en) * 1973-10-04 1975-12-16 Minnesota Mining & Mfg Electrical interconnection for metallized ceramic arrays
US4089575A (en) * 1976-09-27 1978-05-16 Amp Incorporated Connector for connecting a circuit element to the surface of a substrate
JPS5479563A (en) * 1977-12-07 1979-06-25 Kyushu Nippon Electric Lead frame for semiconductor
EP0016522B1 (en) * 1979-02-19 1982-12-22 Fujitsu Limited Semiconductor device and method for manufacturing the same
US4195193A (en) * 1979-02-23 1980-03-25 Amp Incorporated Lead frame and chip carrier housing
US4289922A (en) * 1979-09-04 1981-09-15 Plessey Incorporated Integrated circuit package and lead frame

Also Published As

Publication number Publication date
IT1161869B (it) 1987-03-18
KR900001989B1 (ko) 1990-03-30
GB2115220B (en) 1985-11-06
HK70787A (en) 1987-10-09
GB2115220A (en) 1983-09-01
IT8319414A0 (it) 1983-02-03
MY8700616A (en) 1987-12-31
DE3303165C2 (de) 1993-12-09
DE3303165A1 (de) 1983-09-22
SG36287G (en) 1987-07-24
GB8302730D0 (en) 1983-03-02

Similar Documents

Publication Publication Date Title
EP0015111B1 (en) Lead frame and housing for integrated circuit
KR850700086A (ko) 집적회로
KR880001051A (ko) 히트싱크에 부착사용하는 유연한 세그먼트 패키지속에 장치된 반도체장치
KR930014916A (ko) 반도체 패키지
US4987473A (en) Leadframe system with multi-tier leads
KR960002711A (ko) 전자 부품 및 그 제조 방법
KR970701430A (ko) 교차하는 본딩 와이어의 취급용 리드 프레임(lead frame for handling crossing bonding wires)
KR840003921A (ko) 반도체 장치와 그 제조방법
KR880008446A (ko) 리드프레임과 그 제조방법
JPS63296252A (ja) 樹脂封止型半導体装置
JP3136029B2 (ja) 半導体装置
JPS6230496B2 (ko)
JPH0228966A (ja) 半導体装置
JPH0529527A (ja) 半導体装置
KR950034719A (ko) 리드 프레임 및 이 리드 프레임을 포함한 패키지 디바이스 제조 방법
KR900001988B1 (ko) 반도체장치에 사용되는 리이드 프레임
JPH02253646A (ja) リードフレーム
JPS58112356A (ja) リ−ドフレ−ム
JPS5821180Y2 (ja) 半導体装置
JPS5918866B2 (ja) 集積回路装置
JPS6351542B2 (ko)
KR20020035284A (ko) 칩 스케일 패키지용 스트립
JPS5887837A (ja) 半導体装置
JPS5923553A (ja) 半導体装置の製造方法
JPH0555449A (ja) リードフレーム

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20020325

Year of fee payment: 13

EXPY Expiration of term