KR960002711A - 전자 부품 및 그 제조 방법 - Google Patents

전자 부품 및 그 제조 방법 Download PDF

Info

Publication number
KR960002711A
KR960002711A KR1019950016821A KR19950016821A KR960002711A KR 960002711 A KR960002711 A KR 960002711A KR 1019950016821 A KR1019950016821 A KR 1019950016821A KR 19950016821 A KR19950016821 A KR 19950016821A KR 960002711 A KR960002711 A KR 960002711A
Authority
KR
South Korea
Prior art keywords
electronic component
leads
lead frame
primary
outer edge
Prior art date
Application number
KR1019950016821A
Other languages
English (en)
Other versions
KR100200377B1 (ko
Inventor
슈이치 스기모토
신지 나카무라
모토나리 후지카와
유이 다다
Original Assignee
다테이시 요시오
오므론 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 다테이시 요시오, 오므론 가부시키가이샤 filed Critical 다테이시 요시오
Publication of KR960002711A publication Critical patent/KR960002711A/ko
Application granted granted Critical
Publication of KR100200377B1 publication Critical patent/KR100200377B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명의 목적은 리드 프레임상에 실장된 전자부품 소자를 서지 등으로부터 보호하고, 안전 또는 성는이 우수한 수지 성형의 전자 부품을 간단히 제조하는데 있다.
장단 2개의 수지지지핀(8a,8b)등을 소정 패턴의 리드 프레임(3)으로 가공해 현수핀(10)에 의해 리드 프레임 외측 테두리(3a)에 지지된 다이 패드(5)상에 전자 부품 소자(2)를 다이 본딩한다. 수지 지지판(8a,8b)의 단부를 덮도록 밀봉 성형해서 내부성형 수지부(11)를 성형한다. 이때, 돌기부(11a)에 의해서 짧은 수지 지지핀(8b)의 단부를 덮도록 한다. 노출된 현수핀(10)부분을 절제하는 동안, 내부성형 수지부(11)를 덮도록 해서 외부성형 수지부(12)를 밀봉 성형하고 최종적으로 긴 수지지지핀(8a) 및 (11a)를 절단해서 전자 부품(1)을 제작한다.

Description

전자 부품 및 그 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 일실시예인 전자부품을 도시한 외관 사시도,
제2도는 (a)-(c)는 상술한 전자 부품의 제조방법을 도시한 설명도.

Claims (5)

  1. 전자 부품 소자가 장착된 다이 패드와 입출력용 단자등의 리드류 및 이들 리드류를 유지하는 리드 프레임 외측 테두리를 갖는 리드 프레임의 상기 리드류를 수지 밀봉하는 단계와, 성형 부재에 의해 밀봉 성형된 전자부품을 리드 프레임 외측 테두리에서 떼어내는 단계에 의해 전자 부품을 제조하는 방법에 있어서, 리드 프레임 외측 테두리에 상기 리드류를 저지하는 현수핀과, 상기 리드류에는 접속되지 않는 1차 몰드 유지부를 제공하는 단계와; 상기 리드류 및 상기 1차 몰드유지부에 1차 성형 부재를 수지 성형하는 단계에 의해 상기 리드류 및 상기 1차 몰드 유지부를 1차 성형 부재에 연결하는 단계와; 상기 현수핀을 상기 1차 성형 부재와 상기 프레임 외측 테두리와의 사이에서 절단하는 단계와; 상기 현수핀의 절단개소를 덮고 1차 성형 부재에 2차 성형 부재를 수지 성형하는 단계와; 상기 1차 몰드 유지부를 2차 성형 부재와 상기 리드 프레임 외측 테두리와의 사이에서 절단하는 단계에 의해 전자부품을 리드 프레임 외측 테두리에서 떼어내는 단계를 포함하는 것을 특징으로 하는 전자 부품의 제조 방법.
  2. 전자 부품 소자가 장착된 다이 패드와 입출력용 단자등의 리드류 및 이들 리드류를 유지하는 리드 프레임 외측 테두리를 갖는 리드 프레임의 상기 리드류를 수지 밀봉하는 단계와, 성형 부재에 의해 밀봉 성형된 전자 부품을 리드 프레임 외측 테두리에서 떼어내는 단계에 의해 전자 부품을 제조하는 방법에 있어서, 리드 프레임 외측 테두리에 상기 리드류를 지지하는현수핀과, 상기 리드류에는 접속되지 않는 1차 몰드 유지부를 제공하는 단계와; 상기 리드류 및 상기 1차 몰드유지부에 1차 성형 부재를 수지 성형하는 단계에 의해 상기 리드류 및 상기 1차 몰드 유지부를 1차 성형 부재에 연결하는 단계와; 상기 현수핀을 상기 1차 성형 부재와 상기 프레임 외측 테두리와의 사이에서 절단하는 단계와; 상기 현수핀의 절단개소를 덮고 1차 성형부재에 2차 성형 부재를 수지 성형하는 단계와; 상기 1차 몰드 유지부를 1차 성형 부분과 분리하거나 또는 입출력용 단자 이외의 리드류를 노출시키지 않도록 상기 1차 성형 부재 또는 상기 1차 및 2차 성형 부재를 절단하는 단계에 의해 전자 부품을 리드 프레임 외측 테두리에서 떼어내는 단계를 포함하는 것을 특징으로 하는 전자 부품의 제조방법.
  3. 리드 프레임에서 형성되어 전자 부품의 소자가 실장된 도전 부재를 밀봉 성형한 전자 부품에 있어서, 2중 몰드 구조에 의해 입출력용 도전 부재이외의 상기 전자 부품 소자와 전기적으로 접속된 도전 부재가 밀봉 성형 부재의 표면에 노출하지 않는 구조로 된 것을 특징으로 하는 전자 부품.
  4. 전자 부품과; 전자 부품을 외부에 전기적으로 접속하는 접속 단자와; 상기 전자 부품을 지지하는 제1도전 지지 부재와; 제2도전 지지 부재와; 상기 전자 부품의 노출면과, 상기 접속 단자와, 상기 제1도전 지지 부재와, 상기 제2도전 지지 부재를 피복하는 제1절연 부재와; 상기 제1도전 지지 부재의 노출면을 피복하는 제2절연 부재를 포함하고, 상기 제2도전 지지 부재는 상기 전자 부품과 상기 제1도전 지지 부재로 부터 절연되고, 상기 제1절연 부재를 지지하는 구조를 갖는 것을 특징으로 하는 전자 장치.
  5. 제4항에 있어서, 상기 제2도전 지지 부재는 노출되어 있는 것을 특징으로 하는 전자 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950016821A 1994-06-22 1995-06-22 전자부품 및 그 제조방법 KR100200377B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP94-164767 1994-06-22
JP6164767A JPH088280A (ja) 1994-06-22 1994-06-22 電子部品及びその製造方法

Publications (2)

Publication Number Publication Date
KR960002711A true KR960002711A (ko) 1996-01-26
KR100200377B1 KR100200377B1 (ko) 1999-06-15

Family

ID=15799548

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950016821A KR100200377B1 (ko) 1994-06-22 1995-06-22 전자부품 및 그 제조방법

Country Status (3)

Country Link
US (1) US5841187A (ko)
JP (1) JPH088280A (ko)
KR (1) KR100200377B1 (ko)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6215174B1 (en) 1997-01-20 2001-04-10 Matsushita Electronics Corporation Lead frame, mold for producing a resin-sealed semiconductor device, resin-sealed semiconductor device using such a lead frame
JP3562311B2 (ja) * 1998-05-27 2004-09-08 松下電器産業株式会社 リードフレームおよび樹脂封止型半導体装置の製造方法
US6576496B1 (en) * 2000-08-21 2003-06-10 Micron Technology, Inc. Method and apparatus for encapsulating a multi-chip substrate array
DE10058622A1 (de) * 2000-11-15 2002-05-29 Vishay Semiconductor Gmbh Gemouldetes elektronisches Bauelement
DE10058608A1 (de) 2000-11-25 2002-05-29 Vishay Semiconductor Gmbh Leiterstreifenanordnung für ein gemouldetes elektronisches Bauelement und Verfahren zum Moulden
DE10247610A1 (de) * 2002-10-11 2004-04-29 Micronas Gmbh Elektronisches Bauelement mit einem Systemträger
US20040113240A1 (en) 2002-10-11 2004-06-17 Wolfgang Hauser An electronic component with a leadframe
US20070188053A1 (en) * 2006-02-14 2007-08-16 Robert Bosch Gmbh Injection molded energy harvesting device
DE102006028815B3 (de) * 2006-06-21 2007-08-30 Hansa Tronic Gmbh Verfahren zur Herstellung eines elektrischen Hybridbauteils
US7875962B2 (en) * 2007-10-15 2011-01-25 Power Integrations, Inc. Package for a power semiconductor device
JP4758976B2 (ja) * 2007-12-03 2011-08-31 日立ケーブルプレシジョン株式会社 半導体発光素子搭載用リードフレーム及びその製造方法並びに発光装置
US8659132B2 (en) 2008-10-27 2014-02-25 Nxp B.V. Microelectronic package assembly, method for disconnecting a microelectronic package
KR20120048995A (ko) * 2010-11-08 2012-05-16 삼성엘이디 주식회사 발광소자 패키지 제조방법 및 발광소자 패키지 제조용 프레임
CN102437061A (zh) * 2011-11-30 2012-05-02 深圳市威怡电气有限公司 电子元件及其封装方法
JP5525574B2 (ja) * 2012-08-07 2014-06-18 ホシデン株式会社 部品モジュール及び部品モジュールの製造方法
JP6193622B2 (ja) * 2013-05-28 2017-09-06 日本特殊陶業株式会社 配線基板ユニットおよびリード付き配線基板の製造方法
JP6237919B2 (ja) 2014-10-03 2017-11-29 三菱電機株式会社 リードフレーム、半導体装置の製造方法
DE102015208319A1 (de) * 2015-05-05 2016-11-10 Continental Teves Ag & Co. Ohg Leadframe und Verfahren zur Herstellung elektrischer oder elektronischer Bauelemente
US10147672B2 (en) * 2016-04-20 2018-12-04 Texas Instruments Incorporated Lead frame surface modifications for high voltage isolation
JP6231183B2 (ja) * 2016-12-09 2017-11-15 日立オートモティブシステムズ株式会社 物理量測定装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02292835A (ja) * 1989-05-02 1990-12-04 Matsushita Electron Corp 半導体装置の製造方法
JP2712618B2 (ja) * 1989-09-08 1998-02-16 三菱電機株式会社 樹脂封止型半導体装置
US5367196A (en) * 1992-09-17 1994-11-22 Olin Corporation Molded plastic semiconductor package including an aluminum alloy heat spreader
KR970008355B1 (ko) * 1992-09-29 1997-05-23 가부시키가이샤 도시바 수지밀봉형 반도체장치

Also Published As

Publication number Publication date
JPH088280A (ja) 1996-01-12
US5841187A (en) 1998-11-24
KR100200377B1 (ko) 1999-06-15

Similar Documents

Publication Publication Date Title
KR960002711A (ko) 전자 부품 및 그 제조 방법
CA1040747A (en) Integrated circuit package utilizing novel heat sink structure
KR970067810A (ko) 반도체장치 및 그 제조방법
US5275975A (en) Method of making a relatively flat semiconductor package having a semiconductor chip encapsulated in molded material
KR20010105191A (ko) 집적 커패시터를 갖는 홀 효과 센서 소자
KR0178600B1 (ko) 원피스 하우징내에 전기 요소를 성형하는 방법
KR960009136A (ko) 반도체 패키지 및 그 제조방법
JPH026225B2 (ko)
US4298769A (en) Hermetic plastic dual-in-line package for a semiconductor integrated circuit
US4649460A (en) Single-in-line integrated electronic component
KR950025963A (ko) 반도체 장치의 제조방법
JPS63258050A (ja) 半導体装置
JP2001085120A (ja) コネクタ
KR960002775A (ko) 수지-봉합(resin-sealed) 반도체 소자
KR950004512A (ko) 반도체장치 및 그 제조방법
KR970024110A (ko) 반도체 장치 및 그의 제조방법(semiconductor device and method for manufacturing the same)
KR950015728A (ko) 표면 실장형 반도체 장치
JPH0228966A (ja) 半導体装置
KR100201392B1 (ko) 적층형 반도체 패키지 및 그 제조방법
KR840003921A (ko) 반도체 장치와 그 제조방법
KR200155169Y1 (ko) 반도체 패키지 디바이스
JPH0648877Y2 (ja) 半導体装置
KR930011198A (ko) 반도체 패키지
JPH02246143A (ja) リードフレーム
JPH03129840A (ja) 樹脂封止型半導体装置

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20120223

Year of fee payment: 14

FPAY Annual fee payment

Payment date: 20130227

Year of fee payment: 15

LAPS Lapse due to unpaid annual fee