KR20220011807A - 구조체의 제조 방법 및 구조체 - Google Patents
구조체의 제조 방법 및 구조체 Download PDFInfo
- Publication number
- KR20220011807A KR20220011807A KR1020227001488A KR20227001488A KR20220011807A KR 20220011807 A KR20220011807 A KR 20220011807A KR 1020227001488 A KR1020227001488 A KR 1020227001488A KR 20227001488 A KR20227001488 A KR 20227001488A KR 20220011807 A KR20220011807 A KR 20220011807A
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- Prior art keywords
- metal thin
- thin film
- liquid resin
- bonding
- base
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000011347 resin Substances 0.000 claims abstract description 113
- 229920005989 resin Polymers 0.000 claims abstract description 113
- 229910052751 metal Inorganic materials 0.000 claims abstract description 111
- 239000002184 metal Substances 0.000 claims abstract description 111
- 239000010409 thin film Substances 0.000 claims abstract description 111
- 239000007788 liquid Substances 0.000 claims abstract description 49
- 238000009792 diffusion process Methods 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 31
- 238000009499 grossing Methods 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims description 39
- 239000004065 semiconductor Substances 0.000 claims description 37
- 230000003746 surface roughness Effects 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 229910052709 silver Inorganic materials 0.000 claims description 5
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 230000005489 elastic deformation Effects 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 31
- 230000015572 biosynthetic process Effects 0.000 abstract description 10
- 238000010586 diagram Methods 0.000 description 10
- 239000010408 film Substances 0.000 description 7
- 238000004544 sputter deposition Methods 0.000 description 5
- 238000005304 joining Methods 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 4
- 238000007517 polishing process Methods 0.000 description 4
- 239000004925 Acrylic resin Substances 0.000 description 2
- 229920000178 Acrylic resin Polymers 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229920002050 silicone resin Polymers 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- -1 Au and Ag Chemical class 0.000 description 1
- 230000001464 adherent effect Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
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- B—PERFORMING OPERATIONS; TRANSPORTING
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- B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
- B23K20/001—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating by extrusion or drawing
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- B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
- B23K20/02—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating by means of a press ; Diffusion bonding
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- B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
- B23K20/22—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating taking account of the properties of the materials to be welded
- B23K20/233—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating taking account of the properties of the materials to be welded without ferrous layer
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- B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
- B23K20/24—Preliminary treatment
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- B23K2103/00—Materials to be soldered, welded or cut
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- B23K2103/16—Composite materials, e.g. fibre reinforced
- B23K2103/166—Multilayered materials
- B23K2103/172—Multilayered materials wherein at least one of the layers is non-metallic
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Abstract
기체(10, 20)를 원자 확산 접합한 구조체(1)의 제조 방법으로서, 기체(10)의 표면에 액상 수지(11a)를 도포하는 공정과, 액상 수지(11a)의 표면 장력에 의해, 액상 수지(11a)의 표면을 평활화하는 공정과, 액상 수지(11a)를 경화하여 수지층(11)을 형성하는 공정과, 수지층(11)의 표면에 금속 박막(12)을 형성하는 공정과, 기체(20)의 표면에 금속 박막(21)을 형성하는 공정과, 기체(10)의 금속 박막(12)과 기체(20)의 금속 박막(21)을 밀착시켜 원자 확산 접합하는 공정을 포함한다. 이것에 의해, 부재의 박막 형성면이 평활하지 않은 경우라도 원자 확산 접합에 의한 접합을 행할 수 있다.
Description
본 발명은 구조체의 제조 방법 및 구조체에 관한 것으로, 특히, 원자 확산 접합 방법에 의해 제조된 구조체의 제조 방법 및 구조체에 관한 것이다.
복수의 부재를 접합하여 구조체를 제조하는 것이 행해지고 있다. 예를 들면, 반도체 소자와 기판을 접합(적층)하여 반도체 장치를 제조하는 것이 행해지고 있다. 특허문헌 1에는 기판의 표면의 전극을 덮도록 기판의 표면에 수지층을 형성하고, 수지층을 용융시키면서 기판의 전극에 반도체 소자를 접합하는 접합 방법이 기재되어 있다. 이 제조 방법에 의하면, 기판의 전극과 반도체 소자 사이에 이물이 들어가는 것을 억제할 수 있다.
또 최근에는 상기한 접합 방법 이외에 원자 확산 접합에 의한 부재의 접합 방법이 알려져 있다. 원자 확산 접합 방법은 대향하는 한 쌍의 부재의 각 대향면에 금속 박막을 각각 형성하고, 이 금속 박막을 서로 밀착시켜 원자 확산을 발생시킴으로써 부재 사이를 접합하는 접합 방법이다. 이 원자 확산 접합 방법은 상온 접합이 가능하므로, 부재를 가열하지 않고 접합이 가능하며, 열 팽창률이 상이한 이종 재료의 부재의 접합에도 적용할 수 있다. 또 원자 레벨에서 접합하고 있으므로, 접착제가 불필요하며, 강도, 신뢰성, 내구성이 우수하다.
원자 확산 접합 방법은 부재의 표면에 형성된 금속 박막을 개재시켜 부재 사이를 접합하고 있으므로, 금속 박막을 서로 밀착시킬 필요가 있다. 즉, 금속 박막을 형성하는 박막 형성면이 평활할 필요가 있다.
이 때문에, 부재의 박막 형성면이 평활하지 않은 경우, 예를 들면, 부재의 박막 형성면이 조면인 경우에는, 부재의 박막 형성면을 평활하게 하기 위해서, 부재의 표면(박막 형성면)을 연마하는 연마 처리 등이 필요하게 되고, 이 연마 처리가 번잡하고, 또 비용도 발생한다. 또한 부재를 접합하는 금속 박막의 사이에 이물이 존재하면, 부재의 금속 박막의 밀착이 곤란하게 되므로, 원자 확산 접합에 의한 접합도 곤란하게 된다.
그래서, 본 발명에서는 부재의 박막 형성면이 평활하지 않은 경우라도, 원자 확산 접합에 의한 접합을 행하는 것을 목적으로 한다. 또 부재의 금속 박막의 사이에 이물이 존재하는 경우라도, 원자 확산 접합에 의한 접합을 행하는 것을 목적으로 한다.
본 발명의 구조체의 제조 방법은 복수의 부재를 원자 확산 접합한 구조체의 제조 방법으로서, 적어도 하나의 부재의 표면에 액상 수지를 도포하는 공정과, 도포된 액상 수지의 표면 장력에 의해, 액상 수지의 표면을 평활화하는 공정과, 액상 수지를 경화하여 수지층을 형성하는 공정과, 수지층의 표면에 금속 박막을 형성하는 공정과, 다른 부재의 표면에 금속 박막을 형성하는 공정과, 적어도 하나의 부재의 금속 박막과 다른 부재의 금속 박막을 밀착시켜 원자 확산 접합하는 공정을 포함하는 것을 특징으로 한다.
또 본 발명의 구조체의 제조 방법은 복수의 부재를 원자 확산 접합한 구조체의 제조 방법으로서, 복수의 부재의 표면에 액상 수지를 각각 도포하는 공정과, 도포된 액상 수지의 표면 장력에 의해, 액상 수지의 표면을 평활화하는 공정과, 액상 수지를 경화하여 수지층을 형성하는 공정과, 수지층의 표면에 금속 박막을 형성하는 공정과, 복수의 부재의 금속 박막을 서로 밀착시켜 원자 확산 접합하는 공정을 포함하는 것을 특징으로 한다.
또 본 발명의 구조체의 제조 방법에 있어서, 수지층은 탄성을 가지는 것으로 해도 되고, 부재는 반도체로 해도 된다.
또 본 발명의 구조체의 제조 방법에 있어서, 적어도 하나의 반도체는 표면으로부터 소정 높이 돌출된 복수의 전극을 가지고, 액상 수지를 복수의 전극의 사이에 도포하고, 액상 수지의 표면 장력에 의해, 액상 수지의 표면을 평활화함과 아울러, 복수의 전극의 선단면과 액상 수지의 표면을 동일면으로 해도 된다.
또 본 발명의 구조체의 제조 방법에 있어서, 부재는 반도체를 형성한 반도체 칩이며, 액상 수지는 반도체 칩의 표면 또는 반도체 칩의 이면 또는 그 양쪽에 도포되고, 도포된 액상 수지는 그 표면 거칠기가 다른 부재의 표면 거칠기에 비해 작아지도록 평활화되는 것으로 해도 된다.
또 본 발명의 구조체는 복수의 부재의 각 표면에 금속 박막을 각각 형성하고, 금속 박막을 개재시켜 부재가 원자 확산 접합된 구조체로서, 적어도 하나의 부재와 금속 박막 사이에 마련되고, 표면이 평활화된 수지층을 가지는 것을 특징으로 한다. 또 수지층은 탄성을 가지는 것을 특징으로 한다.
또 본 발명의 구조체에 있어서, 적어도 하나의 부재는 반도체 칩이며, 수지층은 그 표면 거칠기가 접합되는 상대의 부재의 표면 거칠기보다 작은 것으로 해도 된다.
본 발명에 의하면, 부재의 박막 형성면이 평활하지 않은 경우라도, 간이한 방법으로 평활한 박막 형성면을 얻을 수 있고, 원자 확산 접합에 의한 접합을 행할 수 있다. 또 부재의 금속 박막의 사이에 이물이 존재하는 경우라도, 원자 확산 접합에 의한 접합을 행할 수 있다.
도 1은 제1 실시형태의 구조체의 개략 구성도이다.
도 2는 제1 실시형태의 구조체의 제조 공정도이다.
도 3a는 기판 표면이 조면인 경우의 종래의 구조체를 나타내는 모식도이다.
도 3b는 기판 표면이 조면인 경우의 제1 실시형태의 구조체를 나타내는 모식도이다.
도 4는 제2 실시형태의 구조체의 모식도이다.
도 5는 제2 실시형태의 구조체의 제조 공정도이다.
도 6a는 금속 박막 사이에 이물이 들어간 경우에 있어서의 종래의 구조체를 나타내는 모식도이다.
도 6b는 금속 박막 사이에 이물이 들어간 경우에 있어서의 제2 실시형태의 구조체를 나타내는 모식도이다.
도 7은 제2 실시형태의 구조체의 변형예를 나타내는 개략 구성도이다.
도 8은 제3 실시형태의 구조체의 개략 구성도이다.
도 2는 제1 실시형태의 구조체의 제조 공정도이다.
도 3a는 기판 표면이 조면인 경우의 종래의 구조체를 나타내는 모식도이다.
도 3b는 기판 표면이 조면인 경우의 제1 실시형태의 구조체를 나타내는 모식도이다.
도 4는 제2 실시형태의 구조체의 모식도이다.
도 5는 제2 실시형태의 구조체의 제조 공정도이다.
도 6a는 금속 박막 사이에 이물이 들어간 경우에 있어서의 종래의 구조체를 나타내는 모식도이다.
도 6b는 금속 박막 사이에 이물이 들어간 경우에 있어서의 제2 실시형태의 구조체를 나타내는 모식도이다.
도 7은 제2 실시형태의 구조체의 변형예를 나타내는 개략 구성도이다.
도 8은 제3 실시형태의 구조체의 개략 구성도이다.
우선, 제1 실시형태에 대해서, 도 1~3을 참조하여 설명한다. 도 1에 나타내는 바와 같이, 제1 실시형태에 있어서의 구조체(1)는 한 쌍의 부재로서의 기체(基體)(10, 20)를 원자 확산 접합 방법에 의해 서로 접합하여 구성되어 있다. 또한 여기서는 한 쌍의 기체(10, 20)를 구비하는 구조체(1)에 대해서 설명하는데, 기체는 복수여도 된다.
구조체(1)는 일방측의 기체(10)와, 기체(10)의 접합측면에 마련된 수지층(11)과, 수지층(11)의 표면에 마련된 금속 박막(12)과, 타방측의 기체(20)와, 기체(20)의 접합측면에 마련된 금속 박막(21)을 구비하고 있다. 기체(20)는 기체(10)를 접합하는 상대의 부재이다.
기체(10)의 접합측면은 조면이다. 기체(10, 20)의 재질로서는 각종 금속, 합금 이외에 Si 기판 등의 반도체, 유리, 세라믹스, 수지 등을 사용할 수 있다. 또 기체(10, 20)는 금속끼리의 접합과 같이 동일 재질 사이의 접합에 한정되지 않고, 예를 들면, 금속과 세라믹스와의 접합이나, 칩 IC와 Si 기판과의 접합과 같이, 이종 재질 사이의 접합을 행하는 것도 가능하다. 기체(10, 20)의 형상은 특별히 한정되지 않고, 예를 들면, 평판상의 것이나 복잡한 입체형상의 것을 사용할 수 있다. 기체(10)는 예를 들면 반도체를 형성한 반도체 칩이어도 된다. 또 기체(20)는 반도체를 형성한 Si 기판(실리콘 기판) 또는 반도체 칩이어도 된다.
수지층(11)은 기체(10)의 접합측면에 소정의 두께로 형성되어 있다. 수지층(11)은 액상 수지를 기체(10)의 접합측면에 스핀 코트에 의해 도포하여 경화함으로써 형성되어 있다. 수지층(11)의 특성으로서 금속 박막(12)과의 접합 상성이 좋은 재질의 수지를 선택할 필요가 있고, 예를 들면, 실리콘 수지, 불소 수지, 폴리이미드 수지, 아크릴 수지, 또는 에폭시 수지 등을 사용할 수 있다.
금속 박막(12)은 스퍼터링에 의한 성막 방법에 의해 수지층(11)의 표면에 수nm~수백nm의 막두께로 형성되어 있다. 또 금속 박막(21)도 마찬가지의 성막 방법에 의해 기체(20)의 표면에 수nm~10nm의 막두께로 형성되어 있다. 또한 스퍼터링 이외에 PVD, CVD, 진공증착에 의한 성막 방법을 사용해도 된다. 또 금속 박막(12, 21)의 재료로서는 예를 들면 Au, Ag 등의 금속을 사용할 수 있다.
이어서, 구조체(1)의 제조에 대해서 도 2를 참조하여 설명한다. 우선, 도 2에 있어서의 공정 S1에 있어서 기체(10)를 준비한다. 기체(10)의 접합측면은 조면으로 되어 있다. 이와 같은 조면인 경우, 이 조면을 평활면으로 하기 위해서 연마 처리할 필요가 있는데, 제1 실시형태에서는 연마 처리를 행하지 않고, 이 조면의 상태로 사용한다.
공정 S2에서는 기체(10)의 조면에 액상 수지(11a)를 도포한다. 도포된 액상 수지(11a)는 조면을 메움과 아울러, 액상 수지(11a)의 표면 장력에 의해 액상 수지(11a)의 표면을 평활화한다. 즉, 도포 직후에는 액상 수지(11a)에 표면 장력이 작용하여, 액상 수지(11a)의 표면이 평활하게 된다. 액상 수지(11a)의 표면이 평활화한 것을 확인한 후에, 기체(10) 및 액상 수지(11a)를 가열하고, 액상 수지(11a)를 경화하여 수지층(11)을 형성한다.
공정 S3에서는 수지층(11)이 형성된 기체(10)를 진공 용기 내에 배치하고, 수지층(11)의 표면에 스퍼터링에 의해 금속 박막(12)을 형성한다.
한편, 공정 S4에 있어서 기체(20)를 준비하고, 공정 S5에 있어서 기체(20)를 진공 용기 내에 배치하고, 기체(20)의 표면에 스퍼터링에 의해 금속 박막(21)을 형성한다. 또한 기체(20)의 표면은 기체(10)의 표면과 같은 조면이 아니며 표면의 평활화는 필요없으므로, 기체(10)와 같이 액상 수지의 도포는 행하지 않는다.
그리고, 공정 S6에 있어서, 진공 용기로부터 기체(10) 및 기체(20)를 각각 취출하고, 기체(10)를 상하 반전시켜 금속 박막(12)의 면을 하방을 향하게 하여, 이 금속 박막(12)을 기체(20)의 금속 박막(21)에 중첩시킨다. 이 중첩시킨 상태에 있어서, 기체(10)에 하중을 부여하여, 기체(10)의 금속 박막(12)과 기체(20)의 금속 박막(21)을 밀착시킨다. 이 밀착 상태에 의해 금속 박막(12, 21)은 원자 확산에 의해 서로 접합한다. 원자 확산 접합에 의해, 금속 박막(12, 21)은 원자 레벨에서 금속 결합 또는 분자간 결합함으로써 강고하게 접합한다. 금속 박막(12, 21)이 강고하게 접합함으로써 구조체(1)가 구성된다.
또 기체(10)의 표면 Ra(산술 평균 거칠기)와, 수지층(11)의 표면 Ra를 비교하면, 수지층(11)의 표면 Ra는 기체(10)의 표면 Ra보다 작다. 즉, 수지층(11)의 표면은 평활화되어 있으므로 그 표면 Ra는 작고, 기체(10)의 표면은 조면이므로, 그 표면 Ra는 크다. 이 때문에, 수지층(11)의 표면 Ra<기체(10)의 표면 Ra의 관계로 되어 있다. 또 수지층(11)의 표면 Ra는 평활화에 의해 표면이 평활하며 표면의 평활화가 불필요한 기체(20)의 표면 Ra보다 작게 되어 있다.
도 3a, 도 3b를 참조하여, 구조체(1)에 의한 효과에 대해서 설명한다. 도 3a, 도 3b는 접합측면이 조면인 기체를 원자 확산에 의해 접합하는 경우의 모식도이다. 도 3a는 종래의 구조체(100)의 경우를 나타내고, 도 3b는 제1 실시형태의 구조체(1)의 경우를 나타내고 있다.
도 3a에 있어서, 종래의 구조체(100)의 구성에 대해서 간단히 설명한다. 구조체(100)는 접합면이 조면인 기체(110)와, 기체(110)의 조면에 형성된 금속 박막(111)과, 기체(120)와, 기체(120)의 표면에 형성된 금속 박막(121)을 구비하고 있다. 그리고, 금속 박막(111, 121)을 중첩시켜 원자 확산 접합함으로써 구조체(100)를 구성하고 있다.
구조체(100)에서는 기체(110)의 조면은 평활성이 낮으므로, 이 조면에 형성하는 금속 박막(111)의 표면의 평활성도 낮아진다. 이 때문에, 금속 박막(111, 121)을 밀착시키는 것이 곤란하게 되고, 금속 박막(111, 121)을 원자 확산에 의해 접합하는 것도 곤란하게 된다. 그 결과 접합 불량이 된다.
이에 대해, 도 3b에 나타내는 바와 같이, 구조체(1)에서는 기체(10)의 조면을 수지층(11)으로 메우고 있고, 또한 이 수지층(11)의 표면은 평활면이므로, 금속 박막(12)의 표면도 평활면이다. 이 때문에, 금속 박막(12, 21)을 밀착시킬 수 있고, 금속 박막(12, 21)을 원자 확산에 의해 접합할 수 있다.
이와 같이, 기체(10)의 조면을 평활면으로 하기 위한 연마 처리가 불필요하게 되어, 연마 처리의 작업을 줄일 수 있고, 비용을 억제할 수 있다. 또 기체(10)가 조면이어도 원자 확산에 의한 접합을 행할 수 있어, 원자 확산에 의한 접합 부재의 적용 범위를 넓힐 수 있다.
또한 기체(20)의 금속 박막(21)을 형성하는 면이 조면인 경우, 기체(20)와 금속 박막(21) 사이에 수지층(11)을 형성해도 된다. 이 경우에는 도 2에 있어서 공정 S4와 공정 S5 사이에 공정 S2와 같은 공정을 행한다.
이어서, 제2 실시형태에 대해서 도 4~6을 참조하여 설명한다. 제2 실시형태에서는 구조체(2)의 기체(30)의 접합측면은 평활면이며, 수지층(31)의 특성이 수지층(11)의 특성과 상이하다. 그 밖의 구성은 제1 실시형태의 구조체(1)와 마찬가지이다. 이 때문에, 도 4에 있어서, 도 1과 마찬가지의 구성에 대해서는 동일 부호를 붙이고, 그 설명을 생략한다.
수지층(31)은 기체(30)의 접합측면(평활면)에 소정의 두께로 형성되어 있다. 수지층(31)은 액상의 수지를 기체(30)의 접합측면에 스핀 코트에 의해 도포하여 경화함으로써 형성되어 있다. 수지층(31)의 특성으로서 금속 박막(12)과의 접합 상성이 좋은 재질의 수지를 선택할 필요가 있고, 또 경화 후에 탄성을 가지는 재질을 선택할 필요가 있다. 이와 같은 수지로서 예를 들면 실리콘 수지, 불소 수지, 폴리이미드 수지, 아크릴 수지, 또는 에폭시 수지 등을 사용할 수 있다.
구조체(2)의 제조에 대해서 도 5를 참조하여 설명한다. 도 5에 있어서의 공정 S11에 있어서, 기체(30)를 준비한다.
공정 S12에서는 기체(30)의 접합측면에 액상 수지(31a)를 도포한다. 액상 수지(31a)의 재료로서는 경화 후에도 탄성을 가지는 수지 재료를 사용한다. 도포된 액상 수지(31a)는 액상 수지(31a)의 표면 장력에 의해 액상 수지(31a)의 표면이 평활하게 된다. 액상 수지(31a)의 표면이 평활화한 것을 확인한 후에, 기체(30) 및 액상 수지(31a)를 가열하고, 액상 수지(31a)를 경화하여 수지층(31)을 형성한다. 또한 수지층(31)은 경화 후에도 탄성을 가지고 있다.
공정 S13에서는 수지층(31)이 형성된 기체(30)를 진공 용기 내에 배치하고, 수지층(31)의 표면에 스퍼터링에 의해 금속 박막(12)을 형성한다.
공정 S14, S15에서는 공정 S4, S5와 마찬가지로 기체(20)에 금속 박막(21)을 형성한다. 계속해서, 공정 S16에 있어서, 기체(30)를 상하 반전시켜 금속 박막(12)의 면을 하방을 향하게 하여, 이 금속 박막(12)을 기체(20)의 금속 박막(21)에 중첩시킨다. 이 중첩시킨 상태에 있어서, 기체(30)에 하중을 부여하여, 기체(30)의 금속 박막(12)과 기체(20)의 금속 박막(21)을 밀착시킨다. 이 밀착 상태에 의해 금속 박막(12, 21)은 원자 확산에 의해 서로 접합한다. 원자 확산 접합에 의해, 금속 박막(12, 21)은 원자 레벨에서 금속 결합 또는 분자간 결합함으로써 강고하게 접합한다. 금속 박막(12, 21)이 강고하게 접합함으로써 구조체(2)가 구성된다.
도 6a, 도 6b를 참조하여, 구조체(2)에 의한 효과에 대해서 설명한다. 도 6a, 도 6b는 금속 박막 사이에 이물(D)이 들어간 경우를 설명하는 모식도이다. 도 6a는 종래의 구조체(200)의 경우를 나타내고, 도 6b는 제2 실시형태의 구조체(2)의 경우를 나타내고 있다.
도 6a에 있어서, 종래의 구조체(200)는 기체(210)와, 기체(210)의 표면에 형성된 금속 박막(211)과, 기체(220)와, 기체(220)의 표면에 형성된 금속 박막(221)을 구비하고 있다. 그리고, 금속 박막(211, 221)을 중첩시켜 원자 확산 접합함으로써 구조체(200)를 구성하고 있다.
구조체(200)에 있어서, 금속 박막(211, 221)을 중첩시킬 때, 금속 박막(211, 221) 사이에 이물(D)이 들어가면, 이물(D)이 장애가 되어 금속 박막(211, 221)을 중첩시키는 것이 곤란하게 되어, 금속 박막(211, 221)을 밀착시키는 것이 곤란하게 된다. 이 때문에, 금속 박막(211, 221)을 원자 확산에 의해 접합하는 것도 곤란하게 되고, 그 결과 접합 불량이 된다.
이에 대해, 도 6b에 나타내는 바와 같이, 제2 실시형태의 구조체(2)에서는 금속 박막(12, 21) 사이에 이물(D)이 들어간 상태에서, 금속 박막(12, 21)을 중첩시키면 이물(D)의 형상에 따라 수지층(31)이 탄성 변형한다. 그리고, 이물(D)을 감싼 상태에서, 금속 박막(12, 21)이 서로 밀착된다. 즉, 이물(D) 이외의 금속 박막(12, 21)의 부분에서, 금속 박막(12, 21)은 서로 밀착된다.
이물(D) 이외의 금속 박막(12, 21)의 부분은 충분한 중첩 면적을 가지고 있으므로, 금속 박막(12, 21)을 원자 확산에 의해 접합할 수 있고, 이물(D)이 들어가도 구조체(2)를 얻을 수 있다.
또 금속 박막(12, 21)의 표면의 평활성이 낮아도 수지층(31)이 탄성 변형함으로써, 금속 박막(12, 21)이 서로 밀착되므로, 금속 박막(12, 21)을 원자 확산에 의해 접합할 수 있다.
이어서, 제2 실시형태의 변형예에 대해서 도 7을 참조하여 설명한다. 도 7에 나타내는 바와 같이, 제2 실시형태의 변형예를 나타내는 구조체(3)에서는 수지층(22)이 기체(20)측에도 형성되어 있다. 즉, 기체(20)의 접합측면에 수지층(22)이 형성되어 있다. 수지층(22)의 재질로서는 수지층(31)과 마찬가지로 경화 후에 탄성을 가지는 재료를 사용한다.
이와 같이, 기체(30, 20)의 양쪽에 수지층(31, 22)을 형성함으로써, 금속 박막(12, 21)의 사이에 이물(D)이 들어간 경우, 이물(D)의 형상에 따라 수지층(31, 22)이 탄성 변형하므로, 제2 실시형태와 마찬가지로, 이물(D)을 감싼 상태에서 금속 박막(12, 21)이 서로 밀착되어, 금속 박막(12, 21)을 원자 확산 접합 방법에 의해 접합할 수 있다.
또 수지층(31, 22)에 의해 탄성 변형량이 증가하므로, 보다 큰 이물(D)에도 대응할 수 있고, 또 금속 박막(12, 21)의 서로의 면으로의 추종성을 향상시킬 수 있어, 금속 박막(12, 21)의 밀착성을 향상시킬 수 있다.
이어서, 제3 실시형태에 대해서 도 8을 참조하여 설명한다. 제3 실시형태에서는 구조체가 반도체 장치(4)이다. 도 8에 나타내는 바와 같이, 반도체 장치(4)는 기판(40)과, 칩 부품(50)과, 칩 부품(50)의 전극(51) 사이에 마련되는 수지층(52)과, 기판(40)과 칩 부품(50)을 접속하는 금속 박막(42, 53)을 구비하고 있다. 칩 부품(50)은 예를 들면 반도체를 형성한 반도체 칩이다.
기판(40)은 Si 기판(실리콘 기판)이다. 기판(40)에는 복수의 전극(41)이 매설되어 있다. 칩 부품(50)의 하면에는 이 하면으로부터 소정 높이 돌출되는 복수의 전극(51)이 마련되어 있다. 복수의 전극(51)은 기판(40)에 마련된 전극(41)에 각각 대응하도록 배치되어 있다.
전극(51)의 사이에는 제1 실시형태에 있어서의 액상 수지(11a)와 마찬가지의 액상 수지가 도포되어 있고, 전극(51)의 선단면과 액상 수지의 표면이 동일면으로 되어 있다. 칩 부품(50)의 전극(51)의 사이에 액상 수지를 도포하고, 이 액상 수지의 표면 장력에 의해, 액상 수지의 표면이 평활하게 된다. 그리고, 이 평활면은 전극(51)의 선단면과 동일면이 된다. 이 상태에서 액상 수지를 경화함으로써 수지층(52)이 형성된다.
칩 부품(50)의 전극(51)의 선단면 및 수지층(52)의 표면에는 제1 실시형태에 있어서의 금속 박막(12)과 마찬가지의 금속 박막(53)이 형성되어 있다. 또 기판(40)의 표면에도 제1 실시형태에 있어서의 금속 박막(12)과 마찬가지의 금속 박막(42)이 형성되어 있다. 그리고, 칩 부품(50)의 전극(51)과 기판(40)의 전극(41)을 대향시켜, 금속 박막(42, 53)을 원자 확산에 의해 접합함으로써, 칩 부품(50)과 기판(40)이 접합되어 반도체 장치(4)가 구성된다.
이와 같이, 칩 부품(50)의 전극(51)의 사이에 수지층(52)을 형성함으로써, 금속 박막(53)을 형성하는 면적을 확대할 수 있고, 칩 부품(50)과 기판(40)을 보다 강고하게 원자 확산 접합할 수 있다.
이상 설명한 각 실시형태는 2개의 기체를 원자 확산 접합에 의해 접합하는 것으로서 설명했지만, 이것에 한정되지 않고, 예를 들면, 반도체 칩의 표면과 이면에 액상 수지를 도포, 경화시켜 양면에 수지층을 형성하고, 그 위에 금속 박막을 형성한 중간 칩 부품을 복수단으로 적층하고, 그 양단에 반도체 칩의 표면 또는 이면에 액상 수지를 도포, 경화시켜 일방의 면에 수지층을 형성하고, 그 위에 금속 박막을 형성한 단부 칩 부품을 적층하고 원자 확산 접합을 행하여, 반도체 칩을 복수단으로 적층한 구조체로 해도 된다.
1, 2, 3…구조체
4…반도체 장치
10, 20, 30, 40…기체(基體)
11, 22, 31, 52…수지층
11a, 31a…액상 수지
12, 21, 42, 53…금속 박막
41, 51…전극
50…칩 부품
4…반도체 장치
10, 20, 30, 40…기체(基體)
11, 22, 31, 52…수지층
11a, 31a…액상 수지
12, 21, 42, 53…금속 박막
41, 51…전극
50…칩 부품
Claims (4)
- 표면이 조면인 복수의 반도체 칩을 접합한 구조체의 제조 방법으로서,
복수의 상기 반도체 칩의 표면에 액상 수지를 각각 도포하는 공정과,
도포된 상기 액상 수지의 표면 장력에 의해, 상기 액상 수지의 표면을 평활화하는 공정과,
상기 액상 수지를 경화하여 복수의 상기 반도체 칩의 표면에 표면이 평활화된 수지층을 각각 형성하는 공정과,
표면이 평활화된 상기 수지층의 각각의 표면에, Au, Ag 또는 Au 및 Ag를 주성분으로 하는 합금인 금속 박막을 각각 형성하는 공정과,
복수의 상기 반도체 칩의 상기 금속 박막을 서로 밀착시켜 원자 확산 접합에 의해 접합하는 공정
을 포함하고,
상기 접합하는 공정은, 상기 금속 박막의 사이에 이물이 들어간 때에는 상기 수지층의 탄성 변형에 의해 상기 이물을 감싼 상태에서 상기 금속 박막을 서로 밀착시켜 원자 확산 접합에 의해 접합하는 것을 특징으로 하는 구조체의 제조 방법. - 제1 항에 있어서,
적어도 하나의 상기 반도체 칩은 표면으로부터 소정 높이 돌출된 복수의 전극을 가지고,
상기 액상 수지를 복수의 상기 전극의 사이에 도포하고, 상기 액상 수지의 표면 장력에 의해, 상기 액상 수지의 표면을 평활화함과 아울러, 복수의 상기 전극의 선단면과 상기 액상 수지의 표면을 동일면으로 하는 것을 특징으로 하는 구조체의 제조 방법. - 제1 항에 있어서,
상기 액상 수지는 상기 반도체 칩의 표면 또는 상기 반도체 칩의 이면 또는 그 양쪽에 도포되고,
도포된 상기 액상 수지는 그 표면 거칠기가 상기 반도체 칩의 표면 거칠기에 비해 작아지도록 평활화되는 것
을 특징으로 하는 구조체의 제조 방법. - 표면이 조면인 복수의 반도체 칩의 각각의 표면에, Au, Ag 또는 Au 및 Ag를 주성분으로 하는 합금인 금속 박막을 각각 형성하고, 각각의 상기 금속 박막을 개재시켜 상기 반도체 칩이 서로 원자 확산 접합에 의해 접합된 구조체로서,
각각의 상기 반도체 칩과 각각의 상기 금속 박막 사이에 각각 마련되고, 표면이 평활화된 수지층을 가지고,
상기 각각의 수지층의 표면 거칠기는 상기 각각의 반도체 칩의 표면 거칠기보다 작고,
상기 금속 박막의 사이에 이물이 들어간 때에는 탄성 변형에 의해 상기 이물을 감싼 상태에서 상기 금속 박막을 서로 밀착시키는 것을 특징으로 하는 구조체.
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