KR20140107129A - 반도체 장치 및 반도체 장치의 제조 방법 - Google Patents

반도체 장치 및 반도체 장치의 제조 방법 Download PDF

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Publication number
KR20140107129A
KR20140107129A KR1020140021110A KR20140021110A KR20140107129A KR 20140107129 A KR20140107129 A KR 20140107129A KR 1020140021110 A KR1020140021110 A KR 1020140021110A KR 20140021110 A KR20140021110 A KR 20140021110A KR 20140107129 A KR20140107129 A KR 20140107129A
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KR
South Korea
Prior art keywords
layer
connection terminal
insulating
insulating layer
chip
Prior art date
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Withdrawn
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KR1020140021110A
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English (en)
Korean (ko)
Inventor
스미히로 이치카와
다카하루 야마노
Original Assignee
신꼬오덴기 고교 가부시키가이샤
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Publication of KR20140107129A publication Critical patent/KR20140107129A/ko
Withdrawn legal-status Critical Current

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    • H10W20/20—
    • H10W20/023—
    • H10W20/0245—
    • H10W20/0249—
    • H10W90/00—
    • H10P72/7402—
    • H10P72/7416—
    • H10P72/7422—
    • H10W70/65—
    • H10W70/655—
    • H10W72/01235—
    • H10W72/01255—
    • H10W72/01257—
    • H10W72/01271—
    • H10W72/019—
    • H10W72/01904—
    • H10W72/01935—
    • H10W72/0198—
    • H10W72/072—
    • H10W72/07232—
    • H10W72/07236—
    • H10W72/07254—
    • H10W72/073—
    • H10W72/07338—
    • H10W72/221—
    • H10W72/222—
    • H10W72/224—
    • H10W72/232—
    • H10W72/234—
    • H10W72/241—
    • H10W72/242—
    • H10W72/244—
    • H10W72/247—
    • H10W72/248—
    • H10W72/252—
    • H10W72/29—
    • H10W72/325—
    • H10W72/352—
    • H10W72/354—
    • H10W72/921—
    • H10W72/9223—
    • H10W72/923—
    • H10W72/934—
    • H10W72/9415—
    • H10W72/942—
    • H10W72/944—
    • H10W72/952—
    • H10W74/00—
    • H10W74/117—
    • H10W74/15—
    • H10W90/28—
    • H10W90/297—
    • H10W90/722—
    • H10W90/724—
    • H10W90/732—
    • H10W99/00—

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
KR1020140021110A 2013-02-27 2014-02-24 반도체 장치 및 반도체 장치의 제조 방법 Withdrawn KR20140107129A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JPJP-P-2013-037899 2013-02-27
JP2013037899 2013-02-27
JPJP-P-2013-217624 2013-10-18
JP2013217624A JP6232249B2 (ja) 2013-02-27 2013-10-18 半導体装置及び半導体装置の製造方法

Publications (1)

Publication Number Publication Date
KR20140107129A true KR20140107129A (ko) 2014-09-04

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ID=51387324

Family Applications (1)

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KR1020140021110A Withdrawn KR20140107129A (ko) 2013-02-27 2014-02-24 반도체 장치 및 반도체 장치의 제조 방법

Country Status (4)

Country Link
US (1) US9048225B2 (enExample)
JP (1) JP6232249B2 (enExample)
KR (1) KR20140107129A (enExample)
TW (1) TWI645567B (enExample)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9589913B1 (en) * 2013-03-29 2017-03-07 Rockwell Collins, Inc. Flip chip stacking utilizing interposer
JP2016076534A (ja) * 2014-10-03 2016-05-12 イビデン株式会社 金属ポスト付きプリント配線板およびその製造方法
TWI566305B (zh) * 2014-10-29 2017-01-11 巨擘科技股份有限公司 製造三維積體電路的方法
TWI575785B (zh) 2014-10-30 2017-03-21 新世紀光電股份有限公司 發光裝置
JP6437805B2 (ja) * 2014-12-03 2018-12-12 東京応化工業株式会社 積層体の製造方法、封止基板積層体の製造方法及び積層体
JP6780933B2 (ja) * 2015-12-18 2020-11-04 新光電気工業株式会社 端子構造、端子構造の製造方法、及び配線基板
TWI822659B (zh) * 2016-10-27 2023-11-21 美商艾德亞半導體科技有限責任公司 用於低溫接合的結構和方法
EP3451804B1 (en) * 2017-08-28 2020-04-01 Goodrich Actuation Systems Limited Potting method
KR101942745B1 (ko) * 2017-11-07 2019-01-28 삼성전기 주식회사 팬-아웃 반도체 패키지
EP3712298A4 (en) * 2017-11-16 2021-08-11 JX Nippon Mining & Metals Corporation SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD FOR IT
KR20190083054A (ko) * 2018-01-03 2019-07-11 삼성전자주식회사 반도체 패키지
CN110032285A (zh) * 2018-01-11 2019-07-19 南昌欧菲显示科技有限公司 触控模组及其制造方法
KR20190137458A (ko) * 2018-06-01 2019-12-11 삼성전자주식회사 Led를 이용한 디스플레이 모듈 제조방법
US10643943B2 (en) * 2018-06-25 2020-05-05 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure, package-on-package structure and manufacturing method thereof
KR102530754B1 (ko) * 2018-08-24 2023-05-10 삼성전자주식회사 재배선층을 갖는 반도체 패키지 제조 방법
TWI674599B (zh) * 2018-09-12 2019-10-11 鈺冠科技股份有限公司 堆疊型電容器組件結構
TWI676194B (zh) * 2018-09-21 2019-11-01 鈺冠科技股份有限公司 不需要使用碳膠層的堆疊型電容器及其製作方法、以及銀膠層
TWI688017B (zh) * 2019-03-15 2020-03-11 南茂科技股份有限公司 晶片封裝結構及其製造方法
KR102629832B1 (ko) 2019-03-28 2024-01-26 삼성전자주식회사 반도체 패키지 기판 및 이를 이용한 반도체 패키지 제조 방법
US11069605B2 (en) * 2019-04-30 2021-07-20 Advanced Semiconductor Engineering, Inc. Wiring structure having low and high density stacked structures
US20210090981A1 (en) * 2019-09-23 2021-03-25 Intel Corporation Surface finish surrounding a pad
GB2590689B (en) * 2019-12-24 2023-01-11 Rockley Photonics Ltd Packaging of three-dimensional integrated circuit by encapsulation with copper posts and double sided redistribution layer
JP2022047357A (ja) * 2020-09-11 2022-03-24 キオクシア株式会社 半導体装置およびその製造方法
EP3998628A4 (en) * 2020-09-17 2022-08-03 Changxin Memory Technologies, Inc. SOLDER PAD STRUCTURE, SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR PACKAGING STRUCTURE AND METHOD OF MANUFACTURE THEREOF
US11908831B2 (en) * 2020-10-21 2024-02-20 Stmicroelectronics Pte Ltd Method for manufacturing a wafer level chip scale package (WLCSP)
US20230238345A1 (en) * 2022-01-27 2023-07-27 nD-HI Technologies Lab, Inc. High-yielding and ultrafine pitch packages for large-scale ic or advanced ic
US12374647B2 (en) * 2022-05-12 2025-07-29 Renesas Electronics Corporation Semiconductor device including chip-to-chip bonding
WO2025187363A1 (ja) * 2024-03-07 2025-09-12 パナソニックＩｐマネジメント株式会社 インターポーザ

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3972846B2 (ja) * 2003-03-25 2007-09-05 セイコーエプソン株式会社 半導体装置の製造方法
JP4016984B2 (ja) 2004-12-21 2007-12-05 セイコーエプソン株式会社 半導体装置、半導体装置の製造方法、回路基板、及び電子機器
JP5222459B2 (ja) * 2005-10-18 2013-06-26 新光電気工業株式会社 半導体チップの製造方法、マルチチップパッケージ
JP2010067916A (ja) * 2008-09-12 2010-03-25 Panasonic Corp 集積回路装置
US8399987B2 (en) * 2009-12-04 2013-03-19 Samsung Electronics Co., Ltd. Microelectronic devices including conductive vias, conductive caps and variable thickness insulating layers
JP5357241B2 (ja) * 2011-08-10 2013-12-04 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
KR101845529B1 (ko) * 2012-02-02 2018-04-05 삼성전자주식회사 관통전극을 갖는 반도체 소자 및 그 제조방법

Also Published As

Publication number Publication date
US20140239508A1 (en) 2014-08-28
JP2014195041A (ja) 2014-10-09
JP6232249B2 (ja) 2017-11-15
TWI645567B (zh) 2018-12-21
US9048225B2 (en) 2015-06-02
TW201438245A (zh) 2014-10-01

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