KR20120076424A - 칩을 웨이퍼에 본딩하기 위한 방법 - Google Patents

칩을 웨이퍼에 본딩하기 위한 방법 Download PDF

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KR20120076424A
KR20120076424A KR1020127006928A KR20127006928A KR20120076424A KR 20120076424 A KR20120076424 A KR 20120076424A KR 1020127006928 A KR1020127006928 A KR 1020127006928A KR 20127006928 A KR20127006928 A KR 20127006928A KR 20120076424 A KR20120076424 A KR 20120076424A
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South Korea
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chip
chips
support wafer
wafer
bonding
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KR1020127006928A
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KR101377812B1 (ko
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마르커스 빔프링거
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에베 그룹 에. 탈너 게엠베하
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Publication of KR20120076424A publication Critical patent/KR20120076424A/ko
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    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C

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Abstract

지지 웨이퍼(1)에 복수의 칩(9)을 본딩하는 방법에 있어서, 지지 웨이퍼(1)는 지지 웨이퍼(1) 상에 적어도 하나의 층으로 적층되는 칩(3')을 포함하고, 수직으로 이웃하는 칩들을 더 연결하기 위한 전도성 연결(7)이 존재하고, 상기 방법은
a) 지지 웨이퍼(1)를 캐리어(5)에 고정하는 단계와,
b) 칩(3)의 적어도 하나의 층을 상기 지지 웨이퍼(1) 상의 지정된 위치로 배치하는 단계와,
c) 캐리어(5)에 고정되어 있는 지지 웨이퍼(1) 상의 칩(3)을 열처리하는 단계를 포함하고,
단계 c) 이전에 지지 웨이퍼에서 지지 웨이퍼(1)의 분리된 칩 스텍 섹션(1c)으로의 적어도 부분적인 분리가 발생하는 것을 특징으로 하는 지지 웨이퍼에 복수의 칩을 본딩하는 방법.

Description

칩을 웨이퍼에 본딩하기 위한 방법{METHOD FOR CHIP TO WAFER BONDING}
본 발명은 청구항 제 1 항에 따르는 방법에 관한 것이다.
반도체 산업 분야에서 널리 퍼진 소형화에 대한 압력의 결과로, 이른바 “3D 집적 회로”(3D IC)를 생산할 수 있는 방법이 요구되고 있다. 3D IC는 칩 스택으로 구성되는데, 이러한 칩 스택에서, 복수의 칩이 수직으로 적층(stacking)되어 있으며, 실리콘(silicon)을 통한 수직으로 이웃하는 칩으로의 연결이 존재한다. 이러한 연결을 “TSV(Through Silicon Via)"라고 일컫는다.
이들 칩은 높은 패킹 밀도(packing density)와 가격 대비 높은 성능을 보장한다. 덧붙이자면, 이러한 방식으로, 새로운 유형 및 형태의 칩이 생성될 수 있다. 기본적으로 3D IC를 생성하기 위해 여러 다른 방법들이 가능한데, 특히, 매우 시간 소모적인, 개별 칩을 하나씩 수직으로 적층하는 이른바 “칩-투-칩(Chip-to-Chip)(C2C)”방법, 또는 웨이퍼를 수직으로 적층하는 “웨이퍼-투-웨이퍼(Wafer to Wafer)(W2W)” 방법이 있다. 마지막으로, 이른바 “칩-투-웨이퍼(C2W)” 방법이 또한 논의된다. 주요한 기술적 문제로 인해, 오늘날까지 적정한 기술이 구현되지 못했다. 본 발명은 3D IC를 생산하기 위한 기술적으로 실행 가능한 C2W 방법에 관한 것이다.
낮은 처리량 때문에, C2C 방법은 높은 제조비용을 초래하고, 이로 인해 대량 생산에서는 거의 사용되지 않을 수 있다.
W2W 방법은, 2개의 웨이퍼가 동일한 크기를 갖고, 상기 2개의 웨이퍼 상의 칩들이 서로 동일한 크기를 가질 것을 필요로 한다. 여기서 문제점은 상위 칩 스택을 위한 실리콘 이용률이 평균(이른바 평균 수율) 이하라는 것이다. 정상 작동 칩의 획득 가능한 수율이 C2C나 C2W 방법에서보다 더 낮다.
칩 스택이나 3D IC를 생산하기 위해 C2W를 구현할 때 발생하는 기술적 문제는 웨이퍼(특히, 그 위에 적층되어 있는 칩을 갖는 웨이퍼)의 핸들링과 관련되어 있고, 적층 공정 및 회로 기판(또는 근본적으로 더 상위의 패킹 유닛(packing unit))에 장착되기 위한 칩의 커넥터(인터페이스)를 위한 변화하는 요구조건(특히, 온도)과 관련된다.
따라서 지지 웨이퍼의 핸들링이 중요하다. 왜냐하면, 웨이퍼 상의 복수의 칩 스택의 분리 바로 전에 발생하는 지지 웨이퍼의 파손에 의해, 수천 개의 값비싼 칩이 폐기되기 때문이다. 지지 웨이퍼가 더 얇아질수록, 및/또는 지지 웨이퍼의 면적이 더 넓어질수록, 복수의 칩 스택이 고정/본딩(bonding)되어 있는 지지 웨이퍼의 핸들링은 더 어려워진다. 지지 웨이퍼는, C2W 방법에 의해 자신 위에 칩이 적층되는 웨이퍼이다.
US 2007/001281 A1 발명은 반도체 메모리 생산을 위한 방법에 관한 발명인데, 이 발명에서 메모리 칩의 생산에서의 생산 공정을 단순화하기 위하여 칩들이 지지 웨이퍼에 적층되고, 이후 레진에서 포팅(potting)된다. 포팅 후에, 메모리 칩은 그와 인접한 메모리 칩으로부터 분리된다. 특히, 생산중에, 주로, 메모리 칩을 포팅할 때와 캐리어로부터 분리할 때, 그리고 가능한 후속 공정 단계 중에, 칩 스택에 존재하는 다양한 구성요소의 서로 다른 물질의 서로 다른 열팽창이 문제가 된다.
본 발명의 목적은, 가능한 높은 처리량을 가지면서, 폐기되는 칩이 가능한 없는 가능한 정확하게 위치되는 칩 스택(3D IC) 생산 방법을 고안하는 것이다.
이러한 목적은 청구항 제1항의 특징을 이용하여 이뤄진다. 본 발명의 바람직한 형태들이 종속항에서 나타난다. 상세한 설명, 청구범위 및/또는 도면에서 나타나는 둘 이상의 특징들의 모든 조합이 본 발명의 범위 내에 있다. 상기 주어진 값의 범위의 경우, 적시된 한도 내의 값은 경개값으로 기재된 것으로 여겨질 수 있고 어떤 조합으로든 청구될 수 있다.
본 발명은 최소한 칩을 지지 웨이퍼 상에 적층하는 동안 지지 웨이퍼를 고정하고, 본딩을 위해 칩을 열처리하는 동안 웨이퍼를 캐리어 상에 고정하거나 캐리어에 연결하는 것, 그리고 열처리 직전에, 지지 웨이퍼를 적어도 부분적으로 분리하여, 특히 분리된 것이 바람직한 칩 스택 섹션을 도출하는 것에 대한 아이디어를 바탕으로 한다.
지지 웨이퍼를 캐리어에 고정시킴으로써, C2W 방법의 처리량에 대한 놀라운 이점과 함께, 지지 웨이퍼 상의 지정된 위치로 칩을 배치 또는 적층하는 공정 단계와, 지지 웨이퍼 상에서의 칩의 열처리 또는 본딩의 공정 단계를 분리하는 것이 가능해진다. 열처리나 본딩 단계는, 사용되는 재료에 따라서, 매우 오랜 시간이 걸릴 수 있는 반면, 지지 웨이퍼에 칩을 배치하거나 적층하는 단계는 매우 빠르게 진행될 수 있는(가령, 시간 당 수천 개의 칩이 처리될 수 있는) 단계이다. 열처리 동안 지지 웨이퍼가 더 작은 부속으로 분리되어 존재할 때, 서로 다른 구성요소/물질의 열팽창은 칩 스택의 품질에 훨씬 적은 영향을 미치게 된다. 분리의 결과로, 칩 스택은 서로 다른 열팽창에 의하여 응력을 덜 받게 된다.
이러한 방식으로, 복수의 열처리 챔버/본딩 스테이션을 둠으로써, 및/또는 열처리 챔버/본딩 스테이션에서 적층된 칩을 포함하는 복수의 지지 웨이퍼가 처리되게 함으로써, 처리량이 증가될 수 있다. 열처리 챔버는 고온의 플레이트, 연속로 (continuous furnace)등일 수 있다. 특히 바람직한 한 가지 공정은, 열처리 공정 동안 칩에 압력을 가할 수 있도록 수정된 웨이퍼 본딩 챔버를 이용해 구현될 수 있다.
그 밖의 다른 방법에 비교하여, 본 발명에서는 서로 다른 크기의 칩들을 적층할 수 있는 것이 특히 바람직하다.
지지 웨이퍼에 느슨하게 결합되어 있는 캐리어를 이용함으로써, 지지 웨이퍼에 가해지는 응력과 휘어짐이 균등해지거나 상쇄될 수 있다.
적어도 부분적으로 실리콘 및/또는 유리로 구성되고, 지지 웨이퍼의 크기와 일치하는 크기를 갖는 캐리어에 의해(특히, 캐리어의 반경이 지지 웨이퍼의 반경보다 10㎜이상, 특히 5㎜ 이상, 바람직하게는 2㎜ 이상, 더 바람직하게는 1㎜ 이상 차이나지 않음으로써), 핸들링은 더 단순화된다.
특히 선호되는 고정 수단으로는 부압(또는 진공), 정전기 수단, 기계적 클램핑 및/또는 접착제(바람직하게는 내열 접착제)가 있으며, 이들은 열처리 중의 고온에서도 캐리어 상으로의 지지 웨이퍼의 단단한 고정을 보장하기 위해 사용된다. 만들어지는 연결의 타입에 따라, 또는 칩 스택의 높이에 따라, 또는 그 밖의 다른 요인으로 인해, 여러 다른 고정 수단(또는 그 효과)의 조합이 더 개선된 핸들링을 야기할 수 있다.
본 발명의 하나의 바람직한 실시예에서, 수직으로 이웃하는 칩들에 도포된 전기 전도성 박막의 정렬 및 접촉 과정이 칩을 지정된 위치로 배치하는 과정에서 바로 발생하며, 칩의 아래 위치하는 층의 대응하는 전기 전도성 연결도 함께 발생한다.
이 방법에서, 칩을 배치하는 과정에서, 칩이 그 아래 위치하는 층의 정상 작동 칩 상에만 놓이는 것이 관찰되므로 칩의 수율이 바람직하게 개선될 수 있다. 더욱 더 바람직하게는, 배치될 칩에 기능적으로 연결되는 모든 칩의 기능이 체크되고, 칩에 기능적으로 연결될 모든 칩의 기능만 갖고 칩이 배치된다.
열처리 또는 본딩 단계에서, 웨이퍼와 상기 웨이퍼 위에 배치되는 칩 사이에, 또는 배치된 칩들 사이에 전기 전도성 연결이 생성된다. 열처리는 적합한 분위기(atmosphere)에서(바람직하게는, 금속 접촉부 표면의 산화가 피해지도록 무산소 분위기에서) 발생하는 것이 바람직하다. 특히, 이는 질소 분위기 또는 또 다른 비활성 분위기(가령, 아르곤 분위기)를 이용함으로써 달성될 수 있으며, 많은 경우에서, 비활성 분위기뿐 아니라, 환원 분위기도 특히 바람직하다. 이러한 속성은, 예를 들어, 포밍 기체(forming gas) 또는 포름산 증기에 의해 달성될 수 있다. 상기 포밍 기체는 H2와 N2를 혼합함으로써, 특히, 2%의 H2 : 98%의 H2에서 15%의 H2 : 85%의 N2까지의 범위로 H2와 N2를 혼합함으로써, 형성될 수 있다. 이러한 혼합물에서, N2가 그 밖의 다른 비활성 기체로 대체될 수도 있다.
칩이 더 잘 핸들링되고, 배치된 후 미끄러지지 않기 위해, 배치 후에 칩을 선-고정(pre-fix)하는 것, 특히, 바람직하게는 뒤 이은 본딩 단계 동안 기화되는 유기 접착제를 이용해 칩을 접착하는 것이 바람직하다. 또는, 가령, Si 표면, SiO2 표면 또는 SiN 표면 사이에서, 실온에서, 자생적으로 형성되는 분자 연결(molecular connection)에 의해 칩이 고정될 수 있다. 또 다른 대안으로는 초음파 용접이 있다.
특히 열처리는 280℃미만에서, 특히 250℃미만에서, 바람직하게는 220℃미만에서 연속적으로 발생하는 것이 유리하다. 본 발명에서 청구되는 접착제는 전술한 온도에 적합해야 하는데, 이러한 접착제는 최근에서야 상용화되었다. 이러한 접착제 보기로는 미국의 Brewer-Science Inc. 사의 HAT 씨리즈가 있다.
본 발명의 한 가지 특정 구성에서의 지지 웨이퍼는, 특히, 뒷면-연마(back grinding)에 의해, 200㎛ 이하, 특히 100㎛ 이하, 바람직하게는 50㎛ 이하, 더욱 더 바람직하게는 20㎛ 이하의 두께를 갖는다.
특히, 복수의 칩들이 200㎜ 이상, 특히 300㎜ 이상, 바람직하게는 450㎜ 이상의 직경을 갖는 하나의 지지 웨이퍼 상에 수용될 수 있다.
본 발명의 하나의 특정 실시예에서, 본 발명에 의해서, 단계 B 또는 C 후에 각각의 칩 스택을 기판이나 근본적으로는 다음 번 상위 패킹 유닛으로 연결하는 솔더 범프나 C4 범프를 제공하는 것이 가능하다.
상기 솔더 범프는 낮은 용융점을 갖는 금속 합금으로 구성되며, 칩/칩 스택을 다른 전기/전자 부품으로 연결하기 위해 사용되는 것이 일반적이다.
특히, 지지 웨이퍼를 통과하는 전기 전도성 연결(TSV)을 갖는 지지 웨이퍼를 이용할 때, 단계 b 또는 c 후에 칩 또는 칩 스택을 매스(mass)로 포팅(potting) 처리하는 것이 바람직하며, 이때, 매스는 열적 고안정성 및/또는 기계적 고안정성 및/또는 발수성을 특징으로 하며, 매스는 특히 유기 물질 및/또는 세라믹 물질이다. 적어도 부분적으로 에폭시 수지가 매스 내에 포함되거나, 매스가 에폭시 수지로 완전히 형성되는 실시예가 특히 바람직하다. 본 발명의 한 가지 특정 실시예에서, 에폭시 수지-함유 매스는 섬유-강화(fiber-reinforce)될 수 있다.
바람직하게는 매스는 상온 또는 보다 높은 온도에서 액체 형태로 주입 된다.
본 발명의 하나의 바람직한 실시예에서, 매스는 포팅 공정 후 가압된다. 특히, 대기압 이하로(바람직하게는 진공에서) 포팅 공정을 수행한 후, 대기압으로 해방시킴으로써, 가압된다. 이로써, 가능한 갭 및/또는 공동이 매스로 채워지게 되고, 이는 칩 스택의 장기적인 신뢰성에 기여한다.
바람직하게는 듀로플라스틱(duroplastic) 매스에 의한 포팅 공정 후, 상기 지지 웨이퍼가 캐리어로부터 취해질 수 있는 것이 바람직하다.
본 발명의 하나의 바람직한 실시예에서, 매스는 다음과 같이 작용한다. 포팅 공정 후, 또는 포팅 공정 중, 매스가 지지 웨이퍼에 대응하는 기본 형태가 되거나, 및/또는, 매스가 개별 칩의 최상위 층인 한 제거된다(특히, 연마되어 벗겨진다(grind off)). 이는 지지 웨이퍼, 포팅 처리된 칩 및 매스로 구성된 몸체의 추가적인 핸들링을 단순화한다. 그리고 알려진 핸들링 구조가 특별히 사용될 수 있다. 바람직하게는, 매스를 제거함으로써, 정교한 평면 표면이 형성됨으로써, 냉각체(cooling body)가 최상위 층에 제공될 수 있다.
본 발명의 한 가지 바람직한 실시예에서, 지지 웨이퍼 및/또는 캐리어는 실리콘으로 구성되고, 따라서 캐리어는 웨이퍼와 유사하다. 캐리어는 공지된 구조를 이용해 핸들링될 수 있으며, 지지 웨이퍼와 캐리어가 실리콘으로 구성되는 한, 상기 캐리어의 열팽창 계수가 서로 동일하다는 추가적인 이점이 있다.
본 발명의 또 다른 이점, 특징 및 세부사항이 다음의 바람직한 실시예에 대한 기재와 도면을 통해 명백해질 것이다.
도 1은 청구된 발명의 방법의 구현을 위한 유닛의 구조를 보여준다.
도 2a는 청구된 발명의 지지 웨이퍼를 개략적으로 보여준다.
도 2b는 청구된 발명의 일시적인 본딩 과정을 개략적으로 보여준다.
도 2c는 청구된 발명의 뒷면-연마(back grinding) 단계를 개략적으로 보여준다.
도 2d는 청구된 발명의 지지 웨이퍼에서의 전기 전도성 연결 형성을 위한 과정을 보여준다.
도 2e는 청구된 발명의 뒷면의 금속화(back side metallization) 단계, 특히 지지 웨이퍼의 표면에 전기 전도성 박막을 도포하는 단계를 개략적으로 보여준다.
도 2f는 청구된 발명의 위치설정 단계 및 열처리 단계를 개략적으로 보여준다.
도 2g는 청구된 발명의 포팅 단계를 개략적으로 보여준다.
도 2h는 청구된 발명의 지지 웨이퍼로부터 캐리어를 분리하기 위한 분리 단계를 개략적으로 보여준다.
도 2i는 청구된 발명의 세척 단계를 개략적으로 보여준다.
도 2k는 청구된 발명의 솔더 범프 도포 단계를 개략적으로 보여준다.
도 2l은 청구된 발명을 필름 프레임에 적용하는 것을 개략적으로 보여준다.
도 2m은 청구된 발명의 다이싱 단계를 개략적으로 보여준다.
도 2n은 청구된 발명의 칩 스택을 개략적으로 보여준다.
도면에 있어서, 같은 구성 요소와 같은 기능을 가진 구성 요소들은 동일한 참조번호에 의하여 구분되어 있다.
도 1은 본 발명에 따르는 방법을 수행하기 위한 유닛의 개략적 구조를 도시하며, 이때, 지지 웨이퍼(1)의 영역 A에 칩 층을 배치(placement)하는 것이, 도 2f에서 나타나는 바와 같이, 스테이션(B.1)에서 지지 웨이퍼(1)가 캐리어(5) 상에 장착된 후 이루어지거나, 그 밖의 다른 방식으로(가령, 지지 웨이퍼가 캐리어 상에 사전에 장착됨) 이루어지며, 테이프 제거 스테이션(B.2)에서 이전 뒷면-연마(back grinding) 공정에서 제공된 뒷면-연마 테이프(back grinding tape)가 제거된다.
지지 웨이퍼(1)를 갖는 캐리어(5)는, 로봇 암(robot arm)(R)을 갖는 로봇(B.3)에 의해 핸들링된다.
핸들링 모듈(B) 상에는, 칩 스택(16)을 생산하기 위한 방법에 필요한 재료 및/또는 구성요소가 제거되거나 다시 제공되는 카세트 스테이션(cassette station)(B.4)이 존재한다.
칩 배치 시스템(A)에 칩을 배치한 후, 지지 웨이퍼(1) 및 상기 지지 웨이퍼(1) 상에 적층되어 있으며, 선택사항으로서, 접착제에 의해 고정되어 있는 칩이 실린 캐리어(5)가, 지지 웨이퍼(1) 상의 칩의 열처리 또는 본딩을 위한 본딩 스테이션(C)쪽으로 향해진다. 열처리 또는 본딩 동안, 다음 지지 웨이퍼(1)에 칩(9)이 제공될 수 있다. 또한 본딩 스테이션(C)은 복수의 본딩 유닛으로 구성될 수 있다. 요구사항 프로필에 따라, 본딩 공정은, 특히 칩 배치 공정과 비교할 때, 상당한 시간을 소모할 수 있다.
지지 웨이퍼(1) 상에 본딩되는 칩 스택의 그 밖의 다른 처리 단계(예를 들면, 다이싱 모듈(dicing module)에서의 칩 스택의 분리 단계)는 도 1에서 도시되지 않으며, 본딩 스테이션(C) 뒤에서 발생하거나, 핸들링 모듈(B)의 영역, 즉, 도 1에서 핸들링 모듈(B) 위에서 발생하여, 로봇 암(R)을 이용하는 칩 스택(16)의 핸들링이 가능해진다. 본 발명의 하나의 바람직한 실시예에서, 다이싱 모듈에서 캐리어(5)가 사용될 수 있으며, 그 결과로, 칩 스택(16)은, 지지 웨이퍼(1)와의 본딩 후에도, 안전하게 핸들링될 수 있다.
도 2a는 전기 전도성 박막(3')이 제공되는 앞면92)을 갖는 실리콘 지지 웨이퍼(1)를 도시하며, 이전 처리 단계에 의해, 상기 전기 전도성 박막(3')은 앞면(2)의 표면에서 돌출된다.
앞면(2)에 형성되는 다이싱 홈(17)은 지지 웨이퍼(1)를 칩 스택 섹션들(1c)로 나눈다.
다음 단계에서 지지 웨이퍼의 뒷면이 뒷면-연마되는 한, 다이싱 홈(17)은 지지 웨이퍼(1)의 두께의 일부분에만 걸쳐 있는 것이 바람직하다.
도 2b에 도시되어 있는 바와 같이 지지 웨이퍼(1)는 실리콘 웨이퍼와 마찬가지로 연결 수단(4)에 의해, 캐리어(5)로 연결되어, 지지 웨이퍼(1)의 뒷면(6)이 뒷면-연마될 수 있다(도 2c 참조). 여기서 지지 웨이퍼(1) 그리고 따라서 칩 스택 섹션(1c)은 뒷면-연마 동안 거의 자동적으로 분리되고, 그 결과로서 특히 서로 다른 열팽창이 칩 스택의 품질에 면에 영향을 덜 미친다.
도 2d에 나타나 있듯이, 각각의 박막(3') 영역에서, 지지 웨이퍼(1)의 뒷면(6)부터 각각의 박막(3')까지 뻗어있는 전기적인 연결(7)이 지지 웨이퍼의 뒷면(6)으로부터 생산된다.
칩(9) 상에서의 전기 전도성 박막(3)의 전기적 접촉을 위하여, 전기 전도성 박막(8)이 지지 웨이퍼(1)의 뒷면(6)에 있는 전기 전도성 연결(7)에 도포된다(도 2e 참조). 본 발명의 특별한 실시예에서, 칩(9)은 전기 전도성 연결(7)과 직접 접촉되거나, 다른 전기 전도성 링크 점이 생성될 수 있다.
도 2f에 나타나 있듯이, 바닥 측(10)에 배열된 박막(3)을 포함하는 칩(9)이 전기 전도성 박막(8)에 도포된다. 이러한 공정 시퀀스는 열처리 단계 또는 본딩 단계의 유무에 관계없이 개별 배치 단계들 사이에 발생한다.
도 2g에 나타난 공정 단계에 있어서, 칩(9)은 매스(11)에서, 본 예를 들면 에폭시 수지에서 포팅된다. 청구된 본 발명에서처럼, 선행하는 분리과정으로 인하여, 포팅 단계 전에, 특히 서로 다른 열팽창 계수의 물질에 있어서, 임의의 열팽창이 훨씬 더 작은 정도로 영향을 미친다.
공동(cavity)(18)은, 도 2n이 보여주듯이, 적절한 물질 선택 또는 선택사항으로, 가압에 의하여 도움을 받는 모세관 현상에 의한 페어링(pairing)에 의하여 채워지는 것이 바람직하다.
칩(9)의 본딩 및 매스(11)의 세팅 후에, 매스(11)가 얇은 웨이퍼(1)를 충분히 안정하게 할 수 있기 때문에, 캐리어(5)가 제거될 수 있다.
도 2g에 나타난 바와 같이(열에 때라), 포팅 단계에서 연결 수단(4)을 느슨하게 함으로써 캐리어(5)가 자동으로 분리될 수 있다.
더욱이 다운스트림 공정 단계에서 분리 단계를 따로 수행하는 것이 바람직할 수 있고, 분리 단계는 열적, 화학적 또는 외부 에너지원(예를 들면 자외선, 적외선, 레이저, 또는 마이크로파)의 작동에 의하여 시작될 수 있다.
도 2h에서 캐리어(5)가 분리되었고, 도 2i에서 연결 수단(4)이, 특히 세척 단계에서의 세척에 의하여 제거된다.
도 2k에서 알 수 있듯이 솔더 범프(12)를 박막(3')에 도포하기 위해 지지 웨이퍼(1)가 뒤집히고(도 2i 참조), 그리하여 앞면(2)이 지금은 위를 향하고 있다. 솔더 범프(12)는 칩 스택(16)(3d IC)을 기판 또는 다음 번 고차 팩킹 유닛/칩 층에 추후 연결하기 위하여 사용된다.
박막(3), 박막(3'), 박막(8) 및/또는 칩(9) 간의 연결을 위한 물질로서 다양한 변형예가 가능하다. 근본적으로 금속 화합물, 유기 화합물, 무기 화합물, 그리고 하이브리드 화합물 간의 구별이 가능하다. 금속 화합물 영역에서, 금속 확산 연결, 본딩 중에 형성되는 공융 연결, 그리고 본딩 전에 이미 존재하며 본딩 중에는합금의 융해를 가능하게 하는 공융물이 가능하다.
후자는 또한, 볼(ball) 형태로 박막(3, 3')으로 도포되며, 실질적으로 가압 없이 연결의 생성을 가능하게 하는 솔더 범프(12)이다. 전도성 폴리머 또한 가능하다.
도 2l에 도시된 공정 단계에서, 칩 스택(16)과 솔더 범프(12)를 포함하는 지지 웨이퍼(1)가, 도 2m에 도시된 것처럼 칩 스택(16)들을 서로 분리(다이싱)하기 위하여, 다이싱 프레임(13)에 연결된 테이프(14) 상에 증착된다.
분리는 다이싱 홈(17)의 영역에서, 특히 지지 웨이퍼(1)에 직각으로 일어난다. 결과적으로, 분리된 칩 스택(16)(3D IC)(도 2n)이 얻어지는데, 상기 분리된 칩 스택은 지지 웨이퍼(1)를 관통하는 전기 전도성 연결(7)(비아), 전기 전도성 박막(3, 8)을 통과하는 비아(7)로 연결되는 칩(9), 박막(3')에 부착된 솔더 비즈(12) 및 매스(11)를 갖는 지지 웨이퍼(1)의 칩 스택 섹션(1c)으로 구성된다.
A : 칩 배치 스테이션
B : 핸들링 모듈
B.1 : 이송 스테이션
B.2 : 테이프 제거 스테이션
B.3 : 로봇 암을 가진 로봇
B.4 : 카세트 스테이션
C : 본딩 스테이션
R : 로봇 암
1 : 지지 웨이퍼
1c : 칩 적층 섹션
2 : 앞면
3, 3' : 전기 전도성 박막
4 : 연결 수단
5 : 캐리어
6 : 뒷면
7 : 전기 전도성 연결
8 : 전기 전도성 박막
9 : 칩
10 : 바닥 측
11 : 매스
12 : 솔더 범프
13 ; 다이싱 프레임
14 : 테이프
16 : 칩 스택
17 : 다이싱 홈
18 : 공동

Claims (15)

  1. 지지 웨이퍼(1)에 복수의 칩(9)을 본딩하는 방법에 있어서, 지지 웨이퍼(1)는 지지 웨이퍼(1) 상에 적어도 하나의 층으로 적층되는 칩(3')을 포함하고, 수직으로 이웃하는 칩들을 더 연결하기 위한 전도성 연결(7)이 존재하고, 상기 방법은
    a) 지지 웨이퍼(1)를 캐리어에 고정하는 단계와,
    b) 칩(3)의 적어도 하나의 층을 상기 지지 웨이퍼(1) 상의 지정된 위치로 배치하는 단계와,
    c) 캐리어(5)에 고정되어 있는 지지 웨이퍼(1) 상의 칩(3)을 열처리하는 단계를 포함하고,
    단계 c) 이전에 지지 웨이퍼에서 지지 웨이퍼(1)의 분리된 칩 스택 섹션(1c)으로의 적어도 부분적인 분리가 발생하는 것을 특징으로 하는 지지 웨이퍼에 복수의 칩을 본딩하는 방법.
  2. 제 1 항에 있어서, 단계 b) 및 단계 c)는 서로 다른 장치에서 실행되는 것을 특징으로 하는 지지 웨이퍼에 복수의 칩을 본딩하는 방법.
  3. 제 1 항 또는 제 2 항에 있어서, 고정을 위한 고정 수단이 사용되며, 상기 고정 수단은, 특히 진공 수단, 정전기 수단, 기계적 클램핑, 접착제 중 하나 이상이며, 바람직하게는 상기 접착제는 내열 접착제인 것을 특징으로 하는 지지 웨이퍼에 복수의 칩을 본딩하는 방법.
  4. 제 1 항 내지 제 3 항 중 어느 한 항에 있어서, 지정된 위치로 칩을 배치할 때 칩(9)에 도포되는 전기 전도성 박막(3)은, 아래 놓이는 칩 층과 연결되기 위해 대응하는 전기 전도성 박막(8)에 정렬 및 본딩되는 것을 특징으로 하는 지지 웨이퍼에 복수의 칩을 본딩하는 방법.
  5. 제 1 항 내지 제 4 항 중 어느 한 항에 있어서, 칩은 배치된 후에, 바람직하게는 유기 접착제에 의해, 또는 분자 연결에 의해 접착되는 것을 특징으로 하는 지지 웨이퍼에 복수의 칩을 본딩하는 방법.
  6. 제 1 항 내지 제 5 항 중 어느 한 항에 있어서, 열처리는 280℃ 미만, 특히 250℃ 미만, 바람직하게는 220℃ 미만의 온도에서 특히 연속적으로 발생하는 것을 특징으로 하는 지지 웨이퍼에 복수의 칩을 본딩하는 방법.
  7. 제 1 항 내지 제 6 항 중 어느 한 항에 있어서, 단계 b) 또는 단계 c) 이후에, 칩(9) 또는 칩 스택(16)은 매스(11)로 포팅(potting) 처리되며, 상기 매스(11)는 특히 열적 고안정적 속성, 기계적 고안정적 속성, 화학적 고안정적 속성 및 발수(water-repellent) 속성 중 하나 이상을 띄며, 상기 매스(11)는 특히 유기물, 바람직하게는 에폭시 수지, 또는 세라믹 물질인 것을 특징으로 하는 지지 웨이퍼에 복수의 칩을 본딩하는 방법.
  8. 제 7 항에 있어서, 포팅(potting) 이후 지지 웨이퍼(1)가 캐리어(5)로부터 제거되는 것을 특징으로 하는 지지 웨이퍼에 복수의 칩을 본딩하는 방법.
  9. 제 7 항 또는 제 8 항에 있어서, 매스(mass)와, 포팅 공정 또는 포팅 공정 중, 상기 매스(11)로 포팅 처리된 칩(9)이 포함된 지지 웨이퍼(1)가 지지 웨이퍼(1)의 해당 기본 형태가 되거나, 및/또는
    상기 매스(11)가 칩(9)의 최상위 층인 한, 제거, 특히 연마되어 벗겨지는 것(grind off)을 특징으로 하는 지지 웨이퍼에 복수의 칩을 본딩하는 방법.
  10. 제 1 항 내지 제 9 항 중 어느 한 항에 있어서, 단계 b) 또는 단계 c) 후에, 특히 포팅 공정 후에, 각각의 칩 스택(16)의 기판 또는 또 다른 칩(9)으로의 연결을 위해 솔더 범프(12)가 도포되는 것을 특징으로 하는 지지 웨이퍼에 복수의 칩을 본딩하는 방범.
  11. 제 1 항 내지 제 10 항 중 어느 한 항에 있어서, 상기 지지 웨이퍼(1)와 캐리어(5) 중 하나 이상은 적오도 대부분 실리콘으로 구성되는 것을 특징으로 하는 지지 웨이퍼에 복수의 칩을 본딩하는 방법.
  12. 제 1 항 내지 제 11 항 중 어느 한 항에 있어서, 적어도 두 개의 칩(3) 층이 지지 웨이퍼(1)에 도포되는 것을 특징으로 하는 지지 웨이퍼에 복수의 칩을 본딩하는 방법.
  13. 제 1 항 내지 제 6 항 중 어느 한 항에 있어서, 단계 b) 또는 단계 c) 후, 칩(9) 또는 칩 스택이 매스(11), 특히 열가소성 물질로 고온-엠보싱(hot-emboss) 처리되는 것을 특징으로 하는 지지 웨이퍼에 복수의 칩을 본딩하는 방법.
  14. 제 1 항 내지 제 13 항 중 어느 한 항에 있어서, 칩 스택(16)이 이웃한 칩 스택(16)으로부터 분리되기 전에, 지지 웨이퍼 위에 적층된 칩(9)을 포함하는 지지 웨이퍼(1)가 다이싱 프레임(dicing frame)(13)에 고정되는 것을 특징으로 하는 지지 웨이퍼에 복수의 칩을 본딩하는 방법.
  15. 제 1 항 내지 제 14 항 중 어느 한 항에 있어서, 뒷면-연마(back-grinding) 중에 지지 웨이퍼(1)가 분리되는 것을 특징으로 하는 지지 웨이퍼에 복수의 칩을 본딩하는 방법.
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