JP2013505559A - ウエハにチップを結合する方法 - Google Patents

ウエハにチップを結合する方法 Download PDF

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JP2013505559A
JP2013505559A JP2012529140A JP2012529140A JP2013505559A JP 2013505559 A JP2013505559 A JP 2013505559A JP 2012529140 A JP2012529140 A JP 2012529140A JP 2012529140 A JP2012529140 A JP 2012529140A JP 2013505559 A JP2013505559 A JP 2013505559A
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chip
base wafer
chips
main part
wafer
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JP5769716B2 (ja
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マルクス・ヴィンプリンガー
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エーファウ・グループ・エー・タルナー・ゲーエムベーハー
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    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C

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Abstract

本発明は、前面側にチップ（３’）を含むベースウエハ（１）に複数のチップ（３）を結合する方法であって、前記チップ（３）が、前記ベースウエハ（１）の背面側で少なくとも一層に積層され、導電接続部が垂直に隣接するチップ（３、３’）間に組み立てられる方法に関連する。前記方法は、（ａ）前記ベースウエハ（１）の前面側（２）がキャリア（５）に固定される段階、（ｂ）チップ（３）の少なくとも一層が前記ベースウエハ（１）の背面側（６）の画定された位置に配置される段階、（ｃ）前記キャリア（５）に固定される前記ベースウエハ（１）の前記チップ（３、３’）が熱処理される段階を含む。前記方法は、段階（ｃ）の前に、前記ベースウエハ（１）のチップ（３’）が前記ベースウエハの積層チップ部分（１ｃ）に少なくとも分離されることによって特徴付けられる。

Description

本発明は、請求項１に記載された方法に関する。
半導体産業で広まっている圧力の縮小化の結果として、いわゆる“３次元集積回路（３Ｄ ＩＤ）”が製造され得る方法が望まれている。３Ｄ ＩＣｓは、幾つかのチップが垂直に積み重ねられ、シリコンから垂直に隣接するチップへの接続部があるチップ積層体からなる。この接続部は、“シリコン貫通ビア”（ＴＳＶ）と呼ばれる。
これらのチップは、高いパッキング密度及び低コストにおける高い性能を期待させる。さらに、この方法では、チップの新規なタイプ及び形態が製造され得る。基本的に、３Ｄ ＩＣｓを製造するために様々な方法が可能であり、具体的には、個々のチップに個々のチップを積層する非常に時間が掛かる積層、いわゆる“チップトゥーチップ”（Ｃ２Ｃ）法、又は、ウエハにウエハを積層する積層、いわゆる“ウエハトゥーウエハ”（Ｗ２Ｗ）法がある。最後に、いわゆる“チップトゥーウエハ（Ｃ２Ｗ）”法も検討される。合理的で技術的な実施は、主たる技術問題のために今までに成功していない。本発明は、３Ｄ ＩＣｓを製造する技術的に実現可能なＣ２Ｗ法に関する。
処理量が低いために、Ｃ２Ｃ法は、より高い製造コストをもたらし、従って大量生産において殆ど使用され得ない。
Ｗ２Ｗ法は、２つのウエハが同一の大きさを有し、２つのウエハ上のチップが同一の大きさを有することを要求する。ここでの問題は、特に高いチップ積層体用のシリコン利用が平均以下（いわゆる生産量）であることである。機能性チップの達成できる生産量は、Ｃ２Ｃ又はＣ２Ｗ法より低い。
チップ積層体又は３Ｄ ＩＣｓを製造するＣ２Ｗ法の実施における技術的な課題は、特にそれらの上に積層されたチップを有するウエハの取り扱い、及び、変更される仕様、特に積層工程、及び、回路板又は基本的にはより高次のパッキングユニットに載置するためのチップの接続（インターフェイス）における温度である。
従って、ウエハ上の複数のチップ積層体の分離の直ぐ前におけるベースウエハの破砕が数千の高価なチップの廃棄をもたらすので、ベースウエハの取り扱いは、大きな重要性を有する。その上に固定され／結合された複数のチップ積層体を有するベースウエハの取り扱いは、ベースウエハが薄ければ薄いほど、ベースウエハの面積が大きければ大きいほど、より困難である。ベースウエハは、チップがＣ２Ｗ法で積層されるウエハである。
ＵＳ２００７／００１２８１Ａ１は、チップが、メモリチップの製造において製造補給を単純化するためにベースウエハに積層され、次いで樹脂に埋め込まれる半導体メモリを製造する方法に関連する。埋め込み後、メモリチップは、それらの隣接するメモリチップから分離される。特に、チップ積層体に存在する多種の構成の様々な材料の異なる熱膨張係数は、製造中、主にメモリチップを埋め込む際にキャリアからの開放において、及び、後続の処理工程中に問題になる。
米国特許出願公開第２００７／００１２８１号明細書
本発明の目的は、可能な限り高い処理量で、可能な限り正確に位置するチップ積層体（３Ｄ ＩＣｓ）を製造するために可能な限りスクラップがない方法を考え出すことである。
この目的は、請求項１に記載の特徴を用いて達成される。本発明の有利な変更は、従属性急行に与えられる。明細書に、特許請求の範囲に及び／又は図面に与えられた特徴の少なくとも２つの全ての組合せは、本発明の枠組み内にある。任意の数値において、示された限度内の数値範囲は、境界値として開示されると見なされ、あらゆる組合せで特許請求の範囲に記載され得る。
本発明は、少なくともベースウエハ上におけるチップの積層中及び結合のためのチップの熱処理中にベースウエハを固定し、キャリアにウエハを固定し又はキャリアにウエハを接続し、及び、遅くても熱処理前にベースウエハを少なくとも部分的に分離し、特に、好ましくは互いに分離されるチップ積層体部分に分離する概念に基づく。
キャリアにベースウエハを固定することによって、Ｃ２Ｗ法の処理量において驚くべき利点を有して、チップをベースウエハの画定された位置に積層し又は配置する処理段階と、熱処理又はベースウエハ上のチップを熱処理し又はチップをベースウエハに結合する処理段階とを分離することが可能になる。熱処理又は結合段階は、使用される材料に依存して非常に長い時間を要する一方で、ベースウエハ上におけるチップの位置合わせ又は積層及び配置は、例えば１時間あたり数千チップという、非常に迅速に進行し得る処理段階である。熱処理中にベースウエハがさらに小さな部分に分離される場合、様々な構成／材料の熱膨張は、チップ積層体の品質に非常に僅かな影響を与える。分離の結果として、チップ積層体は、様々な膨張によって殆どストレスを受けない。
このように、幾つかの熱処理チャンバー／結合ステーションがあり、及び／又は、積層されたチップを有する幾つかのベースウエハが熱処理チャンバー／結合ステーションで処理されることによって、処理量は増加する。熱処理チャンバーは、高温プレート、連続炉、又はその同等物であり得る。特に有利な処理は、熱処理工程中にチップに圧力を加えることを可能にする修正されたウエハ結合チャンバーを用いて実施することである。
他の方法と比較して、この方法において異なるサイズのチップを積層することができる可能性は、特に有利である。
ベースウエハに単に緩く結合されていないキャリアを用いることによって、ベースのストレス及び反りが均一化され又は無効にされる。
取り扱いは、特に、１０ｍｍを超えて、特に５ｍｍを超えて、好ましくは２ｍｍを超えて、さらに好ましくは１ｍｍを超えて半径でベースウエハから外れないことによって、少なくても部分的にシリコン及び／又はガラスからなり、ベースウエハの大きさに基本的に対応するキャリアによって、さらに単純化される。
特に好ましい固定手段は、熱処理中の高温においてさえもキャリア上のベース上ウエハの確実な固定を保証するために使用される、陰圧又は真空、静電手段、機械的クランプ、及び／又は接着剤、好ましくは耐熱接着剤である。様々な固定手段又は効果の組合せは、組み立てられる接続部のタイプ、又は、チップ積層体の高さに依存して、又は、他の要因のために、さらなる改善された取り扱いをもたらし得る。
本発明の好ましい一実施形態においては、垂直に隣接するチップに付けられる導電薄膜の位置合わせ及び接触形成は、対応するチップの下層の導電接続部を用いて画定された位置におけるチップの配置に直接配置される。
この方法におけるチップ生産量は、チップの配置中に、チップがチップの下層の機能性チップにのみ配置されることが見られるという点で有利には改善され得る。さらに好ましくは、配置されるチップに機能的に接続される全てのチップの機能が確認され、チップは、チップに機能的に接続される全てのチップの機能を有してのみ配置される。
熱処理又は結合段階中に、導電接続部は、ウエハとその上に配置されるチップとの間、又は、配置されるチップ間に製造される。ここで、金属接触表面の酸化が避けられるように、加熱は、好ましくは酸素がない適切な雰囲気で行われる場合、有利である。特に、これは、窒素雰囲気又は他の不活性雰囲気、例えば、アルゴンの使用によって達成され得、多くの用途においては、不活性だけでなく、還元性雰囲気もまた特に有利である。この特性は、例えば気体又はギ酸蒸気を形成することによって実現され得る。形成気体は、特に９８％のＨ２に対する２％のＨ２と、８５％のＮ２に対する１５％のＨ２との間でＨ２をＮ２と混合することによって形成され得る。この混合物において、Ｎ２は、他の不活性気体に置き換えることも可能である。
チップがより良好に取り扱われ、それらが配置された後に滑らないように、配置後にチップを仮固定すること、特に、好ましくは後続の結合段階中に蒸発する有機接着剤を用いてそれらを接着することが有利である。あるいは、チップは、有利には室温で、例えばＳｉ表面、ＳｉＯ２表面、又はＳｉＮ表面間で自然に形成する分子結合によって固定され得る。他の代替案は、超音波溶接である。
有利には、熱処理は、特に連続的に、２８０℃未満の温度で、特に２５０℃未満で、好ましくは２２０℃未満で行われる。本願の特許請求の範囲に記載されるように使用される接着剤は、上述の温度に適しており、これらの接着剤は、最近になって全く利用可能である。これらの接着剤の一例は、米国のブルーワーサイエンス社（Brewer−Science Inc）のＨＡＴシリーズである。
本発明の特別な一形状のベースウエハは、特に裏面研磨によって、２００μｍ、未満、特に１００μｍ未満、好ましくは５０μｍ未満、より好ましくは２０μｍ未満の厚さを有する。
特に、多くのチップは、少なくとも２００ｍｍ、特に少なくとも３００ｍｍ、好ましくは少なくとも４５０ｍｍの直径を有するベースウエハに収容され得る。
本発明の特別な一実施形態において、本発明によってのみ、各々のチップ積層体をボードに又は基本的に次の高次のパッキングユニットに接続するための段階ｂ又はｃ後におけるＣ４バンプに半田バンプを適用することが可能である。
半田バンプは、低融点を有する金属合金からなり、一般的にチップ積層体を他の電気／電子部品に接続するために使用される。
特に、ベースウエハを貫通する導電接続部（ＴＳＶｓ）を有するベースウエハを用いる場合、段階ｂ又はｃ後におけるチップ又はチップ積層体を、高熱及び／又は機械的安定性及び／又は撥水加工特性によって特徴付けられる主要部、特に有機材料及び／又はセラミック材料からなることによって特徴付けられる主要部に埋め込むことが有利である。特に、少なくともある程度エポキシ樹脂が主要部に含まれ又は主要部が完全にエポキシ樹脂から形成される実施形態が望ましい。エポキシ樹脂含有主要部は、本発明の特別な一実施形態では繊維強化され得る。
有利には、主要部は、室温又は高温において液体形態で注がれる。
本発明の有利な一実施形態では、主要部は、特に大気圧以下、好ましくは真空での埋め込みを行った後における大気圧までの開放による埋め込み後に加圧される。さらに、これは、可能な間隙及び／又はキャビティが主要部で満たされることを可能にし、これは、チップ積層体の長期の信頼性に寄与する。
ベースウエハは、好ましくはヂュロプラスチック主要部の作用によって埋め込み後に、有利にはキャリアから外され得る。
本発明の好ましい一実施形態では、埋め込み後又は埋め込み中における主要部が、ベースウエハに対応する基本形状にされ、及び／又は、主要部が、チップの最上層の所まで除去され、特に研磨されるように、主要部は機能する。加えて、これは、ベースウエハ、埋め込まれたチップ及び主要部からなる本体の取り扱いをさらに単純化し、取り扱いのための特に周知の構成が使用され得る。主要部を除去することによって、放熱器は、形成される正確な平坦表面で最上部層に有利に付けられ得る。
本発明の特に好ましい一実施形態は、ベースウエハ及び／又はキャリアがシリコンからなり、従ってキャリアが同様にウエハであるというものである。それは、周知の構成を用いて取り扱われることができ、ベースウエハとキャリアがシリコンからなるという限りにおいてキャリアの熱膨張係数は等しいという利点を有する。
図１は、本願の特許請求の範囲に記載された方法の実施のためのユニットの構成を示す。 図２ａは、本願の特許請求の範囲に記載されたベースウエハの概略図を示す。 図２ｂは、本願の特許請求の範囲に記載された一時的な結合段階の概略図を示す。 図２ｃは、本願の特許請求の範囲に記載された裏面研磨段階の概略図を示す。 図２ｄは、ベースウエハに導電接続部を形成するための本願の特許請求の範囲に記載された段階の概略図を示す。 図２ｅは、本願の特許請求の範囲に記載された裏面金属化の段階、特にベースウエハの表面に対する導電薄膜の適用の概略図を示す。 図２ｆは、本願の特許請求の範囲に記載された研磨段階及び熱処理段階の概略図を示す。 図２ｇは、本願の特許請求の範囲に記載された埋め込み段階の概略図を示す。 図２ｈは、ベースウエハからキャリアを取り外すための本願の特許請求の範囲に記載された取り外し段階の概略図を示す。 図２ｉは、本願の特許請求の範囲に記載された洗浄段階の概略図を示す。 図２ｋは、半田バンプを付ける本願の特許請求の範囲に記載された段階の概略図を示す。 図２ｌは、フィルムフレームに対する本願の特許請求の範囲に記載された適用の概略図を示す。 図２ｍは、本願の特許請求の範囲に記載されたダイシング段階の概略図を示す。 図２ｎは、本願の特許請求の範囲に記載されたチップ積層体の概略図を示す。
本発明の他の利点、特徴及び詳細は、好ましい典型的な実施形態の以下の詳細な説明から及び図面を用いて明らかになるだろう。
図面において、同一の機能を有する同一の構成及び部品は、同一の参照符号で識別される。
図１は、本願の特許請求の範囲に記載された方法を実行するためのユニットの概略構成図を示し、領域Ａにおいて、ベースウエハ１のチップ層の配置は、図２ｆに示されるように行われ、ステーションＢ．１においてベースウエハ１が載置された後に、又は他の方法で、例えばキャリア５に事前配置（プレマウント）された後に、テープ除去ステーションＢ．２において、事前裏面研磨工程から存在する裏面研磨テープが除去されている。
ベースウエハ１を有するキャリア５は、ロボットアームＲを有するロボットＢ．３を用いて取り扱われる。
チップ積層体１６を製造する方法に必要な材料及び／又は部品が除去され又は再び搬送されるカセットステーションＢ．４がハンドリングモジュールＢにある。
チップ配置システムＡにおけるチップの配置後に、ベースウエハ１と、ベースウエハ１に積層され、接着剤を用いて任意に固定されるチップ９と、を有するキャリア５は、ベースウエハ１上へのチップの熱処理又は結合用の結合ステーションＣに送られる。熱処理中又は結合中に、次のベースウエハ１は、チップ９を備えられ得る。要求プロファイルに依存する結合が、特にチップの配置と比較して相当な時間を要するので、結合ステーションＣはまた、幾つかの結合ユニットからなり得る。
例えばダイシングモジュールにおけるチップ積層体１６の分離などの、ベースウエハ１に結合されたチップ積層体を用いた他の処理段階は、図１に示されないが、結合ステーションＣに続き得、又は、ハンドリングモジュールＢの領域に位置し得、従って、図１においてハンドリングモジュールＢの上部で、ロボットアームＲを用いたチップ積層体１６の取り扱いが可能になる。本発明の好ましい一実施形態では、キャリア５は、ダイシングモジュールに使用され得、その結果として、チップ積層体１６はまた、ベースウエハ１と結合した後でさえも、支障なく取り扱い続けることができる。
図２ａは、シリコンベースウエハ１を示し、その前面２には、その前の処理段階によって前面２の表面から突出した導電薄膜３’が備えられる。
前面２に形成されたダイシング溝１７は、ベースウエハ１をチップ積層体部分１ｃに分割する。ベースウエハが後の段階においてその後方から裏面研磨される範囲までは、ダイシング溝１７は、ベースウエハ１の厚さの一部のみまで有利には及ぶ。
図２ｂに示されるようなベースウエハ１は、キャリア５に接続され、ここで同様に、ベースウエハ１の背面６から裏面研磨されることを可能にするために、接続手段４を用いてシリコンウエハに接続される（図２ｃ参照）。ここで、ベースウエハ１及び従ってチップ積層体部分１ｃは、多かれ少なかれ、裏面研磨中に自動的に分離され、その結果として後に、特に異なる熱膨張が、チップ積層体の品質に非常に僅かな影響を与える。
図２ｄに示されるように、各々の薄膜３’の領域において、それぞれの薄膜３’までベースウエハ１の背面６から延びる電気接続部７は、ベースウエハ１の背面６から作られる。
チップ９上の導電薄膜３の電気接触形成のために、導電薄膜８は、ベースウエハ１の背面６における導電接続部７に付けられる（図２ｅ参照）。本発明の特別な実施形態では、チップ９はまた、導電接続部７に直接接触をもたらし、又は、他の導電連結点が作られ得る。
図２ｆに示されるように、底部側１０に配置されるそれらの薄膜３を有するチップ９は、導電薄膜８に付けられる。この工程手順は、個々の配置段階の間の熱処理段階又は結合段階の有無に関わらず行われ得る。ベースウエハ１上のチップ９の配置は、チップ配置ステーションＡで行われる。
図２ｇに示されるような工程段階において、チップ９は、この典型的な実施形態ではエポキシ樹脂である主要部１１に埋め込まれる。埋め込み段階の前の、本願の特許請求の範囲に記載されるような先の分離のために、あらゆる熱膨張は、特に異なる熱膨張係数の材料においては、非常に僅かな程度まで効果を生じる。
図２ｎに明確に示されるようなキャビティ１８は、有利には、任意に加圧によって支持される毛細管現象によって、相応しい材料選択又は組合せによって満たされ得る。
主要部１１が薄いウエハ１を十分に安定化するので、チップ９の結合及び主要部１１の設定の後に、キャリア５は、除去され得る。
キャリア５は、図２ｇに示されるような埋め込み段階において接続手段４を緩めることによって自動的に取り外される（加熱に依存して）。さらに、下流の工程段階で取り外し工程を個別に行うことが有利であり得、取り外し段階は、熱的、化学的、又は、外部エネルギー源（例えば、ＵＶ光、赤外光、レーザー又はマイクロ波）の作用の何れかによって開始され得る。
図２ｈにおいて、キャリア５は取り外されており、図２ｉにおいて、接続手段４は、特に洗浄段階における洗浄によって取り除かれる。
ベースウエハ１は、前面２が上を向くように、薄膜３’（図２ｉを参照）に半田バンプ１２を付けるための、図２ｋに示されるような工程段階において回転されている。半田バンプ１２は、ボード又は次の高次パッキングユニット／チップ層へのチップ積層体１６（３ｄ ＩＣｓ）の後の接続に使用される。
一連のバージョンは、薄膜３、３’、８及び／又はチップ９の間の接続のために材料として可能である。基本的に、金属化合物、有機化合物、無機化合物及びハイブリッド化合物間の区別をすることが可能である。金属化合物の領域において、金属拡散接続、結合中に形成する共晶接続、及び、結合前に既に存在し、合金の溶融を可能にする結合中における共晶接続が可能である。
後者はまた、ボールの形態の薄膜３、３’に付けられると共に圧力の印加なしに基本的に接続の生成を可能にする半田バンプ１２である。導電性高分子も可能である。
図２ｌに示されるような工程段階において、チップ積層体１６と半田バンプ１２を有するベースウエハ１は、次いで図２ｍに示されるように互いにチップ積層体１６を分離するために（ダイシング）、ダイシングフレーム１３に取り付けられるテープ１４に堆積される。分離は、特にベースウエハ１に垂直にダイシング溝１７の領域において行われる。結果として、図２ｎに示される分離されたチップ積層体１６（３Ｄ ＩＣ）は、ベースウエハ１を貫通する導電接続部７（ビア）を有するベースウエハ１のチップ積層体部分１ｃと、薄膜３’に取り付けられる導電薄膜３、８の半田ビーズ１２を介してビア７に接続されるチップ９と、主要部１１と、からなるように得る。
Ａ チップ配置ステーション
Ｂ ハンドリングモジュール
Ｂ．１ 移動ステーション
Ｂ．２ テープ除去ステーション
Ｂ．３ ロボットアームを有するロボット
Ｂ．４ カセットステーション
Ｃ 結合ステーション
Ｒ ロボットアーム
１ ベースウエハ
１ｃ チップ積層部分
２ 前面
３ 導電薄膜
３’ 導電薄膜
４ 接続手段
５ キャリア
６ 背面
７ 導電接続
８ 導電薄膜
９ チップ
１０ 底部側
１１ 主要部
１２ 半田バンプ
１３ ダイシングフレーム
１４ テープ
１６ チップ積層体
１７ ダイシング溝
１８ キャビティ

Claims (15)

  1. チップ（３’）を含むベースウエハ（１）に複数のチップ（９）を結合する方法であって、前記チップ（９）が、前記ベースウエハ（１）上で少なくとも一層に積層され、導電接続部（７）がさらに垂直に隣接するチップを接続するために組み立てられ、
    （ａ）前記ベースウエハ（１）をキャリア（５）に固定する段階と、
    （ｂ）画定された位置における少なくとも一層のチップ（３）を前記ベースウエハ（１）に配置する段階と、
    （ｃ）前記キャリア（５）に固定された前記ベースウエハ（１）の前記チップ（９）を熱処理する段階と、を備え、
    前記段階（ｃ）前に、前記ベースウエハ（１）の分離したチップ積層体部分（１ｃ）への前記ベースウエハ（１）の少なくとも部分的な分離が行われる、方法。
  2. 段階（ｂ）及び（ｃ）が、異なる装置で行われる、請求項１に記載の方法。
  3. 固定手段が、特に真空、静電手段、機械的クランプ、及び／又は、接着剤、好ましくは耐熱接着剤を固定するために使用される、請求項１または２に記載の方法。
  4. 画定された位置における前記チップ（３）の配置における前記チップ（９）に付けられる導電薄膜（３）が、前記チップの下層の接続のための対応する導電薄膜（８）に位置合わせされ、結合される、請求項１から３の何れか一項に記載の方法。
  5. 配置後の前記チップ（９）が、好ましくは有機接着剤又は分子結合によって付着される、請求項１から４の何れか一項に記載の方法。
  6. 熱処理が、特に連続的に、２８０℃未満の温度で、特に２５０℃未満で、好ましくは２２０℃未満で行われる、請求項１から５の何れか一項に記載の方法。
  7. 前記段階（ｂ）または（ｃ）後における前記チップ（９）又はチップ積層体（１６）が、特に高熱及び／又は機械的及び／又は化学的安定性及び／又は撥水加工特性によって特徴付けられ、有機材料、好ましくはエポキシ樹脂、又はセラミック材料である主要部（１１）に埋め込まれる、請求項１から６の何れか一項に記載の方法。
  8. 前記ベースウエハ（１）が、埋め込みの後に、前記キャリア（５）から除去される、請求項７に記載の方法。
  9. 埋め込み後又は埋め込み中における前記主要部（１１）と前記主要部（１１）に埋め込まれた前記チップ（９）とを有する前記ベースウエハ（１）が、前記ベースウエハ（１）に対応する基本形状にされ、及び／又は、前記主要部（１１）が、前記チップ（９）の最上層の所まで除去され、特に研磨される、請求項７または８に記載の方法。
  10. 段階（ｂ）又は（ｃ）の後に、特に埋め込みの後に、半田バンプ（１２）が、各々のチップ積層体（１６）をボード又は他のチップ（９）に接続するために付けられる、請求項１から９の何れか一項に記載の方法。
  11. 前記ベースウエハ（１）及び／又は前記キャリア（５）が、少なくとも主にシリコンからなる、請求項１から１０の何れか一項に記載の方法。
  12. 少なくとも２つの層のチップ（９）が、前記ベースウエハ（１）に付けられる、請求項１から１１の何れか一項に記載の方法。
  13. 段階（ｂ）又は（ｃ）の後における前記チップ（９）又はチップ積層体が、特に熱可塑性プラスチック材料である主要部（１１）と熱エンボス加工される、請求項１から６の何れか一項に記載の方法。
  14. 前記チップ積層体（１６）が隣接するチップ積層体（１６）から分離される前に、その上に積層された前記チップ（９）を有する前記ベースウエハ（１）が、ダイシングフレーム（１３）に固定される、請求項１から１３の何れか一項に記載の方法。
  15. 前記ベースウエハ（１）が、裏面研磨中に分離される、請求項１から１４の何れか一項に記載の方法。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014183097A (ja) * 2013-03-18 2014-09-29 Disco Abrasive Syst Ltd ウエーハの加工方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2299486B1 (de) * 2009-09-18 2015-02-18 EV Group E. Thallner GmbH Verfahren zum Bonden von Chips auf Wafer
KR20160075845A (ko) * 2010-03-31 2016-06-29 에베 그룹 에. 탈너 게엠베하 양면에 칩이 장착되는 웨이퍼를 제작하기 위한 방법
EP3035370A1 (de) * 2012-07-24 2016-06-22 EV Group E. Thallner GmbH Vorrichtung zum permanenten bonden von wafern
JP6278760B2 (ja) * 2014-03-11 2018-02-14 株式会社ディスコ チップ整列方法
KR102258743B1 (ko) * 2014-04-30 2021-06-02 삼성전자주식회사 반도체 패키지의 제조 방법, 이에 의해 형성된 반도체 패키지 및 이를 포함하는 반도체 장치
CN105893324A (zh) * 2015-01-26 2016-08-24 超威半导体产品（中国）有限公司 一种多芯片及其制造方法
CN107251212B (zh) * 2016-01-29 2020-08-18 业纳光学系统有限公司 用于从晶片中取出微芯片并且将微芯片施装到基底上的方法和设备
CN110214369A (zh) * 2017-03-02 2019-09-06 Ev 集团 E·索尔纳有限责任公司 用于键合芯片的方法和装置
US10790296B1 (en) * 2019-05-21 2020-09-29 Sandisk Technologies Llc Distortion-compensated wafer bonding method and apparatus using a temperature-controlled backside thermal expansion layer
CN110265526B (zh) * 2019-06-18 2020-07-24 上海纬而视科技股份有限公司 一种led封装工艺

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1174230A (ja) * 1997-08-29 1999-03-16 Nippon Telegr & Teleph Corp <Ntt> 薄膜半導体装置の製造方法
JP2001085363A (ja) * 1999-09-13 2001-03-30 Mitsui High Tec Inc 半導体装置の製造方法
JP2007012848A (ja) * 2005-06-30 2007-01-18 Elpida Memory Inc 半導体記憶装置及びその製造方法
JP2008130704A (ja) * 2006-11-20 2008-06-05 Sony Corp 半導体装置の製造方法
JP2008235401A (ja) * 2007-03-19 2008-10-02 Spansion Llc 半導体装置及びその製造方法
JP2009176957A (ja) * 2008-01-24 2009-08-06 Disco Abrasive Syst Ltd 積層型半導体装置の製造方法
JP2009188254A (ja) * 2008-02-07 2009-08-20 Oki Semiconductor Co Ltd 半導体装置及びその製造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0174773B1 (ko) * 1995-03-31 1999-04-01 모리시다 요이치 반도체장치의 검사방법
JP4128319B2 (ja) * 1999-12-24 2008-07-30 株式会社新川 マルチチップボンディング方法及び装置
US6492196B1 (en) * 2002-01-07 2002-12-10 Picta Technology Inc. Packaging process for wafer level IC device
US7109635B1 (en) * 2003-06-11 2006-09-19 Sawtek, Inc. Wafer level packaging of materials with different coefficients of thermal expansion
JP4741332B2 (ja) * 2005-09-30 2011-08-03 株式会社ディスコ ウエーハの加工方法
DE102006000687B4 (de) * 2006-01-03 2010-09-09 Thallner, Erich, Dipl.-Ing. Kombination aus einem Träger und einem Wafer, Vorrichtung zum Trennen der Kombination und Verfahren zur Handhabung eines Trägers und eines Wafers
US7727806B2 (en) * 2006-05-01 2010-06-01 Charles Stark Draper Laboratory, Inc. Systems and methods for high density multi-component modules
JP4927484B2 (ja) * 2006-09-13 2012-05-09 株式会社ディスコ 積層用デバイスの製造方法
JP2008098427A (ja) * 2006-10-12 2008-04-24 Toshiba Corp 半導体装置の製造方法
US8102734B2 (en) * 2007-02-08 2012-01-24 St. Jude Medical, Atrial Fibrillation Division, Inc. High intensity focused ultrasound transducer with acoustic lens
EP2104138A1 (de) * 2008-03-18 2009-09-23 EV Group E. Thallner GmbH Verfahren zum Bonden von Chips auf Wafer
US7863092B1 (en) * 2008-09-30 2011-01-04 Xilinx, Inc. Low cost bumping and bonding method for stacked die
WO2010057339A1 (en) * 2008-11-19 2010-05-27 Hong Kong Applied Science and Technology Research Institute Co. Ltd Semiconductor chip with through-silicon-via and sidewall pad
EP2299486B1 (de) * 2009-09-18 2015-02-18 EV Group E. Thallner GmbH Verfahren zum Bonden von Chips auf Wafer
US8552567B2 (en) * 2011-07-27 2013-10-08 Micron Technology, Inc. Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1174230A (ja) * 1997-08-29 1999-03-16 Nippon Telegr & Teleph Corp <Ntt> 薄膜半導体装置の製造方法
JP2001085363A (ja) * 1999-09-13 2001-03-30 Mitsui High Tec Inc 半導体装置の製造方法
JP2007012848A (ja) * 2005-06-30 2007-01-18 Elpida Memory Inc 半導体記憶装置及びその製造方法
JP2008130704A (ja) * 2006-11-20 2008-06-05 Sony Corp 半導体装置の製造方法
JP2008235401A (ja) * 2007-03-19 2008-10-02 Spansion Llc 半導体装置及びその製造方法
JP2009176957A (ja) * 2008-01-24 2009-08-06 Disco Abrasive Syst Ltd 積層型半導体装置の製造方法
JP2009188254A (ja) * 2008-02-07 2009-08-20 Oki Semiconductor Co Ltd 半導体装置及びその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014183097A (ja) * 2013-03-18 2014-09-29 Disco Abrasive Syst Ltd ウエーハの加工方法

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