TW457657B - Wafer-level packaging of micro electromechanical elements and fabrication method thereof - Google Patents

Abstract

The present invention provides a wafer-level packaging of micro electromechanical elements and a fabrication method thereof, which includes a silicon wafer having a plurality of micro electromechanical elements and a packaging silicon wafer having the same size as the silicon wafer. A plurality of channels are formed between the top and bottom surfaces of the packaging silicon wafer. A metal conductive cylinder is formed in each channel to electrically connect the top and bottom surfaces of the packaging silicon wafer. There is formed a soldering bump on the metal conductive cylinder such that the soldering bump on the metal conductive cylinder can attach to a predetermined soldering bump on the silicon wafer having a plurality of micro electromechanical elements, thereby forming a packaging device.

Description

407657 V. Description of the invention ¢ 1) Field of the invention: The present invention relates to a wafer-level packaging technology, in particular to a wafer-level packaging method for a micro-electro-mechanical device and a packaging device formed by the same ^ Background of the Invention: In the field of semiconductors Micro-machining technology (micr 〇machiningtech η o 1 ogy) is a new emerging technology, which is used to manufacture various micro-sensing elements and micro-brakes; In addition, micro-processing technology and microelectronic circuits can form a micro-system after integration, said It is a micro electromechanical system (MEMS). For related information, please refer to: K. Ε, Peterson, Silicon as a mechanical material, IEEE Proc. 7 0, 4 2 0, (1 9 8 2).; S. M i dd e1h oek and SA Audet, Silicon Sensors, Academic Press, New York, (1989); RS Muller, RT Howe, SD Senturia, RL Smith, and RM White, ed s., Microcrosensors, IEEE Press, New york, (19 9 1); SM Sze, ed ., Semiconductor Sensors,

John Wiley & Sons Inc., (1994) ° Different from the conventional integrated circuit manufacturing technology, the related manufacturing technologies that constitute MEMS are quite extensive and complex, but their common point is that most MEMS components are The use of micro-machining technology to create a floating structure with only a few branches to increase its mechanical sensitivity (such as pressure sensors, etc.), or to reduce its thermal conductivity characteristics (such as thermal sensors, etc.). The conventional integrated circuit device production process is to produce integrated circuit components on a second wafer (wa fer). The wafer is cut into a plurality of single-wafers (ch 1 p

V. Description of the invention ¢ 2)), and then encapsulation through steps such as bonding wire (w i r e b ο n d i n g), sealing glue and so on. Based on cost considerations, if this integrated circuit production process can be applied to the production of micro-electromechanical components, it will be beneficial to the development of this industry. However, there are several problems that must be faced: first, the scouring of cooling water during cutting (dici ng) and the fines generated by cutting will damage the suspended components and reduce their yield; further, during the sealing process The micro-components will be fixed, and the original design will be lost as a floating structure to enhance its sensitivity. Therefore, the present invention is to propose a packaging method suitable for micro-electro-mechanical components to avoid the damage caused during the above-mentioned packaging process. OBJECTS AND SUMMARY OF THE INVENTION: The main object of the present invention is to provide a wafer-level packaging method for micro-electro-mechanical devices, and provide a packaging device formed by the manufacturing method. Another object of the present invention is to prevent the micro-electromechanical component from being damaged due to external force during the packaging process. Another object of the present invention is to use a silicon wafer as a package base. In addition to making the entire packaging device have good flatness and maintaining good contact with the chip package, it also has better thermal conductivity characteristics in order to make the package The rear module has good heat dissipation effect. According to the present invention, a silicon wafer having a plurality of microelectromechanical elements and a packaged silicon wafer of the same size are bonded together, and the metal silicon pillars between the upper and lower surfaces of the packaged silicon wafer are used to conduct the packaged silicon crystal. The upper and lower sides of the circle form an electrical connection. Detailed descriptions are provided below with specific embodiments and accompanying drawings.

457057 V. Description of the invention (3) It is easy to understand the purpose, technical content, features and functions of the present invention. Description of drawing number · 1 0 4 protection ring 204 metal conductor post 2 0 8 protection ring 2 1 2 etching window 2 1 6 etching window 220 perforation 224 conductive starting layer 10 microelectromechanical element silicon wafer 1 0 2 solder bump 1 0 6 Micro-Electro-Mechanical Components 20 Packaged Silicon Wafer 2 0 2 Cavity 2 0 6, 2 0 6 'Solder Bump 2 1 0 Overlay 2 1 4 Overlay 2 1 8 Trench 222 Dielectric Layer 2 2 6 Adhesive Film 3 〇Single module 3 2 Solder joints 34 Cutting lines Detailed description: The main feature of the present invention is to use the conductive pillars of the silicon wafer for packaging and solder bonding to electrically connect the input / output pads of the micro-electromechanical components to the packaging silicon. The exposed side of the wafer is bonded to the micro-electro-mechanical device silicon wafer and then cut into a plurality of single modules. As shown in the first figure, it is a schematic flow chart of the micro-electro-mechanical device wafer-level packaging technology of the present invention. It is a method of bonding the micro-electro-mechanical device silicon wafer 丨 0 and the same-size silicon wafer 20 for packaging by solder. Together and then cut

Page 6 ^ 57657 Five 'invention description ¢ 4) into individual single modules 30. The biggest advantage of this method is that the micro-electro-mechanical components can avoid damage caused by external forces during the aforementioned packaging process; and the use of silicon wafers as the package base has a relatively good flatness, which is more suitable for wafer-level packaging than other materials. It will not cause poor contact of some chip packages due to the unevenness of the package base. Moreover, the thermal expansion coefficient of a wafer can be considered to be the same. The thermal residual stress caused by temperature effects during the packaging process is also smaller than other packaging materials. , Such as: glass, ceramic 'printed circuit boards, and so on. At the same time, the silicon material has good thermal conductivity and has a good heat dissipation effect on the packaged module. Compared to the first figure, a more detailed schematic description of the present invention can be seen in the second figure, which is a partial enlarged process sectional view of the present invention. As shown in the figure, the upper layer is a micro-electro-mechanical device silicon wafer 10, and a plurality of micro-electro-mechanical devices (not shown in the figure) are produced inside. The outermost surface of the wafer 10 corresponds to the input / output of each wafer. A plurality of solder & solder bumps (solder bumpM 02) are produced on the solder pad (I / 0 b ο ndingpad), and another solder bump is produced on the periphery to form a solder & guarding ring (guarding) 1 0 4 to surround Protect the entire internal components; the other packaged silicon wafer 20 as a package base is a micro-electromechanical component of the same size as the wafer 10 on the surface of the packaged silicon wafer 20 and corresponding to the wafer 10 A plurality of cavities 2 0 2 are formed at the positions to cover the corresponding micro-electromechanical components. In the packaged silicon wafer 20, a plurality of metal conductive posts 2 0 4 penetrates through them, and two ends of the conductive post 2 0 4 are respectively A plurality of solder bumps 2 06, 2 06 'and solder bump guard ring 2 0 8 were produced, and their positions were respectively related to the solder bumps 102 and the guard ring 1 on the micro-electromechanical device silicon wafer 10. Corresponding to 0 4, the packages of the two wafers 10 and 20 are transmitted through a plurality of solder bumps 1 0 2 and 2 0 6 Protective ring

457657 V. Description of the invention (5) 1 0 4 and 2 0 8 are bonded to each other to form a plurality of solder joints 3 2. The bonding method and process are described as follows: After the fabrication of the solder bump is completed, a double-side aligner (such as: Electronic Vision EV-620) is used to combine the micro-electromechanical device silicon wafer I 0 and the packaged silicon wafer. 2 0 Align with each other, and then fix it with a clamp. The fixed module is then moved to the bonding machine (Electronic Vision EV-560) (the bonding machine has the functions of heating, pressure and vacuum, so it can be used as airtight or even vacuum packaging). The steps of temperature, pressure, and shock welding are completed to complete the bonding process. Finally, the packaged wafer is cut into a plurality of single modules 30 through a predefined scribe line 3 4. Among them, the above-mentioned technical method in which a plurality of metal conductor posts 204 are formed in the packaged silicon wafer 20 will be described in detail later; as for the fabrication of solder bumps 102 on the solder pads of wafer 10, The conventional technology of body circuit packaging is not repeated here. At the same time with the three-dimensional structure shown in the third figure, the structure of the wafer-level packaging device of the micro-electro-mechanical device is better understood. 6. The component types are not limited here. A plurality of solder bumps 102 are provided on the input / output pads of the wafer 10 corresponding to each wafer, and a protective ring 1 is formed on the periphery. 0 4, to surround and protect the entire internal micro-electro-mechanical element 106;-a plurality of cavities 2 0 2 are formed on the surface of the packaging silicon wafer 20 for the packaging substrate and corresponding to the micro-electro-mechanical element I 0 6, The corresponding micro-electromechanical element 106 is covered, and a plurality of metal conductor posts 2 0 4 are arranged between the upper and lower surfaces of the packaged silicon wafer 20, and solder is produced at both ends of the conductor post 204. Bump 2 0 6

Page 8 457657 ____ ______ _________- —— V. Description of the invention (6) and guard ring 2 0 8 whose positions are respectively related to the solder bump 1 0 2 and guard ring 1 0 4 on the micro-electromechanical device silicon wafer 10 Correspondingly, the micro-electro-mechanical device silicon wafer 10 uses the solder bumps 102 and the guard ring 10 on the micro-electromechanical element. The solder block 2 0 6 and the guard ring 2 0 are mounted on the packaged silicon wafer 2 0. 8 on. Among them, through the adhesion of the protective rings 104, 208 formed on the two wafers 10, 20, depending on the types and requirements of the micro-electromechanical components, it can provide air-tight and even vacuum packaging. Therefore, the present invention is to provide a wafer-level packaging technology suitable for MEMS devices. Figures 4a to 4h are cross-sectional views showing a part of the manufacturing process of the packaged Shixi wafer of the present invention. As shown in Figure 4a, the size and size of the silicon wafer 20 for packaging is the same as that of the micro-electromechanical device silicon wafer 10, and a cover layer 210 is formed on the surface of the silicon wafer 20, which is usually an oxide. A first mask lithography (photo 1 i thography) is used to form a plurality of etch windows 212 on the first surface of the silicon wafer 20 and corresponding to the micro-electro-mechanical components of the Shi Xi wafer. 'To expose the silicon material. As shown in FIG. 4b, a plurality of cavities 2 0 2 are formed on the surface of the silicon wafer 2 0 through the #scribed window 2 1 2 using an anisotr etching method, and then the cover layer 210 is removed. . Another cover layer 214 is grown on the surface of the broken wafer 20, which is usually a oxidized stone, as shown in FIG. 4c, and a plurality of #etches are formed on the first surface of the wafer 20 by photolithography. Window 2 丨 6 to expose Shi Xi material. Please refer to Figure 4d. Using high-density plasma reactive ion etching (high dens Uy plasma reactive ion etching HDP R IE ’), the method is to use inductive coupling to generate high-density plasma’, so it ’s also called inductively coupled

Page 9 457657 V. Description of the invention (7) Plasma ICP RIE, for example: Alcatel 601E), is etched on the stone 々 7 7 Japanese yen 20 through a plurality of etching windows 2 1 6 and has a plurality of ridges < The trench 218 of the official wall, and the depth of the trench 218 can be easily outside the J-tooth stone wafer 20. The etching gas used in I CP RIE is mainly six t,% sulphur (SF 6). The depth-to-width ratio of trench 22 after etching can be as high as 30 or more, and the etch rate of Shi Xi material at η 可以 can reach丨 0 / im / mi η. For example, if the thickness is about 670 / z m, the smallest groove size can be as follows, and the pitch size can also be less than 50 // out. As shown in figure 4e, 'using the CP RIE engraving technique, a plurality of perforations 2 2 0 are formed in Shi Xiyue, and the cover layer 2 1 4 is removed: then the circle 20 is formed on the 20 surface and the plurality of perforations 22 is formed. Another dielectric layer 22 is grown on the surface for wafer-type insulation. The material of the dielectric layer 22 may be the aforementioned silicon oxide—an electrochemical silicon material. As shown in FIG. 4f, the electrochemical deposition = nitrogen is used as the metal conductor post 205, and the steps are as follows: a conductive adhesive film 226 is fixed on one surface of the wafer 20, and conductive Start; f 24 considers conductive metals such as Shao, Lu, Titanium, etc., and uses them: 2: 4 ordinary cathode. Electrodeposition of daggers is shown in Figure 4g. Electrochemical deposition can be used to inject pleated peasants at low temperatures,. 4 metals are provided with several perforations 2 2 0, and then the glue 2 is removed. Ftu ... The starting layer 224 is the injection operation of the ship b on the Chung-do road and the pilot Fan Yicheng ¥ qi 205. Finally, as shown by the child, complete the metal jealousy ^ ^ Sisi hi! Η Λ "After the injection operation of the temperature column 2 0 5, immediately make the bismuth and other materials at the two ends of the view u 2 0 5 The body bar is provided with a plurality of solder bumps 206, 206, and 208. In addition, according to the present invention, A-P-Yu can inject low-dazzling tin / lead alloy through metal melting method. Α 点 金 遛 王, Wang entered a number of perforations, the method is to

Page 10 457657 V. Description of the invention (8) A certain amount of low melting point metal is placed on the perforated packaged silicon wafer, the above combination is made into a dense mold, and the mold is heated. When the temperature reaches the melting point of the metal conductor, The metal conductor is injected into the perforation by the pressure of the pressure plate on the mold or the vacuum at the bottom of the mold. In order to highlight the innovative implementation of the present invention, Figures 5a to 5c are the actual use of ICPRIE to complete wafer perforation, injecting electroplated nickel metal into the perforation, and melt-injecting low melting tin / lead alloy into the perforation. Photographs to prove the feasibility of the invention. The above-mentioned embodiments are only for explaining the technical ideas and characteristics of the present invention. The purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. When the scope of the patent of the present invention cannot be limited, Any equal changes or modifications made according to the spirit disclosed in the present invention, such as non-hermetic packaging, should still be covered by the patent scope of the present invention.

4 5 7 6 5 7 Case No. Μίί4069_ 年月 日 __ Round type brief description Schematic description: The first figure is a schematic diagram of the packaging technology process of the present invention. The second figure is a partial enlarged flow chart of the present invention. The third figure is a schematic diagram of the three-dimensional structure of the single module shown in the second figure. Figures 4a to 4h are partial cross-sectional views of the manufacturing process of the packaged silicon wafer of the present invention. Figures 5a to 5c are schematic diagrams of actual photographs of metal conductor posts made according to the present invention.

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Claims (1)

457657 6. Scope of patent application 1. A wafer-level package of micro-electro-mechanical components, including: a micro-electro-mechanical device silicon wafer, a plurality of micro-electro-mechanical components are fabricated inside, and the wafer's outermost surface corresponds to A plurality of solder bumps are fabricated on the input / output pads, and a solder bump protection ring is formed on the periphery of each crystal moon to surround the entire internal micro-electromechanical components and input / output pads; and a silicon wafer for packaging The substrate is the same size as the silicon wafer of the micro-electro-mechanical device. A plurality of cavities are formed on the surface of the substrate and corresponding to the micro-electro-mechanical device to cover the corresponding micro-electro-mechanical device. A plurality of metal conductor pillars are arranged between the upper and lower surfaces, and a plurality of solder bumps are made at both ends of the conductor pillar, and a solder bump protection ring is made on the first surface of the silicon wafer substrate. The positions correspond to the solder bumps and the solder bump protection ring on the MEMS silicon wafer, respectively, and the MEMS silicon wafer is mounted on the MEMS silicon wafer with the solder bump and the solder bump protection ring thereon. The solder bump and solder bump protection ring of the silicon wafer substrate used for mounting ^ 2. —A method for manufacturing a silicon wafer for packaging of a wafer-level package suitable for micro-electromechanical components, including the following steps: A cover layer is formed on the surface of a packaging substrate; a plurality of etching windows are formed on the first surface of the substrate and corresponding to the micro-electro-mechanical components of the silicon wafer by using a first photolithography technique; And a plurality of cavities are formed on the first surface of the substrate through the etching window through the etching window; the cover layer is removed; another cover layer is grown on the surface of the substrate; A plurality of etched windows are formed on the first surface of the substrate Page 13 157657 VI. Scope of patent application After the high-density plasma ion etching method is used to etch out a plurality of perforations penetrating vertically through the substrate through the etching window, the cover layer is removed; the substrate and the perforations are removed. An insulating dielectric layer is formed on the surface; a metal conductor post is made at each of the through holes; and a solder bump is made at two ends of each of the metal conductor posts. 3. The manufacturing method as described in item 2 of the scope of patent application, wherein the metal conductor post is a nickel or copper or gold metal produced by chemical or electrochemical deposition method. 4. As described in item 2 of the scope of patent application The manufacturing method, wherein the metal conductor post is used to inject a low-melting-point metal conductor into a plurality of the perforations by a metal melting method. 5. The manufacturing method according to item 4 of the scope of patent application, wherein the metal melting method includes the following steps: placing a predetermined amount of a low-melting-point metal conductor on the wafer having a plurality of perforations; and placing the above combination into In a tight mold, heat the mold; when the temperature reaches the melting point of the metal conductor, the pressure of the platen on the mold or the bottom of the mold is evacuated, and then the metal conductor is injected into the perforation ^ Page 14