CN110214369A - 用于键合芯片的方法和装置 - Google Patents
用于键合芯片的方法和装置 Download PDFInfo
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- CN110214369A CN110214369A CN201780085240.8A CN201780085240A CN110214369A CN 110214369 A CN110214369 A CN 110214369A CN 201780085240 A CN201780085240 A CN 201780085240A CN 110214369 A CN110214369 A CN 110214369A
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Abstract
提出了一种用于将芯片(7)键合到衬底(11')上或键合到其它芯片上的方法,其特征在于,所述芯片(7)通过直接键合来被键合到所述衬底(11')或者所述其它芯片上。
Description
技术领域
本发明涉及一种用于键合芯片的方法和装置。
背景技术
在现有技术中描述经由焊料球或具有焊料帽的铜柱(英文Copper pillars withsolder caps)来实施芯片到晶圆(C2W)或芯片到芯片(C2C)工艺。然而,焊料球或具有焊料帽的铜柱极大而且使这样产生的芯片的厚度增加。
发明内容
因此,本发明的任务是说明一种经改善的键合方法或一种经改善的键合装置或一种经改善的产品。
该任务利用专利并列权利要求的主题来解决。本发明的有利的扩展方案在从属权利要求中说明。由在说明书、权利要求书和/或附图中说明的特征中的至少两个特征构成的全部组合也落入到本发明的保护范围内。在所说明的值域的情况下,在所提到的极限之内的值也应明显被看作是极限值并且应该能以任意的组合来要求保护。
根据本发明,规定了一种用于将芯片键合到衬底、尤其是半导体衬底上或键合到其它芯片上的方法,其中通过直接键合将这些芯片键合到衬底或者其它芯片上。直接键合被理解为直接经由两个表面的相互作用构造的、未形成液相的键合。根据另一术语定义,直接键合被理解为其中不必使用附加材料的键合。直接键合尤其被理解为金属-金属固体键合,尤其是扩散键合、预键合或由预键合引起的熔合键合或者混合键合、也就是说基于熔合键合部分以及金属键合部分的键合。
根据本发明,还规定了一种用于将芯片键合到衬底或其它芯片上的装置,其中可以通过直接键合将这些芯片键合到衬底或者其它芯片上。
根据本发明,还规定了一种由芯片构成的芯片堆,其中这些芯片通过直接键合来彼此键合。
根据本发明,还规定了一种具有芯片的衬底(产品),其中这些芯片通过直接键合来键合至该衬底上。
根据本发明,能够实现在C2C或C2W层面上的直接键合可能性。有利地,不再需要焊料球或具有焊料帽的铜柱。所产生的芯片堆或产品的厚度变得更小,吞吐量提高而且芯片通信的效率升高。直接键合尤其具有大于0.1 J/m2、优选地大于0.5 J/m2、还更优选地大于1.0 J/m2、最优选地大于2.0 J/m2、尤其最优选地大于2.5 J/m2的键合强度。直接键合尤其是在小于400℃、优选地小于300℃、还更优选地小于200℃、最优选地小于150℃、尤其最优选地小于100℃的温度下进行。此外,直接键合在不产生液相的情况下进行。
本发明所基于的思想在于:保持芯片的表面清洁,使得可进行接下来的直接键合步骤。接着,可将这样制备的包括无污染的键合表面的芯片键合到衬底上(英文:chip-to-wafer(芯片到晶圆),C2W)或键合到其它芯片上(英文:chip-to-chip(芯片到芯片),C2C)。
在本披露的进一步进程中,衬底或半导体衬底被理解为半导体行业的尚未分离的、尤其是圆形的半成品。特别有利地,衬底是晶圆。衬底可具有任何任意的形状,但是优选地为圆形。衬底的直径尤其是有行业标准。对于晶圆来说,行业常用的直径是1英寸、2英寸、3英寸、4英寸、5英寸、6英寸、8英寸、12英寸和18英寸。但是,根据本发明的实施方式原则上可运用任何衬底,与该衬底的直径无关。
在本披露的进一步进程中,芯片被理解为通过分离半导体衬底(晶圆)来获得的、大多是矩形的零件。芯片通常包含集成电路,该集成电路在加工半导体衬底时形成。
在本披露中,键合表面被理解为在工艺期间将在某一时刻变成键合分界面的部分的表面。特别地,键合表面被理解为在芯片被键合之前该芯片的必须根据本发明来处理、尤其是清洁的表面。如果将芯片键合至衬底上,则衬底表面也可被称作键合表面。
在一个优选的实施方式中,键合表面是混合键合表面。混合键合表面被理解为如下键合表面,该键合表面由金属区和介电区组成并且借此由金属键合表面部分和介电键合表面部分组成。因此,所有在本披露中提到的通常涉及直接键合的方法和/或装置可应用于混合表面的键合。优选地,金属表面部分和介电表面部分尽可能位于一个平面内。尤其是,金属表面部分相对于介电表面部分凹入或相对于介电表面部分突出小于0.5 μm、优选地小于100 nm、更优选地小于50 nm、最优选地小于10 nm。
清洁方法
在进一步披露中,清洁被理解为通过如下方法中的一个和/或多个方法来除去键合表面的污染:
· 湿化学清洁,尤其是
○ 用水,尤其是
▪ 含CO2的水
○ 用醇
○ 用酸,尤其是
▪ 甲酸
▪ 柠檬酸
▪ 过氧单硫酸
·标准清洁1(SC1)
- 标准清洁2(SC2)
○ 用碱,尤其是
▪NH4OH
· 等离子体清洁
· 等离子体灰化
· 机械清洁,尤其是
○刷洗。
等离子体清洁被理解为用等离子体的离子化部分对表面的轰击、一般是高能量的轰击。在此,等离子体的离子通过电场和/或磁场来加速而且具有不可忽视的渗入深度。等离子体清洁可伴随着表面的等离子体活化。
等离子体灰化被理解为对表面的有机物的清洁工艺、一般是低能量的清洁工艺。清洁在此尤其是通过有机物的尤其是与氧和/或氟或任何其它适合的并且可离子化的氧化剂的氧化而实现。优选地,通过等离子体灰化而被氧化的有机成分从反应室排出。这或者通过等离子体的持续的流动或者通过对等离子体室的连续的充气和排气来实现。然而,在一个更优选的实施方式中,通过化学和/或物理方法在等离子体室之内使被灰化和被氧化的有机成分键合,使得防止这些有机成分回到衬底表面。由此,避免了以等离子体的循环为前提的复杂装置。
可选地,在等离子体灰化之后,利用上面提到的液体中的一种或多种液体来执行湿化学清洁,以便借此还进一步改善表面的清洁度和/或待清洁的表面的表面化学,尤其是通过利用适合的、本领域技术人员公知的物质终止该表面来优化表面的清洁度和/或待清洁的表面的表面化学。有利地,该方法用于:除去颗粒、尤其是在等离子体灰化时形成和/或残留在表面上的颗粒。
因此,也可通过所提到的方法中的多个方法来执行对键合表面的清洁。该清洁可以在一个芯片上执行或者在多个芯片上同时执行。尤其是,各个芯片可以在两个阶段之间运输时被清洁。
自对准
在一个优选的实施方式中,芯片被定位并且进行芯片的自对准。自对准(英文:selfalignment)被理解为对对象、在当前情况下是芯片的通过最小化的物理定律来驱动的定位过程。
自对准优选地通过如下方式来实现:芯片在键合表面上以极小的静摩擦、尤其是由于在键合表面上沉积的液体引起的极小的静摩擦来驱动到键合表面的特征部之间的位置、尤其是中心的位置。
例如,会是可设想的是:例如有四个金属区、尤其是如接触垫那样的金属键合面处在键合表面上,尤其是作为混合键合表面的部分或通道。芯片在其键合表面上同样具有四个区。如果将这种芯片放到液体上,则出发点应该是:更亲水区将定位于更亲水区上方,而更疏水区将定位于更疏水区上方。因此,将出现对准,其中混合键合表面的金属区将被覆盖。
本领域技术人员清楚的是,参与自对准的结构的对称性越高,这种自对准就可以实现得越好。属于此的是芯片的几何形状、混合键合表面的金属区之间的距离、金属区的形状等等。优选地,芯片应该是方形的。此外,混合键合表面的金属区优选地同样应该位于所设想的方形的角上。如果在相对应的混合键合区的亲水性与疏水性之间的差异尽可能大,则将会存在另一优点。构造在测试液滴、尤其是水与待测量的表面之间的接触角是对亲水性或疏水性的量度。亲水表面使液滴平坦,因为液体与表面之间的黏着力超过液体的内聚力而占主导,并且因此形成小的接触角。疏水表面导致液滴的球形形态,因为液体的内聚力超过液体与表面之间的黏着力而占主导。优选地,在两个不同的所提到的混合键合区之间的接触角差大于1°、优选地大于5°、还更优选地大于25°、最优选地大于50°、尤其最优选地大于100°。
被涂覆到键合表面上的液体层具有小于2 mm、优选地小于1.5 mm、还更优选地小于1 mm、最优选地小于0.5 mm、尤其最优选地小于0.1 mm的厚度。液体优选地是水。但是,也可设想的是使用任何其它液体,如
· 醇
· 醚
· 酸
· 碱。
尤其是醚具有很高的蒸汽压力并且因此几乎没有剩余地从表面蒸发掉,这自动导致在实现自对准之后对液体的除去。有利地,在除去液体之后在表面之间自动形成预键合。
在根据本发明的一个特殊的实施方式中,在衬底和/或芯片的键合表面上、尤其是在介电区有凹槽,所述凹槽使得在芯片的自对准之后对液体的除去变得容易或者首先能够实现在芯片的自对准之后对液体的除去。这些凹槽优选地从芯片表面的区域引导到芯片的边缘,使得液体可通过流动和/或蒸发而向外被除去,优选地自动地、更优选地在导致将液体压出的重力的辅助下被除去。
键合装置和键合方法
公开了多个根据本发明的用于键合芯片的装置和工艺。根据本发明的方法可划分成单独键合方法和集体键合方法。因此,相对应的装置是用于单独键合或用于集体键合的装置。所有根据本发明的方法和装置的共同之处是,芯片的键合表面必须直至键合过程无污染。在下文更详细地描述了用于实现该目标的根据本发明的工艺步骤和设备。
单独键合装置和单独键合方法
单独键合方法被理解为在现有技术中常见的用于将芯片单独地、也就是说相继地放置在其它芯片上(C2C)或放置在晶圆上(C2W)的过程。这种方法具有如下优点:可以使不同的大小和/或不同的功能的芯片键合。
在胶带上的分离
在根据本发明的示例性的第一方法中,衬底被固定在载体、尤其是胶带(英文:tape)上,而且那里被分离成芯片。在本披露的进一步进程中,将胶带用作示范性示例。然而,也可设想的是使用刚性载体。因此,在成功将衬底固定在胶带上之后才制成芯片。
在该方法的第一工艺步骤中,对载体、尤其是胶带的固定发生在固定框、尤其是切割框(英文:dicing frame)上。如果载体是刚性载体,则可以省去该工艺步骤,或可以将该刚性载体固定在衬底夹持器/载体夹持器上。
在可选的第二工艺步骤中,对衬底的键合表面进行清洁,从该衬底中形成芯片的稍后的键合表面。该清洁可以是已经提到的清洁方式之一。尤其是,该清洁通过等离子体和/或液体和/或气体来实现。附加地,等离子体处理优选地导致键合表面的等离子体活化。只有当键合表面已被先前的工艺弄脏,使得有污染一并被转移到胶带上或者存在稍后会阻止和/或妨碍直接键合的构造的污染时,该键合表面才必须被清洁。然而,对衬底的键合表面的清洁优选地总是在固定之前进行。
在根据本发明的第三工艺步骤中,以衬底的、尤其是被清洁的、优选地经等离子体活化的键合表面将该衬底固定在载体上。在此,根据本发明,胶带被构建为使得在将衬底从载体除去之后对键合表面的污染尽可能小。如果载体是刚性载体,则可能需要在固定衬底之前给载体表面配备保护层。就胶带来说,大多已经存在这种保护层。
此外,从接触键合表面的时间点开始,载体也用作对该键合表面的保护并且阻止了对该键合表面的污染。优选地,载体至少在衬底的中心绝大部分被涂层,使得在衬底的键合表面与载体之间存在着低黏着,而载体在衬底的外围区域一定可以具有黏着特性。黏着强度高的区域、即粘合力较高的区域将可能在衬底外围产生污染,只要不涉及键合表面的稍后从中制造芯片的区域,该污染优选地就可以被忽略。优选地,胶带被构建为使得黏着力由于将能量输入到胶带中(UV、热量)而降低,而且这样可以稍后更容易地将芯片取下。这种胶带在现有技术中公知。
然而,优选地,特别是将污染少的胶带用于根据本发明的工艺。
胶带优选地具有胶粘剂,所述胶粘剂不能渗入到键合表面中,尤其是不能渗入到贮液槽中,所述贮液槽是由于之前执行的等离子体活化而产生的。优选地,这一点通过如下方式来确保:胶粘剂具有很高的粘性,该很高的粘性阻止了渗入到纳米多孔表面中。还更优选地,胶粘剂的分子大得使得由于分子大而不可能渗入到孔中。这些孔尤其是小于10 nm、还更优选地小于5 nm、最优选地小于1 nm、还更优选地小于0.5 nm、尤其最优选地小于0.2nm。在WO2012100786A1中也公开了孔大小。最优选的是,胶粘剂是粘合在聚合物基质中的固体。优选地,通过胶粘剂的这种形态,在将胶带除去之后可以省去利用溶剂的清洁,并且这样可以防止溶剂嵌入在是由于在键合表面的表面上的等离子体活化而产生的贮液槽中。这造成经改善的键合结果,因为可以防止在键合之后溶剂的排出并且因此可以防止在键合分界面中的气泡形成。
在出版文献WO2012100786A1、WO2012136267A1、WO2012136268A1、WO2012136266A1和WO2014015899A1中公开了这种贮液槽的产生。
然而,在根据本发明的一个非常优选的实施方式中,载体被涂层为使得该载体可以将衬底整面地固定,在衬底上没有留下污染而且稍后产生的芯片可以轻易被除去。
在根据本发明的第四工艺步骤中,将衬底分离。该分离可以通过任何任意的方法来执行,只要该方法没有将键合表面弄脏。在本披露的进一步进程中,将更详细地探讨一些分离方法,借助于这些分离方法,确保了在分离期间对键合表面的根据本发明的保持清洁。
在根据本发明的第五工艺步骤中,通过机器、尤其是芯片键合器将经分离的芯片从载体除去。在根据本发明的一个特别优选的实施方式中,在除去芯片期间和/或在将芯片运输到其它位置、尤其是键合位置期间,继续、尤其是持续地对芯片的键合表面进行清洁。该清洁优选地利用等离子体来实现。在此,芯片或者经过其中发生该清洁的区域,或者在其中自动实现该清洁特性的空间内将芯片从载体取出。这样,例如可设想的是:在芯片键合器的等离子体室内将芯片从载体取出。更优选地,芯片在从载体取下之后被移动经过大气等离子体源。尤其使用氧等离子体,该氧等离子体优选地导致残留物的灰化。
在根据本发明的第六工艺步骤中,通过键合、尤其是直接键合或混合键合将所运输的、经分离的芯片的键合表面与第二键合表面键合。芯片相对于该芯片应该被键合到的第二键合表面的对准工艺、一般是相对顺利地被执行的对准工艺先于键合过程。在本披露的其它区域更详细地提及关于最优的键合的根据本发明的改善方案:该对准工艺优选地持续少于5秒、更优选地少于2秒、最优选地少于1秒。
用于分离的方法
根据本发明的实施方式的一个重要方面在于分别保持衬底或从中分离的芯片的键合表面清洁。为了确保键合表面的清洁度,分离工艺也必须引起尽可能微小的污染。尤其是,在分离衬底时不允许形成毛边。根据本发明,这可通过多个不同的工艺来确保。
在可能的第一工艺、即所谓的隐形切割(stealth dicing)中,聚焦的激光束使材料特性发生变化,使得芯片可容易分离。优点尤其在于省去了机械分离装置、如切断轮。在现有技术中公知隐形切割工艺的基本工作原理。
在可能的第二工艺中,通过使用等离子体来使芯片彼此分离。
在可能的第三工艺中,通过使用机械分离装置来使芯片彼此分离。这里,在根据本发明的一个非常优选的实施方案中,在对键合表面的可选的清洁和将衬底固定在载体上之前在键合侧产生缝隙。在从衬底的后侧的分离过程中,机械分离装置接着碰到所预制的缝隙。借此,通过使机械分离装置提前到达空的空间,这些缝隙防止了对各个芯片的键合表面的污染。
这些缝隙优选地也可用在之前提到的分离方法中,因为这些分离方法也可能导致在边缘上的弄脏和/或毛边。尤其是当断裂、尤其是在隐形切割时的断裂例如由于芯片的层构造而未连续地垂直地经过晶圆时。这些缝隙尤其是被提供用于至少避免毛边在键合表面上的构造。
这些缝隙也可能是掩模工艺的结果,该掩模工艺被应用于将材料沉积在表面上。在这种工艺中,在掩模位置处没有沉积材料。接着,掩模区形成这些缝隙。
集体键合装置和集体键合方法
在一定的情境下可能不利的是:通过单独键合方法来使芯片键合。尤其是当必须清洁芯片的键合表面以便获得高键合质量时,可能是有利的是:首先将所有芯片放置在载体上,使得稍后的键合表面指向上。在该预固定中,芯片的所有键合表面接着可以立即、尤其是在为此所设置的机器中被清洁和预处理。在另一工艺步骤中,接着立即将所有芯片键合到真正所要键合的衬底或真正所要键合的芯片上。
在这种集体键合的情况下主要所要满足的质量特征是由所有芯片的所有键合表面形成的键合平面的平面度。在理想情况下,所有芯片的键合表面都必须全部彼此重合。
临时载体
以下工艺描述了对具有多个芯片的临时载体的制造,所述多个芯片的键合表面彼此重合,以便执行集体键合过程。
在根据本发明的第一工艺步骤中,第一载体、尤其是载体衬底、最优选地是载体晶圆、还更优选地是胶带在切割框(英文:dicing frame)上涂层有保护层。尤其是在使用胶带时,可设想的是:保护层已经被涂覆到胶带上。在其它情况下,可利用常见的、公知的涂层方法、如旋涂、喷涂、层压等等来进行对载体的涂层。
替选地,也可设想的是:给芯片的表面配备保护层。这可以在从晶圆切出芯片之前已经实现。
在根据本发明的第二工艺步骤中,以很高的对准精度将多个芯片固定在第一载体上。尤其是借助于对准标记和光学系统来进行对准。在此,对准精度优于1 mm、优选地优于100 μm、还更优选地优于10 μm、最优选地优于1 μm、尤其最优选地优于100 nm。
通过芯片的稍后的键合表面来进行固定。芯片的键合表面应尽可能彼此重合。此外,保护层应尽可能薄,具有尽可能小的粘性并且具有尽可能高的弹性,以便防止芯片不一样深地渗入到层中且这里破坏了这些芯片的键合表面的重合。保护层的厚度优选地应尽可能小,以便尽可能地消除弹性特性。因此,第一载体作为无限坚硬的阻力来起作用,保护层仅仅作为键合表面与第一载体之间的分离器来起作用。
在此,胶带的弹性模量介于1 GPa与1000 GPa之间、优选地介于1 GPa与500 GPa之间、更优选地介于1 GPa与100 GPa之间、最优选地介于1 GPa与50 GPa之间、尤其最优选地介于1 GPa与20 GPa之间。例如,聚酰胺的弹性模量介于3 GPa与6 GPa之间。
在此,更坚硬的载体的弹性模量介于1 GPa与1000 GPa之间、优选地介于10 GPa与1000 GPa之间、更优选地介于25 GPa与1000 GPa之间、最优选地介于50 GPa与1000 GPa之间、尤其最优选地介于100 GPa与1000 GPa之间。例如,一些钢种的弹性模量在200 GPa左右。
在根据本发明的第三工艺步骤中,第二载体、尤其是载体衬底、最优选地是载体晶圆用胶粘剂来涂层。第二载体是临时载体。与来自根据本发明的第二工艺步骤的保护层相反,该胶粘剂应具有弹性和/或塑性的适配能力,以便补偿芯片的可能高度差,使得没有失去芯片的键合表面的重合。因此,该胶粘剂应具有尽可能小的粘性和持久的变形的可能性。
在室温下,胶粘剂的粘性介于10E6 mPa*s与1 mPa*s之间、优选地介于10E5 mPa*s与1 mPa*s之间、还更优选地介于10E4 mPa*s与1 mPa*s之间、最优选地介于10E3 mPa*s与1mPa*s之间。
在根据本发明的第四工艺步骤中,将芯片的与芯片的键合表面对置的后侧表面与临时载体连接。在此,第一载体侧上维持芯片的键合表面的重合,而后侧表面如果必要则使临时载体上的胶粘剂相对应地变形,尤其是由于优选地低的粘性而使临时载体上的胶粘剂相对应地变形。因此,在键合过程之后,芯片与临时载体之间的胶粘剂的厚度可因芯片而异。在根据本发明的一个扩展方案中,除去芯片之间的胶粘剂是可能的。第一载体与临时载体之间的对准优选地通过位于第一载体和临时载体上的对准标记来实现。也可设想的是:对准标记位于芯片的表面上并且这些对准标记与临时载体上的对准标记对准。在出版文献US6214692B1、WO2015082020A1、WO2014202106A1中详细描述了用于对准衬底的对准器(英文:aligner)。
在根据本发明的第五工艺步骤中,除去具有保护层的第一载体。因此,胶粘剂、临时载体与芯片之间的黏着作用尤其是高于保护层与芯片的键合表面之间的静摩擦。在根据本发明的一个特别优选的实施方式中,保护层被设计为使得芯片的键合表面的脱离无污染地、尤其是完全无污染地进行。如果第一载体是胶带,则可剥离该胶带,这使得除去变得容易。也可能需要借助于化学品和/或电磁辐射、尤其是UV光、可见光或红外光和/或热量化学地或者关于机械特性方面改变保护层,以便该保护层失去或至少降低其黏着特性。
在此,保护层与芯片之间的键合强度小于1 J/m2、优选地小于0.1 J/m2、还更优选地小于0.01 J/m2、最优选地小于0.001 J/m2、尤其最优选地小于0.0001 J/m2。
在可选的第六工艺步骤中,尤其是对芯片的裸露的键合表面同时进行清洁和/或等离子体活化。尤其是当从芯片的键合表面除去第一载体并非完全无污染地进行时,该措施是重要的。所有芯片的清洁尤其可以在这一次同时进行,这提高了根据本发明的方法的吞吐量。
接着,在根据本发明的第七工艺步骤中,所有被固定在临时载体上的芯片的键合过程同时在产品衬底、尤其是晶圆上进行。这也包含将临时载体上的芯片键合到已位于产品衬底上的芯片上的可能性。由此,提供了逐渐在产品衬底上构造芯片堆的可能性。临时载体与产品衬底之间的对准优选地通过位于载体和产品衬底上的对准标记来实现。也可设想的是:对准标记位于芯片的键合表面上并且这些对准标记与产品衬底上的对准标记对准。
在根据本发明的第八工艺步骤中,将临时载体从芯片除去。可能需要借助于化学品和/或电磁辐射、尤其是UV光、可见光或红外光和/或热量化学地或者关于机械特性、尤其是粘性方面改变胶粘剂,以便该胶粘剂失去其黏着特性。特别优选地,临时载体是对于来自EM光谱的特定的波长范围的光子来说透明的载体。优选地涉及玻璃载体。由此,根据本发明,可以使用如下胶粘剂,该胶粘剂可借助于激光从后侧被破坏,使得从临时载体的后侧出发对该临时载体的去键合可能性是可能的。
在根据本发明的第九工艺步骤中,通过所提到的清洁方法之一来清洁芯片的后侧表面的胶粘剂。在该工艺步骤之后,可将任意其它芯片堆在现有的芯片上,以便这样在产品衬底上构造芯片堆。
优选地,通过芯片的自对准能够实现或至少辅助根据第二工艺步骤的芯片在第一载体上的定位精度以及根据第七工艺步骤的芯片通过集体键合过程在临时载体上的定位。在此,定位精度优于1 mm、优选地优于100 μm、还更优选地优于10 μm、最优选地优于1 μm、尤其最优选地优于100 nm。只有当能够实现芯片相对于第一载体和/或相对于临时载体的横向移动时,才实现通过自对准的辅助。为此,第一载体上的保护层和/或临时载体上的胶粘剂必须拥有相应地小的剪切模数或甚至必须能够实现塑性变形,使得芯片可横向移动。
固定载体
替代使用刚刚提到的临时载体,可设想的是将芯片固定在固定载体上,该固定载体拥有相对应的固定元件。这些固定元件可以是
· 真空固定件
· 静电固定件
· 磁性固定件
· 凝胶包固定件
芯片可以直接以它们的后侧表面固定在固定载体上。不利的是:与所提到的临时载体相反,不存在借助其所有芯片的键合表面可统一在一个平面内的胶粘剂。所提到的凝胶包固定件的凝胶包的弹性至多能够实现类似效果。稍后所描述的顶出装置尤其也可用作固定载体。
顶出装置
在本披露的进一步进程中,描述了多个装置和方法,其中需要对芯片的拾取和固定。因此,所有公开的方法和装置都涉及已经分离的芯片及对所述芯片的运用,根据本发明,对所述芯片的运用总是应该实现为使得键合表面尽可能不再被污染。这些被称作顶出装置的实施方式主要具有如下任务:将多个已经分离的芯片固定,以便在这些芯片上执行清洁工艺并且将这些芯片的键合表面准备用于真正的键合过程。
具有凹陷设计的顶出装置
为了处理芯片的键合表面并且将该键合表面直接输送给键合工艺,根据本发明的第一顶出装置在于将芯片安置在载体中。该载体拥有芯片可定位和/或固定在其中的凹陷。
在一优选的实施方式中,凹陷的轮廓全等于芯片的轮廓。在根据本发明的另一变型方案中,凹陷的轮廓也可不同于芯片的轮廓。尤其是,凹陷大于芯片。由此,有助于清洁流体和/或等离子体进入到芯片一侧。在此,芯片的轮廓与凹陷的轮廓之间的距离小于5 mm、优选地小于1 mm、还更优选地小于0.5 mm、最优选地小于0.1 mm、尤其最优选地小于0.05mm。
在凹陷的底面上有通道(在下文也被称作套管)、尤其是孔,提升装置可以通过所述通道来提升芯片,以便使这些芯片对于夹具(在下文也被称作夹头)来说能接触到。在根据本发明的一个特别优选的实施方式中,芯片的高度正好对应于凹陷的深度。借此,待清洁的键合表面与载体表面重合。通过这种实施方式特别有助于机械清洁过程。因为芯片未从凹陷中伸出,所以这些芯片不能被机械损坏。此外,这些芯片没有沉没在凹陷中并且因此可由所有类型的清洁设备最优地到达。此外,根据本发明的实施方式最优地适合于对芯片的等离子体清洁,因为由于键合表面与载体表面之间产生的无缝的平整度,所使用的等离子体的均匀性很高。由于均匀性高,确保了键合表面的高再现性以及尤其是对键合表面的均匀的清洁、尤其是均匀的等离子体活化。
所有在本披露中规定的在等离子体室中使用的载体都应具有特定的特性。尤其是,这些载体必须由导电材料组成。因此,这些载体优选地由如下材料组成:
· 导电体(electrics),尤其是
○ 金属,尤其是
○ 合金,尤其是
- 钢
▪ 铝
▪ 不锈钢合金
▪ 钛
○ 导电陶瓷,尤其是
▪ 有掺杂的SiC
▪ 有掺杂的Si3N4
金属载体优选地被涂层,以便防止金属对芯片的污染。优选地,考虑介电体、尤其是氧化物、氮化物或碳化物作为涂层。
载体优选地也由两部分组成地来实施,使得芯片座落在金属片上,并且接着为了进行等离子体活化而铺上网筛,该网筛由介电体、尤其是Si、SiC或Si3N4组成。在这种情况下,网筛具有与芯片类似或相同的介电特性。因此,可以确保尽可能均匀的等离子体。尤其是,该网筛甚至由与芯片相同的介电材料组成。
芯片高度h与凹陷的深度t之差的绝对值小于1 mm、优选地小于0.5 mm、还更优选地小于0.1 mm、最优选地小于0.05 mm、尤其最优选地小于0.01 mm。
通过根据本发明的实施方式,可以同时处理多个芯片的键合表面,这导致了对已经分离的芯片的清洁的极大的效率提高。
在将芯片顶出到明确规定的高度之后,使用夹头来拾取和运输该芯片。在此,夹头不是在刚刚被清洁的键合表面上固定芯片,而是在与该键合表面对置的固定表面上固定芯片。固定表面尤其可能在这些工艺步骤中被污染。然而,在其它工艺步骤中,该固定表面可能变成其它芯片可被放置在其上的新的键合表面,而且必须接着相对应地被清洁。
在所描述的顶出装置的情况下,预先给定凹陷的深度t。如果根据本发明来固定芯片高度h稍微不同的芯片,则这些芯片的待清洁的键合表面不再彼此重合。在这种情况下可设想的是:提升装置执行对一些芯片、尤其是其芯片高度h小于凹陷的深度t的芯片的高度校正。
具有附件设计的顶出装置
根据本发明的另一第二顶出装置由载体组成,在该载体中有通道、尤其是孔。与先前的第一顶出器设计相反,该顶出装置没有凹陷。待清洁的芯片直接被固定在载体表面上。周围大气尤其是借助于密封件来与通道分离。借此可能的是:执行对芯片的清洁,而不执行由于清洁剂、例如化学品、如液体或者来自等离子体的离子所引起的对通道的污染。将芯片固定的固定元件可位于密封空间之内。这些固定元件是如下固定件中的至少一个固定件:
· 真空固定件(优选)
· 静电固定件
· 磁性固定件
· 黏着固定件,
· 机械固定件(最不优选)
最优选地,使用真空固定件,所述真空固定件可将通道以及密封件之间的空间抽真空,而且这样引起将芯片压紧到密封件上。这些密封件或者可以是固体、尤其是聚合物,或者可以是尤其是高粘性的和/或时效硬化的聚合物。那么,这些密封件优选地是蜡、胶粘剂、胶水等等。这些聚合物需要定期更换,因为它们随着时间、尤其是由于所执行的清洁工艺而被除去。
掩模
在根据本发明的一个尤其是针对所提到的顶出装置的扩展方案中,使用具有孔隙的掩模,以便保护芯片的键合表面免受污染。总是通过机器构件来抓取芯片,这些机器构件一定必须移动得越过这些芯片。除了真正的夹头和该夹头处在其一端上的相对应的臂之外,也必须使电缆和导线一并移动。当全部这些机器元件都移动得越过这些芯片时,全部这些机器元件必然促成了对芯片的键合表面的污染。
在根据本发明的一个特别优选的实施方式中,实现在具有孔隙的掩模与芯片之间的相对移动。优选地,芯片位于其上的装置移动。也可设想的是掩模移动。为了取出芯片,将孔隙定位在待取出的芯片上方。提升装置将待键合的芯片提升得越过掩模。在掩模的上侧,夹头通过芯片的后侧表面将该芯片取出,而不触碰该芯片的键合表面,而且将该芯片运输到对其进行进一步处理的位置。尤其是,利用第一光学系统来检测芯片的对准标记,作为下一步骤。然后,该芯片被移动到待键合的位置下方,并且然后尤其是借助于第二光学系统相对于待键合的位置高度精确地被定位和键合。因此,根据本发明可能的是:芯片被键合的位置远在芯片取出之外。芯片还可经过多个阶段,尤其是对准和/或测量和/或清洁和/或测试阶段等等,直至真正的键合过程。根据本发明,在整个芯片运输期间,只仅触碰芯片的后侧表面,而从不触碰该芯片的键合表面。因此,夹头优选地自从提升装置取出的时间点开始直至键合结束都将该芯片固定。
在一个特殊的实施方式中,芯片应该在其上键合的产品衬底直接位于待键合的芯片上方。所有其它芯片以及借此这些芯片的键合表面又通过掩模表面来保护免受污染。顶出器将芯片从顶出装置卸下并且将该芯片直接键合到产品衬底上或直接键合到产品衬底的芯片/芯片堆上。在此,产品衬底或该产品衬底的芯片的键合表面直接朝向顶出器,因此指向重力方向。通过掩模,防止了对在顶出装置上的还要顶出的芯片的键合表面的污染。与上面提到的其中夹头将芯片运输到其它位置并且在那里使芯片键合的实施方式相比,根据本发明的该实施方式不那么优选,因为在该变型方案中在该芯片上不能执行其它工艺步骤。
对于所有实施方式来说,掩模本身在此必须本身无污染。尤其是,该掩模可在组装工艺之间利用所提到的清洁方法之一来清洁。根据本发明的掩模主要用于键合过程,其中待装备芯片的衬底以该衬底的键合表面沿重力方向被放置。在此,根据本发明的掩模防止了将衬底的污染转移到位于衬底下方的芯片上或者将正在移动的机器元件的污染转移到位于衬底下方的芯片上。这些掩模尤其是与在本披露中详细描述的顶出装置一起使用。在这些实施方式中,尤其可以省去对芯片的旋转并且借此可以省去在这些芯片的键合表面上对这些芯片的接触。确切的实施方式在本披露的其它位置以及在附图和所属的附图说明中详细地予以阐述。
此外,在清洁室中存在着自上而下(Top-Down)流动。因此,空气总是从较高的位置循环到较低的位置并且在此吸引尘粒。流动方向同样对键合表面的污染有不利的影响。根据本发明,根据本发明可设想的是:在其中多个芯片以暴露的键合表面被固定的装置附近、尤其是在所提到的顶出装置或固定载体中设置如下机器,这些机器产生侧面流动,以便将尘粒横向地排出。
键合头
在根据本发明的另一实施方式中,描述了一种用于固定并且键合芯片的固定装置。该固定装置也被称作键合头(英文:bond head)并且描述了如下机器构件,该机器构件负责对单个芯片的固定、运输和键合到键合表面上。为了能够充分利用芯片上的干净的键合表面的根据本发明的优点,需要尽可能多地控制键合过程。尤其是,绝对必要的是:芯片不是首先在边缘键合,而是键合波从芯片的中心向外传播。键合波的概念对于本领域技术人员来说已经从晶圆到晶圆(英文:W2W)键合中公知。这里,参阅出版文献WO2014191033A1、PCT/EP2016053268、PCT/EP2016056249和PCT/EP2016069307,用来仅举几例。
然而,与所提到的W2W方法相反,C2W方法具有极高的吞吐量。固定装置以极高的速度从芯片的拾取位置移动到键合位置并返回。由于要迅速达到高速度,加速度也相对高。尤其是,沿z方向的、也就是说垂直于键合表面的加速度也很高。可将该所希望的物理事实用于构建一种全新的固定装置,借助于该固定装置能够仅基于惯性就使芯片凸地变形,以便借此保证芯片的键合表面的中心首先接触第二键合表面。
根据本发明的思想在于:该固定装置在外围具有如下弹簧元件,这些弹簧元件的弹簧常数小于位于中心的弹簧元件的弹簧常数。在根据本发明的一个非常特殊的实施方式中,固定表面在外围完全不受支撑,也就是说在外围省去了弹簧元件。
在此,外围的弹簧元件的弹簧常数与位于中心的弹簧元件的弹簧常数之比小于1、优选地小于0.1、还更优选地小于0.01、最优选地小于0.0001、尤其最优选地小于0.00001。
附图说明
本发明的其它优点、特征和细节根据随后对优选的实施例的描述以及依据附图来得到。其中:
图1a示出了根据本发明的第一工艺的根据本发明的第一工艺步骤,
图1b示出了根据本发明的第一工艺的根据本发明的第二工艺步骤,
图1c示出了根据本发明的第一工艺的根据本发明的第三工艺步骤,
图1d示出了根据本发明的第一工艺的根据本发明的第四工艺步骤,
图1e示出了根据本发明的第一工艺的根据本发明的第五工艺步骤,
图1f示出了根据本发明的第一工艺的根据本发明的第六工艺步骤,
图1g示出了根据本发明的第一工艺的根据本发明的第七工艺步骤,
图2a示出了根据本发明的第二工艺的根据本发明的第一工艺步骤,
图2b示出了根据本发明的第二工艺的根据本发明的第二工艺步骤,
图2c示出了根据本发明的第二工艺的根据本发明的第三工艺步骤,
图2d示出了根据本发明的第二工艺的根据本发明的第四工艺步骤,
图2e示出了根据本发明的第二工艺的根据本发明的第五工艺步骤,
图2f示出了根据本发明的第二工艺的根据本发明的第六工艺步骤,
图2g示出了根据本发明的第二工艺的根据本发明的第七工艺步骤,
图2h示出了根据本发明的第二工艺的根据本发明的第八工艺步骤,
图2i示出了根据本发明的第二工艺的根据本发明的第九工艺步骤,
图3示出了根据本发明的第一顶出装置,
图4示出了根据本发明的第二顶出装置,
图5示出了在根据本发明的第一实施方式中的根据本发明的具有孔隙的掩模,
图6示出了在根据本发明的第二实施方式中的根据本发明的具有孔隙的掩模,
图7a示出了根据本发明的自对准的第一工艺步骤,
图7b示出了根据本发明的自对准的第二工艺步骤,
图8a示出了利用根据本发明的键合头的键合过程的根据本发明的第一工艺步骤,
图8b示出了利用根据本发明的键合头的键合过程的根据本发明的第二工艺步骤。
在这些附图中,相同的构件或者功能相同的构件用相同的附图标记来表征。
具体实施方式
图1a示出了根据本发明的第一工艺的根据本发明的第一工艺步骤,用于在根据本发明的第一工艺之后产生最终产品19。在衬底11上执行用于制造多个芯片的所有准备。属于这些准备的是制造芯片的所有功能特性、尤其是接触部13。此外,可预切出缝隙12,以便有助于稍后的分离工艺。由于执行所有准备步骤,键合表面7b可能已被污染。
图1b示出了根据本发明的第一工艺的第二工艺步骤、即对键合表面7b的清洁步骤。尤其是通过等离子体和/或湿化学方法来对键合表面7b进行清洁和/或活化。
图1c示出了根据本发明的第一工艺的第三工艺步骤,其中将衬底11固定在载体、尤其是胶带15上。胶带表面15o优选地被构建为使得通过键合表面7b来固定衬底11,但是稍后对胶带15的除去使在键合表面7b上没有留下残留物。
图1d示出了根据本发明的第一工艺的第四工艺步骤,其中将衬底11分成各个芯片7。根据本发明,芯片7的键合表面7b在此不允许被污染。因此,优选地,尤其是在通过分离装置16来进行机械分离时,在衬底11中设置缝隙12,以便已经可以在键合表面7b上方结束分离工艺。也可设想的是:通过激光、尤其是通过已知的隐形技术、通过化学品、尤其是通过蚀刻、优选地通过干法蚀刻、通过等离子体等等来进行分离。
图1e示出了根据本发明的第一工艺的第五工艺步骤,其中通过固定件6位于其上的键合头9将芯片7从胶带15除去。在此,键合头9将芯片7固定在该芯片的后侧表面7r上,使得在键合表面7b上没有污染。
图1f示出了根据本发明的第一工艺的第六工艺步骤,其中键合头9在已使芯片7相对于另一衬底11'对准之后键合到该另一衬底11'上。在此,键合表面7b优选地是混合表面,该混合表面由介电表面区20和通过接触部13来表示的电表面区组成。在这种混合键合表面的情况下,在芯片7的键合表面7b的介电表面区20与衬底11'的介电表面区20'之间进行所谓的预键合。
图1g示出了根据本发明的第一工艺的根据本发明的最终产品19,该最终产品由衬底11'和多个芯片7组成。可设想的是:重复所提到的工艺步骤,以便将芯片7的其它层堆到芯片7的第一层上。
图2a示出了根据本发明的第二工艺的根据本发明的第一工艺步骤,其中将多个已经分离的芯片7以键合表面7b固定在载体、尤其是胶带15上。芯片7的键合表面7b必须已在先前的工艺中被清洁和/或活化。优选地,芯片7通过芯片键合器的键合头9来对准和定位。放大图示出了芯片7的键合表面7b与胶带15的胶带表面15o之间的分界面。在胶带表面15o上可以有保护层17,该保护层优选地也具有黏着特性。然而,特别优选地,保护层17与胶带表面15o之间的黏着特性大于保护层17与键合表面7b之间的黏着特性,使得在稍后的工艺步骤中将胶带15除去时保留尽可能无污染的键合表面7b。
图2b示出了根据本发明的第二工艺的根据本发明的第二工艺步骤,其中制备衬底11"作为临时载体。通过已知的方法、尤其是通过旋涂工艺来将胶粘剂18涂覆到衬底11"上。
图2c示出了根据本发明的第二工艺的根据本发明的第三工艺步骤,其中芯片7的后侧表面7r与键合胶粘剂进行接触。在该接触之前,尤其是使所有相对于彼此固定的芯片7相对于衬底11'对准。在该工艺步骤中也可设想的是:从胶带后侧15r进行机械压力加载,该机械压力加载应该引起所有芯片7的键合表面7b在一个平面E内的重合。在此,平面E是芯片7的所有键合表面7b都应位于其中的平面。平面E尤其应该与保护层17的沿芯片7的方向的表面相同。这尤其是在载体15是胶带时是重要的。例如可设想的是:滚筒滚动经过胶带后侧15r。然而,优选地进行整面的加载,该整面的加载导致均匀的压力分布。
图2d示出了根据本发明的第二工艺的根据本发明的第四工艺步骤,其中已将胶带15从芯片7的键合表面7b除去。优选地将胶带15剥离。依据放大图Z1看出:在将胶带15除去之后,保护层17的剩余可能留在键合表面7b上。在这种不那么优选的情况下,必须在另一工艺步骤中重新对芯片进行清洁。优选地,在将胶带15除去之后,键合表面7b无污染。放大图Z2示出了两个并排的芯片的夸张的图示,这两个并排的芯片在其厚度d1和d2方面有区别。然而,胶粘剂18的弹性引起:键合表面7b位于同一平面E内,这是该工艺的根据本发明的一个重要方面。
图2e示出了根据本发明的第二工艺的根据本发明可选的、不那么优选的第五工艺步骤,其中已通过清洁方法来清洁芯片7的键合表面7b。放大图Z1不再能看出保护层17。
图2f示出了根据本发明的第二工艺的根据本发明的第六工艺步骤,其中装备有芯片7的临时载体11"相对于另一衬底11'对准并且进行键合。根据本发明,对所有芯片7的键合同时进行。
图2g示出了根据本发明的第二工艺的根据本发明的第七工艺步骤,其中对胶粘剂18进行处理。该处理可以化学地和/或热地和/或借助于EM波、尤其是借助于UV光或红外线来进行。在根据本发明的一个特别优选的实施方式中,该处理通过临时载体11"来进行。该处理优选地导致:胶粘剂18的黏着特性减小或者甚至完全消除,使得临时载体11"可从芯片7脱离。
图2h示出了根据本发明的第二工艺的根据本发明的第八工艺步骤,其中将载体衬底11"除去。
图2i示出了根据本发明的第二工艺的根据本发明的第九工艺步骤,其中对芯片7的后侧表面7r进行清洁。结果又一次是最终产品19。
图3示出了用于芯片7的批量清洁和/或等离子体活化和/或键合的根据本发明的第一实施方式。芯片7位于拥有凹陷2的顶出装置1中。在凹陷2的底部安装有套管3 、尤其是简单的孔,提升装置4可使芯片7穿过所述套管上升和下降。芯片7的装载和/或卸下可通过夹头5来实现,该夹头可借助于固定件6使芯片7仅固定在其后侧表面7r上,以便运输该芯片。优选地,所有芯片7的所有键合表面7b在批量清洁和/或等离子体活化期间都在平面E之内重合。所有键合表面7b的重合具有均匀的处理的优点。由此,尤其是在等离子体处理的情况下保证了:等离子体密度在整个表面内均匀。如果芯片7应该会在其厚度方面稍微不同,则提升装置可进行轻微的校正,以便再次确保键合表面7b的重合。
图4示出了用于芯片7的批量清洁和/或等离子体活化和/或键合的根据本发明的第二实施方式。
芯片7位于拥有密封件8的顶出装置1'中。芯片7可利用提升装置4来装载和/或卸除,该提升装置可平移移动经过套管3。优选地通过固定件6、尤其是通过真空通道来进行固定,所述固定件在芯片7与密封件8接触时允许在中间空隙中产生真空。为了清楚起见,在该图中未曾绘出夹头5。
因此,顶出装置1、1'用于经分离的芯片7的一般的批量清洁和/或等离子体活化和/或键合。还可设想的是:顶出装置1、1'本身紧凑地来构建,使得它们可以被用作就根据本发明的第二工艺而言的载体晶圆11"。在这种情况下,至少在与衬底11的键合工艺之前,芯片7的键合表面7b必须稍微伸出超过顶出器表面1o、1o',这对于顶出器1'的顶出器表面1o'来说在结构技术上自动被满足。借此,顶出装置1'尤其适合作为一种固定载体。那么,固定件6也可以是静电固定件、磁性固定件或凝胶包固定件。
图5示出了键合的根据本发明的实施方式的第一扩展方案,其中示范性地,可以使用顶出装置1,以便可以由夹头5经过掩模23的孔隙24来拾取芯片7。所拾取的芯片7被运输,尤其是被运输越过多个阶段。在此,光学系统25可测量芯片7和/或衬底11'的键合表面7b和/或后侧表面7r。尤其可以寻找在芯片7和/或衬底11'上的对准标记(未绘出),以便使所运输的芯片7正确地定位。因此,在该扩展方案中,待装备的衬底11'不是直接位于芯片上方。
图6示出了键合的根据本发明的实施方式的第二扩展方案,其中示范性地,可以使用顶出装置1',以便使芯片7经过掩模23的孔隙24与载体11'的芯片7键合。根据本发明的思想在于:尤其是由优选地没有表面污染的高纯度材料组成的掩模23保护在示范性地使用的顶出装置1'上的芯片7免受污染。借此,根据本发明,再次示出了:可如何保护芯片7的键合表面7b免受污染。当然,替代示范性地使用的顶出装置1',可使用任何其它类型的装置,以便引导芯片7经过孔隙24并且将该芯片与另一芯片7或衬底11'的位于掩模23的另一侧的表面进行键合。
图7a示出了在衬底1'上的芯片7的根据本发明的自对准的根据本发明的第一工艺步骤。芯片7通过键合头9被放在液膜21上。在一个特殊的实施方式中,液膜21不是连续地分布在整个衬底1'内,而是仅作为液滴或液坑存在于应该进行芯片7的自对准的位置。
能看出芯片7的接触部13与衬底1'的接触部13的并非最优的对准。
图7b示出了在衬底1'上的芯片7的根据本发明的自对准的根据本发明的第二工艺步骤。键合头9松开对芯片7的固定。现在,该芯片通过该芯片的由于存在液膜21而引起的横向可移动性来对准,使得芯片7的接触部13与衬底1'的接触部13尽可能全等。其原因在于介电区与电区的不同的键合特性。亲水的那些区优选地吸引亲水区。优选地,该相互作用可通过具有至少部分的极性的介质来扩散。水是偶极子并且因此根据本发明特别好地适于该任务。
图8a示出了根据本发明的键合头9,该键合头由具有固定件6的固定表面22组成。具有不同的弹簧常数的弹簧元件10、10'处在固定表面22后面。建造在中心的弹簧元件10的弹簧常数优选地大于建造在外围的弹簧元件10'的弹簧常数。键合头9沿横向方向的加速对固定表面22的形状没有影响。
图8b示出了在沿待键合的表面的法线方向加速时的根据本发明的键合头9。由于中间的弹簧元件10的弹簧常数更高,惯性对固定表面22的中间部分的作用不那么强烈,或者换言之,固定表面22的中间部分跟随外围部分并且比外围部分更快地做出反应。有利地,也通过快速接近接触面和存在的气垫来实现弯曲。在弹簧元件相同的情况下,对固定表面22的通过平移移动所产生的动态压力会将该固定表面对称地向后压。然而,由于外围的弹簧元件10'与中间的弹簧元件10相比具有更小的弹簧常数,这些外围的弹簧元件更容易屈服,因为它们更有弹性。因此,除了惯性之外,所形成的动态压力也造成弯曲。由于该机械不对称性,固定表面22以及借此被固定在该固定表面上的芯片7凸地弯曲而且可以产生对于直接键合来说最优的接触点23。借此排除了芯片7首先侧面地或平坦地接触。
附图标记列表
1、1' 顶出装置
1o、1o' 顶出器表面
2 凹陷
3 套管
4 提升装置
5 夹头
6 固定件
7 芯片
7b 键合表面
7r 后侧表面
8 密封件
9 键合头
10、10' 弹簧元件
11、11'、11" 衬底
12 缝隙
13 接触部
14 框
15 胶带
15o 胶带表面
15r 胶带后侧
16 分离装置
17 保护层
18 胶粘剂
19 最终产品
20 介电表面
21 液体
22 固定表面
23 掩模
24 孔隙
25 光学系统
d1、d2 厚度
E 重合平面
t 深度
Z1、Z2 放大图
Claims (16)
1.一种用于将芯片(7)键合到半导体衬底(11')上或键合到其它芯片上的方法,
其特征在于,
所述芯片(7)通过直接键合来被键合到所述半导体衬底(11')或者所述其它芯片上。
2.根据权利要求1所述的方法,其特征在于,在所述芯片(7)的键合表面(7b)上进行所述直接键合,其中所述键合表面(7b)是混合键合表面。
3.根据上述权利要求中任一项所述的方法,其特征在于,所述芯片(7)被定位而且进行所述芯片(7)的自对准。
4.根据上述权利要求中任一项所述的方法,其特征在于,为了制造所述芯片(7),将衬底(11)固定在载体(15)上,尤其是固定在胶带上,并且然后将所述衬底(11)分离成所述芯片(7)。
5.根据权利要求4所述的方法,其特征在于,在将所述衬底(11)固定在所述载体(15)上之前,对所述衬底(11)的键合表面(7b)进行清洁。
6.根据权利要求4或5所述的方法,其特征在于,在从所述载体(15)除去期间和/或在运输到其它位置、尤其是键合位置期间,对所述芯片(7)的键合表面(7b)进行清洁,尤其是持续地进行清洁。
7.根据权利要求4、5或6所述的方法,其特征在于,所述芯片(7)通过机械分离装置来分离,其中事先已将缝隙(12)引入到所述衬底(11)的键合表面(7b)中。
8.一种用于将芯片(7)键合到半导体衬底(11')或其它芯片上的装置,
其特征在于,
所述芯片(7)能通过直接键合来被键合到所述半导体衬底(11')或者所述其它芯片上。
9.根据权利要求8所述的装置,所述装置具有顶出装置(1),所述顶出装置具有用于对所述芯片(7)进行定位和/或固定的凹陷(2)。
10.根据权利要求8或9所述的装置,其中套管(3)、尤其是孔位于所述凹陷(2)的底面上,其中提升装置(4)能提升所述芯片(7)经过所述套管(3),以便使所述芯片(7)对于夹具(5)来说能接触到。
11.根据权利要求8、9或10所述的装置,其中所述凹陷(2)的深度(t)对应于所述芯片(7)的高度。
12.根据权利要求8、9、10或11所述的装置,其中所述夹具(5)将所述芯片(7)固定在与所述键合表面(7b)对置的固定表面上。
13.根据权利要求8、9、10、11或12所述的装置,所述装置具有掩模(23),所述掩模具有孔隙(24),其中所述掩模(23)能一直在装载有所述芯片(7)的顶出装置(1、1')上方移动,直至所述孔隙(24)位于下一个待键合的芯片(7)上方。
14.根据权利要求8、9、10、11、12或13所述的装置,所述装置具有键合头(9),用于对所述芯片(7)进行固定、运输和键合。
15.一种由芯片构成的芯片堆,其特征在于,所述芯片通过直接键合来彼此键合。
16.一种具有芯片的半导体衬底(11'),其特征在于,所述芯片通过直接键合来被键合到所述半导体衬底(11')上。
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JP7453299B2 (ja) | 2024-03-19 |
US20200176437A1 (en) | 2020-06-04 |
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US11990463B2 (en) | 2024-05-21 |
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TW202401595A (zh) | 2024-01-01 |
KR20240010753A (ko) | 2024-01-24 |
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TWI797492B (zh) | 2023-04-01 |
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JP2024060010A (ja) | 2024-05-01 |
JP2020509578A (ja) | 2020-03-26 |
JP7137571B2 (ja) | 2022-09-14 |
TW202121610A (zh) | 2021-06-01 |
EP3590130A1 (de) | 2020-01-08 |
US20240170474A1 (en) | 2024-05-23 |
KR20190119031A (ko) | 2019-10-21 |
US20210134782A1 (en) | 2021-05-06 |
SG11201906510PA (en) | 2019-08-27 |
US11764198B2 (en) | 2023-09-19 |
TW201842630A (zh) | 2018-12-01 |
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