KR20090089268A - 배선 기판, 이의 제조 방법 및 반도체 패키지 - Google Patents

배선 기판, 이의 제조 방법 및 반도체 패키지 Download PDF

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Publication number
KR20090089268A
KR20090089268A KR1020090013084A KR20090013084A KR20090089268A KR 20090089268 A KR20090089268 A KR 20090089268A KR 1020090013084 A KR1020090013084 A KR 1020090013084A KR 20090013084 A KR20090013084 A KR 20090013084A KR 20090089268 A KR20090089268 A KR 20090089268A
Authority
KR
South Korea
Prior art keywords
layer
wiring board
wiring
integrated
management information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1020090013084A
Other languages
English (en)
Korean (ko)
Inventor
카즈타카 코바야시
Original Assignee
신코 덴키 코교 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 신코 덴키 코교 가부시키가이샤 filed Critical 신코 덴키 코교 가부시키가이샤
Publication of KR20090089268A publication Critical patent/KR20090089268A/ko
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/114—Pad being close to via, but not surrounding the via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09609—Via grid, i.e. two-dimensional array of vias or holes in a single plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09936—Marks, inscriptions, etc. for information
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing of the conductive pattern
    • H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
KR1020090013084A 2008-02-18 2009-02-17 배선 기판, 이의 제조 방법 및 반도체 패키지 Ceased KR20090089268A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008036234A JP2009194321A (ja) 2008-02-18 2008-02-18 配線基板及びその製造方法、半導体パッケージ
JPJP-P-2008-036234 2008-02-18

Publications (1)

Publication Number Publication Date
KR20090089268A true KR20090089268A (ko) 2009-08-21

Family

ID=40954067

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020090013084A Ceased KR20090089268A (ko) 2008-02-18 2009-02-17 배선 기판, 이의 제조 방법 및 반도체 패키지

Country Status (3)

Country Link
US (1) US8035033B2 (https=)
JP (1) JP2009194321A (https=)
KR (1) KR20090089268A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20240103618A (ko) * 2022-12-27 2024-07-04 트릴리온 하비스트 리미티드 기판의 솔더 마스크 레이저 제거 제조방법

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100924559B1 (ko) * 2008-03-07 2009-11-02 주식회사 하이닉스반도체 반도체 패키지의 제조 방법
US8436252B2 (en) * 2009-06-30 2013-05-07 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
JP5603600B2 (ja) * 2010-01-13 2014-10-08 新光電気工業株式会社 配線基板及びその製造方法、並びに半導体パッケージ
JP5830347B2 (ja) * 2011-10-25 2015-12-09 日本特殊陶業株式会社 配線基板の製造方法
JP2012151509A (ja) * 2012-05-01 2012-08-09 Shinko Electric Ind Co Ltd 配線基板及びその製造方法、半導体パッケージ
JP2015005141A (ja) * 2013-06-20 2015-01-08 株式会社東芝 半導体記憶装置及び製造方法
KR102375653B1 (ko) * 2014-02-12 2022-03-16 쇼와덴코머티리얼즈가부시끼가이샤 감광성 엘리먼트
JP6208054B2 (ja) 2014-03-10 2017-10-04 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
JP6534602B2 (ja) * 2015-11-17 2019-06-26 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
JP2017162895A (ja) * 2016-03-08 2017-09-14 株式会社ジェイデバイス 配線構造、プリント基板、半導体装置及び配線構造の製造方法
BE1023850B1 (nl) * 2016-06-29 2017-08-14 C-Mac Electromag Bvba Verbeterde elektronische schakeling en substraat met identificatiepatroon voor afzonderlijke elektronische schakelingen en werkwijze voor het produceren daarvan
US10665523B2 (en) * 2018-07-17 2020-05-26 Advance Semiconductor Engineering, Inc. Semiconductor substrate, semiconductor package, and method for forming the same
DE102019110191A1 (de) * 2019-04-17 2020-10-22 Infineon Technologies Ag Package aufweisend einen Identifizierer auf und/oder in einem Träger
JP2022096004A (ja) * 2019-04-26 2022-06-29 株式会社アクセス プリント配線基板の製造方法及びプリント配線基板
TW202220064A (zh) * 2020-09-24 2022-05-16 日商索尼互動娛樂股份有限公司 半導體封裝、電子機器及電子機器的製造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10326951A (ja) * 1997-05-23 1998-12-08 Ngk Spark Plug Co Ltd 配線基板
JP3731360B2 (ja) * 1998-12-22 2006-01-05 松下電工株式会社 多層プリント配線板の製造方法
JP4451534B2 (ja) * 2000-03-13 2010-04-14 イビデン株式会社 積層配線板およびその製造方法
KR100509058B1 (ko) * 2000-04-11 2005-08-18 엘지전자 주식회사 인쇄회로기판의 제조방법
JP2003086735A (ja) 2001-06-27 2003-03-20 Shinko Electric Ind Co Ltd 位置情報付配線基板及びその製造方法並びに半導体装置の製造方法
JP2003051650A (ja) * 2001-08-06 2003-02-21 Ibiden Co Ltd プリント配線板、多層プリント配線板およびその製造方法
JP2005129663A (ja) * 2003-10-22 2005-05-19 Internatl Business Mach Corp <Ibm> 多層配線基板
TWI233323B (en) * 2004-04-22 2005-05-21 Phoenix Prec Technology Corp Circuit board with identifiable information and method for fabricating the same
JP4619223B2 (ja) * 2004-12-16 2011-01-26 新光電気工業株式会社 半導体パッケージ及びその製造方法
TW200906260A (en) * 2007-07-20 2009-02-01 Siliconware Precision Industries Co Ltd Circuit board structure and fabrication method thereof
TWI393233B (zh) * 2009-08-18 2013-04-11 欣興電子股份有限公司 無核心層封裝基板及其製法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20240103618A (ko) * 2022-12-27 2024-07-04 트릴리온 하비스트 리미티드 기판의 솔더 마스크 레이저 제거 제조방법

Also Published As

Publication number Publication date
US8035033B2 (en) 2011-10-11
US20090205860A1 (en) 2009-08-20
JP2009194321A (ja) 2009-08-27

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