KR20040035782A - 에칭 방법 및 에칭 보호층 형성용 조성물 - Google Patents
에칭 방법 및 에칭 보호층 형성용 조성물 Download PDFInfo
- Publication number
- KR20040035782A KR20040035782A KR10-2004-7003748A KR20047003748A KR20040035782A KR 20040035782 A KR20040035782 A KR 20040035782A KR 20047003748 A KR20047003748 A KR 20047003748A KR 20040035782 A KR20040035782 A KR 20040035782A
- Authority
- KR
- South Korea
- Prior art keywords
- etching
- water
- soluble
- protective layer
- composition
- Prior art date
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Classifications
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/40—Treatment after imagewise removal, e.g. baking
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Materials For Photolithography (AREA)
- Drying Of Semiconductors (AREA)
- Paints Or Removers (AREA)
- Polyurethanes Or Polyureas (AREA)
- Polymers With Sulfur, Phosphorus Or Metals In The Main Chain (AREA)
Abstract
Description
내식막 종류 | 내식막 두께 초기값(㎛) | 미노광부(패턴 외) 막두께 | 막 감소량*(㎛) | 산화막의 에칭 전의 형상** | ||
에칭 전(㎛) | 에칭 후(㎛) | |||||
실시예 1 | i선 내식막 | 1.00 | 1.06 | 0.59 | 0.41 | ◎ |
실시예 2 | KrF 내식막 | 0.70 | 0.78 | 0.28 | 0.42 | ◎ |
실시예 3 | i선 내식막 | 1.00 | 1.08 | 0.66 | 0.34 | ◎ |
실시예 4 | KrF 내식막 | 0.70 | 0.76 | 0.35 | 0.35 | ◎ |
실시예 5 | i선 내식막 | 1.00 | 1.07 | 0.65 | 0.35 | ◎ |
실시예 6 | KrF 내식막 | 0.70 | 0.75 | 0.34 | 0.36 | ◎ |
비교예 1 | i선 내식막 | 1.00 | 1.00 | 0.52 | 0.48 | O |
비교예 2 | KrF 내식막 | 0.70 | 0.70 | 0.14 | 0.56 | O |
Claims (10)
- 기판 위에 광내식막을 사용하여 내식막 패턴을 형성하는 공정, 형성된 내식막 패턴 위에 에칭 보호층 형성용 조성물을 도포하는 공정, 물을 함유하는 현상액에 불용성인 에칭 보호층을 에칭 보호층 형성용 조성물과 내식막과의 계면에 형성하는 공정, 에칭 보호층 형성용 조성물의 에칭 보호층 이외의 불필요한 부분을 물을 함유하는 현상액으로 제거하는 공정 및 에칭 보호층을 갖는 내식막 패턴을 마스크로 하여 기판의 에칭 처리를 실시하는 공정을 구비함을 특징으로 하는, 기판의 에칭방법.
- 제1항에 있어서, 에칭 보호층이 내식막 패턴과 에칭 보호층 형성용 조성물의 가열에 의해 형성됨을 특징으로 하는, 기판의 에칭 방법.
- 제1항 또는 제2항에 있어서, 에칭 보호층이, 내식막 표면 근방에 함유되는 산에 의해 에칭 보호층 형성용 조성물을 가교시킴으로써 형성됨을 특징으로 하는, 기판의 에칭방법.
- 제1항 내지 제3항 중의 어느 한 항에 있어서, 물을 함유하는 현상액이 물로 이루어짐을 특징으로 하는, 기판의 에칭 방법.
- 제1항 내지 제3항 중의 어느 한 항에 있어서, 물을 함유하는 현상액이 물과 알콜의 혼합물로 이루어짐을 특징으로 하는, 기판의 에칭 방법.
- 수가용성 또는 수분산성 수지, 가교제 및 용제로서의 물 및/또는 수용성 유기 용제를 함유함을 특징으로 하는, 제1항 내지 제5항 중의 어느 한 항의 기판의 에칭방법에 사용되는 에칭 보호층 형성용 조성물.
- 제6항에 있어서, 수용성 또는 수분산성의 수지가 아크릴산, 메타크릴산, 비닐 아세탈, 비닐 알콜, 에틸렌이민, 에틸렌 옥사이드, 스티렌, 스티렌 유도체, 다환 방향족계 비닐 화합물, 복소환계 비닐 화합물, 무수 말레산, 비닐 아민, 알릴 아민, 메타크릴아민, 비닐 메틸 에테르, 에틸렌 글리콜로 이루어진 그룹으로부터 선택된 하나 이상의 단량체로 형성된 중합체 또는 공중합체, 수용성 노볼락 수지, 옥사졸린기 함유 수용성 수지, 수용성 멜라민 수지, 수용성 요소 수지, 알키드 수지 및 설폰아미드로 이루어진 그룹으로부터 선택된 하나 이상임을 특징으로 하는 에칭 보호층 형성용 조성물.
- 제7항에 있어서, 수용성 또는 수분산성의 수지가 아크릴산, 메타크릴산, 비닐 아세탈, 비닐 알콜, 비닐피롤리돈, 에틸렌이민, 무수 말레산, 비닐 아민, 알릴 아민, 메타크릴아민 및 비닐메틸에테르로 이루어진 그룹으로부터 선택된 하나 이상의 단량체와 스티렌, 스티렌 유도체, 다환 방향족계 비닐 화합물 및 복소환계 비닐화합물로 이루어진 그룹으로부터 선택된 하나 이상의 단량체와의 공중합체로 이루어진 수용성 또는 수분산성의 수지 및 수용성 노볼락 수지로 이루어진 그룹으로부터 선택된 하나 이상의 수지 또는 이들 수지의 하나 이상과 옥사졸린기 함유 수용성 수지, 수용성 멜라민 수지, 수용성 요소 수지, 알키드 수지 및 설폰아미드로 이루어진 그룹으로부터 선택된 하나 이상과의 혼합물로 이루어짐을 특징으로 하는 에칭 보호층 형성용 조성물.
- 제6항 내지 제8항 중의 어느 한 항에 있어서, 수용성 가교제가 멜라민 유도체, 요소 유도체, 벤조구아나민 및 글리콜우릴로 이루어진 그룹으로부터 선택된 하나 이상임을 특징으로 하는 에칭 보호층 형성용 조성물.
- 제6항 내지 제9항 중의 어느 한 항에 있어서, 수용성 유기 용제가 탄소수 1 내지 4의 지방족 알콜, 프로필렌 글리콜 모노에틸 에테르, 락트산에스테르, 아세트산에틸 및 N-메틸피롤리돈으로 이루어진 그룹으로부터 선택된 하나 이상임을 특징으로 하는 에칭 보호층 형성용 조성물.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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JP2001277600A JP4237430B2 (ja) | 2001-09-13 | 2001-09-13 | エッチング方法及びエッチング保護層形成用組成物 |
JPJP-P-2001-00277600 | 2001-09-13 | ||
PCT/JP2002/008962 WO2003025677A1 (fr) | 2001-09-13 | 2002-09-04 | Procede de gravure et composition permettant de former une couche de protection contre la gravure |
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KR20040035782A true KR20040035782A (ko) | 2004-04-29 |
KR100884910B1 KR100884910B1 (ko) | 2009-02-20 |
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KR1020047003748A KR100884910B1 (ko) | 2001-09-13 | 2002-09-04 | 기판의 에칭방법 및 에칭 보호층 형성용 조성물 |
Country Status (9)
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US (1) | US7141177B2 (ko) |
EP (1) | EP1429185B1 (ko) |
JP (1) | JP4237430B2 (ko) |
KR (1) | KR100884910B1 (ko) |
CN (1) | CN100478781C (ko) |
AT (1) | ATE431574T1 (ko) |
DE (1) | DE60232343D1 (ko) |
TW (1) | TW575790B (ko) |
WO (1) | WO2003025677A1 (ko) |
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KR20200111248A (ko) * | 2018-01-30 | 2020-09-28 | 도쿄엘렉트론가부시키가이샤 | 기판 처리 방법, 기판 처리 장치 및 에칭액 |
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JP4235466B2 (ja) * | 2003-02-24 | 2009-03-11 | Azエレクトロニックマテリアルズ株式会社 | 水溶性樹脂組成物、パターン形成方法及びレジストパターンの検査方法 |
JP4012480B2 (ja) * | 2003-03-28 | 2007-11-21 | Azエレクトロニックマテリアルズ株式会社 | 微細パターン形成補助剤及びその製造法 |
WO2005013011A1 (ja) | 2003-08-04 | 2005-02-10 | Fujitsu Limited | レジストパターン厚肉化材料、それを用いたレジストパターンの製造方法及び半導体装置の製造方法 |
JP4490228B2 (ja) | 2004-06-15 | 2010-06-23 | 富士通株式会社 | レジストパターン厚肉化材料、レジストパターンの形成方法、半導体装置及びその製造方法 |
JP4679997B2 (ja) * | 2004-08-31 | 2011-05-11 | Azエレクトロニックマテリアルズ株式会社 | 微細パターン形成方法 |
JP4718145B2 (ja) | 2004-08-31 | 2011-07-06 | 富士通株式会社 | 半導体装置及びゲート電極の製造方法 |
JP4583860B2 (ja) | 2004-10-04 | 2010-11-17 | 富士通株式会社 | レジストパターン厚肉化材料、レジストパターンの形成方法、並びに、半導体装置及びその製造方法 |
US7595141B2 (en) * | 2004-10-26 | 2009-09-29 | Az Electronic Materials Usa Corp. | Composition for coating over a photoresist pattern |
JP4676325B2 (ja) | 2005-02-18 | 2011-04-27 | 富士通株式会社 | レジストパターン厚肉化材料、レジストパターンの形成方法、半導体装置及びその製造方法 |
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KR20200111248A (ko) * | 2018-01-30 | 2020-09-28 | 도쿄엘렉트론가부시키가이샤 | 기판 처리 방법, 기판 처리 장치 및 에칭액 |
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US20040238486A1 (en) | 2004-12-02 |
CN1555510A (zh) | 2004-12-15 |
CN100478781C (zh) | 2009-04-15 |
EP1429185A4 (en) | 2006-06-07 |
EP1429185A1 (en) | 2004-06-16 |
ATE431574T1 (de) | 2009-05-15 |
DE60232343D1 (de) | 2009-06-25 |
US7141177B2 (en) | 2006-11-28 |
JP2003084457A (ja) | 2003-03-19 |
KR100884910B1 (ko) | 2009-02-20 |
TW575790B (en) | 2004-02-11 |
JP4237430B2 (ja) | 2009-03-11 |
EP1429185B1 (en) | 2009-05-13 |
WO2003025677A1 (fr) | 2003-03-27 |
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