KR20020010605A - 깊은 개구부 형성을 위한 플라즈마처리 반응실에서의실리콘층 에칭공정 - Google Patents

깊은 개구부 형성을 위한 플라즈마처리 반응실에서의실리콘층 에칭공정 Download PDF

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Publication number
KR20020010605A
KR20020010605A KR1020017013210A KR20017013210A KR20020010605A KR 20020010605 A KR20020010605 A KR 20020010605A KR 1020017013210 A KR1020017013210 A KR 1020017013210A KR 20017013210 A KR20017013210 A KR 20017013210A KR 20020010605 A KR20020010605 A KR 20020010605A
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KR
South Korea
Prior art keywords
etching
plasma
gas
reactor
silicon layer
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KR1020017013210A
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English (en)
Korean (ko)
Inventor
대릴 맥레이놀즈
Original Assignee
리차드 로브그렌
램 리서치 코포레이션
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Application filed by 리차드 로브그렌, 램 리서치 코포레이션 filed Critical 리차드 로브그렌
Publication of KR20020010605A publication Critical patent/KR20020010605A/ko
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials

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  • Drying Of Semiconductors (AREA)
KR1020017013210A 1999-04-20 2000-04-06 깊은 개구부 형성을 위한 플라즈마처리 반응실에서의실리콘층 에칭공정 Withdrawn KR20020010605A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/295,634 US6191043B1 (en) 1999-04-20 1999-04-20 Mechanism for etching a silicon layer in a plasma processing chamber to form deep openings
US09/295,634 1999-04-20
PCT/US2000/009447 WO2000063960A1 (en) 1999-04-20 2000-04-06 Process for etching a silicon layer in a plasma processing chamber to form deep openings

Publications (1)

Publication Number Publication Date
KR20020010605A true KR20020010605A (ko) 2002-02-04

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020017013210A Withdrawn KR20020010605A (ko) 1999-04-20 2000-04-06 깊은 개구부 형성을 위한 플라즈마처리 반응실에서의실리콘층 에칭공정

Country Status (5)

Country Link
US (2) US6191043B1 (https=)
JP (1) JP4852196B2 (https=)
KR (1) KR20020010605A (https=)
TW (1) TW457584B (https=)
WO (1) WO2000063960A1 (https=)

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US6544860B1 (en) * 2000-03-06 2003-04-08 Koninklijke Philips Electronics N.V. Shallow trench isolation method for forming rounded bottom trench corners
US6743732B1 (en) * 2001-01-26 2004-06-01 Taiwan Semiconductor Manufacturing Company Organic low K dielectric etch with NH3 chemistry
US6451673B1 (en) * 2001-02-15 2002-09-17 Advanced Micro Devices, Inc. Carrier gas modification for preservation of mask layer during plasma etching
US6746961B2 (en) 2001-06-19 2004-06-08 Lam Research Corporation Plasma etching of dielectric layer with etch profile control
AU2002337812A1 (en) * 2001-10-31 2003-05-12 Tokyo Electron Limited Method of etching high aspect ratio features
US7547635B2 (en) * 2002-06-14 2009-06-16 Lam Research Corporation Process for etching dielectric films with improved resist and/or etch profile characteristics
US20040171260A1 (en) * 2002-06-14 2004-09-02 Lam Research Corporation Line edge roughness control
JP4098225B2 (ja) * 2003-12-01 2008-06-11 松下電器産業株式会社 プラズマエッチング方法
DE10331526A1 (de) * 2003-07-11 2005-02-03 Infineon Technologies Ag Verfahren zum anisotropen Ätzen einer Ausnehmung in ein Siliziumsubstrat und Verwendung einer Plasmaätzanlage
KR101083558B1 (ko) * 2003-12-01 2011-11-14 파나소닉 주식회사 플라즈마 에칭 방법
US20050280674A1 (en) 2004-06-17 2005-12-22 Mcreynolds Darrell L Process for modifying the surface profile of an ink supply channel in a printhead
US7309641B2 (en) * 2004-11-24 2007-12-18 United Microelectronics Corp. Method for rounding bottom corners of trench and shallow trench isolation process
US7202178B2 (en) * 2004-12-01 2007-04-10 Lexmark International, Inc. Micro-fluid ejection head containing reentrant fluid feed slots
JP5041696B2 (ja) * 2005-11-15 2012-10-03 パナソニック株式会社 ドライエッチング方法
US7985688B2 (en) * 2005-12-16 2011-07-26 Lam Research Corporation Notch stop pulsing process for plasma processing system
CN101379600A (zh) * 2006-02-01 2009-03-04 阿尔卡特朗讯公司 各向异性刻蚀方法
US7608195B2 (en) * 2006-02-21 2009-10-27 Micron Technology, Inc. High aspect ratio contacts
US7517804B2 (en) * 2006-08-31 2009-04-14 Micron Technologies, Inc. Selective etch chemistries for forming high aspect ratio features and associated structures
CN101553914B (zh) 2006-12-12 2011-02-23 Nxp股份有限公司 在基片中制造开口、通孔的方法和含该通孔的半导体器件
KR100838399B1 (ko) 2007-05-17 2008-06-13 주식회사 하이닉스반도체 반도체 소자의 트렌치 형성 방법
JP5135879B2 (ja) * 2007-05-21 2013-02-06 富士電機株式会社 炭化珪素半導体装置の製造方法
US8500913B2 (en) * 2007-09-06 2013-08-06 Micron Technology, Inc. Methods for treating surfaces, and methods for removing one or more materials from surfaces
US8263497B2 (en) * 2009-01-13 2012-09-11 International Business Machines Corporation High-yield method of exposing and contacting through-silicon vias
JP5305973B2 (ja) * 2009-02-20 2013-10-02 ラピスセミコンダクタ株式会社 トレンチ形成方法
WO2011066668A1 (en) * 2009-12-02 2011-06-09 C Sun Mfg. Ltd. Method of etching features into substrate
US8802571B2 (en) 2011-07-28 2014-08-12 Lam Research Corporation Method of hard mask CD control by Ar sputtering
JP2013110139A (ja) 2011-11-17 2013-06-06 Tokyo Electron Ltd 半導体装置の製造方法
US20140199833A1 (en) * 2013-01-11 2014-07-17 Applied Materials, Inc. Methods for performing a via reveal etching process for forming through-silicon vias in a substrate
CN104347390B (zh) * 2013-07-31 2017-06-27 中微半导体设备(上海)有限公司 一种等离子体刻蚀基片的方法
JP6557588B2 (ja) * 2015-12-04 2019-08-07 株式会社日立ハイテクノロジーズ ドライエッチング方法
JP6328703B2 (ja) * 2016-08-15 2018-05-23 東京エレクトロン株式会社 半導体装置の製造方法
WO2020131793A1 (en) * 2018-12-20 2020-06-25 Mattson Technology, Inc. Silicon mandrel etch after native oxide punch-through
CN112285828A (zh) * 2020-09-30 2021-01-29 中国科学院微电子研究所 一种端面耦合器及其封装方法、应用
CN114678270B (zh) * 2020-12-24 2025-08-08 中微半导体设备(上海)股份有限公司 一种电感耦合等离子处理装置及其刻蚀方法

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US4702795A (en) * 1985-05-03 1987-10-27 Texas Instruments Incorporated Trench etch process
US4726879A (en) 1986-09-08 1988-02-23 International Business Machines Corporation RIE process for etching silicon isolation trenches and polycides with vertical surfaces
FR2616030A1 (fr) * 1987-06-01 1988-12-02 Commissariat Energie Atomique Procede de gravure ou de depot par plasma et dispositif pour la mise en oeuvre du procede
US4992134A (en) * 1989-11-14 1991-02-12 Advanced Micro Devices, Inc. Dopant-independent polysilicon plasma etch
US5356515A (en) * 1990-10-19 1994-10-18 Tokyo Electron Limited Dry etching method
US5296095A (en) * 1990-10-30 1994-03-22 Matsushita Electric Industrial Co., Ltd. Method of dry etching
US5933748A (en) * 1996-01-22 1999-08-03 United Microelectronics Corp. Shallow trench isolation process
US5843226A (en) * 1996-07-16 1998-12-01 Applied Materials, Inc. Etch process for single crystal silicon
JP3907087B2 (ja) * 1996-10-28 2007-04-18 キヤノンアネルバ株式会社 プラズマ処理装置
US6033991A (en) * 1997-09-29 2000-03-07 Cypress Semiconductor Corporation Isolation scheme based on recessed locos using a sloped Si etch and dry field oxidation

Also Published As

Publication number Publication date
US6191043B1 (en) 2001-02-20
WO2000063960A1 (en) 2000-10-26
TW457584B (en) 2001-10-01
JP2002542623A (ja) 2002-12-10
JP4852196B2 (ja) 2012-01-11
US20010001743A1 (en) 2001-05-24

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