CN112285828A - 一种端面耦合器及其封装方法、应用 - Google Patents

一种端面耦合器及其封装方法、应用 Download PDF

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CN112285828A
CN112285828A CN202011062486.3A CN202011062486A CN112285828A CN 112285828 A CN112285828 A CN 112285828A CN 202011062486 A CN202011062486 A CN 202011062486A CN 112285828 A CN112285828 A CN 112285828A
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face coupler
coupler
silicon
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唐波
张鹏
杨妍
李志华
刘若男
李彬
黄凯
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Priority to PCT/CN2021/081449 priority patent/WO2022068153A1/zh
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Abstract

本发明涉及一种端面耦合器及其封装方法、应用。一种端面耦合器的封装方法，包括：在SOI片上形成端面耦合器；在端面耦合器设有沟槽开口的表面等离子体增强化学气相沉积氧化硅；进行后续封装工序。本发明利用PECVD的低台阶覆盖率特点对端面耦合器的沟槽开口封口，解决了后续封装材料填充堵塞沟槽导致器件失效的问题。

Description

一种端面耦合器及其封装方法、应用
技术领域
本发明涉及光子设备领域，特别涉及一种端面耦合器及其封装方法、应用。
背景技术
硅光子技术以硅作为光学介质，利用CMOS(互补金属氧化物半导体，英文全称ComplementaryMetal Oxide Semiconductor)工艺进行光学器件的开发和集成，有望实现低成本、高速的光通信，拥有广阔的市场应用前景。抑制硅光子芯片广泛应用的关键问题之一的是光纤与硅光子芯片的耦合。与光纤的耦合问题是任何一个硅光子芯片或产品必须解决的问题。硅波导耦合器主要包括两种，即光栅耦合器和端面耦合器。光栅耦合器的优点是对准容差大、便于封装，并且可进行片上测试等，但其耦合效率不高，工作带宽窄。端面耦合器(Edge Coupler)一般采用楔形结构，其优点是耦合效率高、工作带宽大。
目前端面耦合器的生产工艺包括分为前道工艺线和后道封装线，前道工艺线主要指CMOS(互补式金属氧化物半导体)的生产线。由于后道封装线通常会用到金、铜等重金属，完成后道封装线的圆片通常不能回到前道线继续工艺。在后道封装存在的问题是：前道制作完的端面耦合器直接送去封装线，端面耦合器区域的硅槽裸露，封装时会导致封装材料(例如金属或者氮氧化硅等低折射率材料)填充进耦合器，导致耦合器失效。
为此，特提出本发明。
发明内容
本发明的主要目的在于提供一种端面耦合器的封装方法，该方法利用PECVD的低台阶覆盖率特点对端面耦合器的沟槽开口封口，解决了后续封装材料填充堵塞沟槽导致器件失效的问题。
为了实现以上目的，本发明提供了以下技术方案。
一种端面耦合器的封装方法，包括：
在SOI片上形成端面耦合器；
在端面耦合器设有沟槽开口的表面等离子体增强化学气相沉积氧化硅；
进行后续封装工序。
与现有技术相比，本发明在常规的封装工序之前增加了一道工序——等离子体增强化学气相沉积(PECVD)氧化硅，增加的该工序能对端面耦合器的沟槽开口适当(而不是过度填充)封口，从而避免后续封装材料填充堵塞沟槽导致器件失效的问题。这是因为PECVD相比LPCVD、ALD等其他沉积工艺具有更低的台阶覆盖率，即沉积膜的一致性较差，从而使得沉积的氧化硅膜在沟槽开口处的膜更薄(相比端面耦合器顶层表面)，这样可以充分保留沟槽内的空腔，将封口对沟槽的不利影响最小化。然而在本领域其他器件的制作中，沉积膜(例如绝缘膜、电极、介电膜等)往往要求较高的台阶覆盖率。可见，本发明将PECVD的缺点应用在端面耦合器的封装上，反而转化为优点，巧妙解决了封装和集成无法兼顾的问题。
上述方法得到的端面耦合器可用于固体开关、逻辑电路、脉冲放大电路等光子器件中。
与现有技术相比，本发明达到了以下技术效果：
(1)避免了封装材料(例如金属或者氮氧化硅等低折射率材料)填充堵塞耦合器的沟槽，改善了器件性能。
附图说明
通过阅读下文优选实施方式的详细描述，各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的，而并不认为是对本发明的限制。
图1为本发明列举的端面耦合器的结构示意图；
图2为图1的结构封口的形貌图；
图3为端面耦合器封口前的电镜图；
图4为端面耦合器封口后的电镜图。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
为了适应端面耦合器生产工艺由前至后依次操作、无法返工的特点，同时解决沟槽被大量填充而致器件失效的问题，本发明提供了以下实施方案。
一种端面耦合器的封装方法，包括：
在SOI片上形成端面耦合器；
在端面耦合器设有沟槽开口的表面等离子体增强化学气相沉积氧化硅；
进行后续封装工序。
与现有技术相比，该方案在常规的封装工序之前增加了一道工序——等离子体增强化学气相沉积(PECVD)氧化硅，增加的该工序能对端面耦合器的沟槽开口适当(而不是过度填充)封口，从而避免后续封装材料填充堵塞沟槽导致器件失效的问题。这是因为PECVD相比LPCVD、ALD等其他沉积工艺具有更低的台阶覆盖率，即沉积膜的一致性较差，从而使得沉积的氧化硅膜在沟槽开口处的膜更薄(相比端面耦合器顶层表面)，这样可以充分保留沟槽内的空腔，将封口对沟槽的不利影响最小化。然而在本领域其他器件的制作中，沉积膜(例如绝缘膜、电极、介电膜等)往往要求较高的台阶覆盖率。
可见，本发明将PECVD的缺点应用在端面耦合器的封装上，反而转化为优点，巧妙解决了封装和集成无法兼顾的问题。
本发明所述的沟槽主要指刻蚀至硅衬底上的沟槽，相应地，在形成端面耦合器时包括：在硅衬底上形成沟槽。
本发明对沟槽的形状不作限定，包括但不限于典型的底部呈类球形的沟槽。例如图1所示的端面耦合器，由下至上依次包括硅衬底1、埋氧层2、顶层硅3、氧化硅覆盖层4，其中开设的沟槽5伸入到底层的硅衬底1上，底部呈类球形；顶层硅中形成有矩形波导6。经过本发明的封口工艺后，得到如图2所示的形貌，最上层为氧化硅膜7，其顶层的膜厚显著大于侧墙膜厚。
在一些优选的实施方式中，所述SOI片中的埋氧层为氧化硅。
在实际封装中，可通过调整PECVD的工艺条件，使台阶覆盖率达到更低。
在一些优选的实施方式中，所述等离子体增强化学气相沉积(PECVD)的工艺条件为：沉积温度400℃，腔体压力6-10Torr，反射功率600-700W。
台阶覆盖率(step coverage，简称SC)＝(边墙膜厚度/顶层膜厚度)×100％。
以图1所示的端面耦合器为例，其封口前的电镜图如图3所示，封口后的电镜图如图4，沟槽底部的空腔仍然保持完整，封口对器件的不利影响可忽略不计。
在一些优选的实施方式中，所述等离子体增强化学气相沉积的氧化硅膜厚根据以下因素确定：开口尺寸越大，需要沉积的厚度越厚，需要沉积的厚度约为开口宽度。
PECVD沉积时的硅源包括但不限于：无碳前体，例如硅烷(SiH4)、乙硅烷(Si2H6)、三硅烷(Si3H8)和二氯硅烷(SiH2Cl2)；含碳前体，例如烷氧基硅烷、烷基硅烷、环状硅氧烷、炔基硅烷和原硅酸盐(如正硅酸乙酯)。合适的含氧反应物的示例包括O2、CO2和N2O。当含硅前体包括硅和氧(例如，正硅酸乙酯)时，这种单一前体可以用作硅源和含氧反应物。含有含硅前体和含氧反应物的沉积工艺气体通常与稀释气体一起流入处理室(在一些情况下具有预先汽化的液体反应物)。稀释气体的示例包括N2和稀有气体，例如氦气、氩气、氖气和氪气。
在一些优选的实施方式中，PECVD沉积时的硅源为正硅酸乙酯。
本发明对后续封装工序的流程及工艺条件不作限定，包括但不限于典型的如下流程：硅通孔技术(TSV)开孔，种子层填充或Cu电镀。
利用上文任意封装工艺获得端面耦合器可用于固体开关、逻辑电路、脉冲放大电路等光子器件中。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (8)

1.一种端面耦合器的封装方法，其特征在于，包括：
在SOI片上形成端面耦合器；
在端面耦合器设有沟槽开口的表面等离子体增强化学气相沉积氧化硅；
进行后续封装工序。
2.根据权利要求1所述的封装方法，其特征在于，所述等离子体增强化学气相沉积采用的硅源为正硅酸乙酯。
3.根据权利要求1或2所述的封装方法，其特征在于，所述等离子体增强化学气相沉积的工艺条件为：沉积温度400℃，腔体压力6-10Torr，反射功率600-700W。
4.根据权利要求1所述的封装方法，其特征在于，所述形成端面耦合器时包括：在硅衬底上形成沟槽。
5.根据权利要求1所述的封装方法，其特征在于，所述后续封装工序包括：TSV开孔，种子层填充或Cu电镀。
6.根据权利要求1所述的封装方法，其特征在于，所述SOI片中包括氧化硅埋氧层。
7.一种端面耦合器，其特征在于，其采用权利要求1-6任一项所述的封装方法获得。
8.权利要求7所述的端面耦合器在固体开关或逻辑电路中的应用。
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