KR19990079658A - 반도체패키지 - Google Patents

반도체패키지 Download PDF

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Publication number
KR19990079658A
KR19990079658A KR1019980012364A KR19980012364A KR19990079658A KR 19990079658 A KR19990079658 A KR 19990079658A KR 1019980012364 A KR1019980012364 A KR 1019980012364A KR 19980012364 A KR19980012364 A KR 19980012364A KR 19990079658 A KR19990079658 A KR 19990079658A
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South Korea
Prior art keywords
semiconductor chip
semiconductor
semiconductor package
lead
input
Prior art date
Application number
KR1019980012364A
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English (en)
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KR100260997B1 (ko
Inventor
이선구
Original Assignee
마이클 디. 오브라이언
앰코 테크놀로지 코리아 주식회사
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Application filed by 마이클 디. 오브라이언, 앰코 테크놀로지 코리아 주식회사 filed Critical 마이클 디. 오브라이언
Priority to KR1019980012364A priority Critical patent/KR100260997B1/ko
Priority to JP06867099A priority patent/JP3196026B2/ja
Priority to US09/287,711 priority patent/US6303997B1/en
Publication of KR19990079658A publication Critical patent/KR19990079658A/ko
Application granted granted Critical
Publication of KR100260997B1 publication Critical patent/KR100260997B1/ko

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    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

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Abstract

본 발명은 반도체패키지에 관한 것으로, 반도체패키지의 두께를 초박형으로 함과 더불어 열방출성을 향상시키고 또한 그 반도체패키지를 다수개로 적층하여 사용할 수 있음으로써 실장밀도를 극대화시키기 위해, 다수의 입출력패드가 구비된 반도체칩(2)과; 상기 반도체칩(2)의 상면 외주연에 위치되어 있되, 일단에는 상하돌출부(6b)가 형성되어 있는 다수의 리드(6a)와; 상기 반도체칩(2)의 입출력패드와 리드(6a)의 타단을 전기적으로 접속하는 접속수단과; 상기 리드(6a)의 상하돌출부(6b) 하면에 입출력단자로써 융착된 솔더볼(10)과; 상기 반도체칩(2), 접속수단 등을 외부의 환경으로부터 보호하기 위해 봉지재로 감싸서 형성된 몸체(12)를 포함하여 이루어진 것을 특징으로 한다.

Description

반도체패키지
본 발명은 반도체패키지에 관한 것으로, 보다 상세하게 설명하면 반도체패키지의 두께를 초박형으로 하는 동시에 전기적 성능 및 열방출성을 향상시키고 또한 그 반도체패키지를 다수개로 적층하여 사용할 수 있음으로써 실장밀도를 극대화시킬 수 있는 반도체패키지에 관한 것이다.
일반적으로 메모리용반도체소자를 위한 패키징 기술은 고밀도 실장기술을 요구하고 있다. 즉, 동일한 면적에서 보다 많은 메모리 용량을 확보하기 위해서는 반도체칩의 집적 기술도 중요하지만, 마더보드(Mother Board) 등에의 실장시에 얼마나 많은 반도체패키지를 적은 면적에 효율적으로 실장하는가도 큰 변수로 작용하기 때문이다. 이와 같이 실장밀도를 증가시키는 방법의 하나로써 종래에 리드프레임을 이용한 반도체패키지 또는 볼그리드어레이(Ball Grid Array)반도체패키지(이하 BGA패키지로 칭함)를 수직으로 적층한채 마더보드에 실장하는 기술이 알려져 있다.
상기의 반도체패키지 중에서 최근의 BGA패키지(30')를 이용한 적층형 반도체패키지(40')를 도1에 도시하였다.
도시된 바와 같이 종래 적층형 반도체패키지(40')는 다수의 BGA패키지(30')를 일렬로 쌓아 놓은 형태를 한다. 상기 각각의 BGA패키지(30') 구조는 인쇄회로기판(2')을 중심으로 그 상면에 접착제(4')로 반도체칩(6')이 접착되어 있고, 상기 반도체칩(6')의 입/출력패드(도시되지 않음)는 인쇄회로기판(2') 상면에 전도체로 형성된 회로패턴(8')에 전도성와이어(10')로 본딩되어 있으며, 상기 회로패턴(8')은 전도성비아홀(도시되지 않음)을 통해 하부의 솔더볼랜드(12')에 연결되어 있으며, 상기 솔더볼랜드(12')에는 솔더볼(14')이 융착되어 있으며, 상기 인쇄회로기판(2')의 상면은 반도체칩(6') 및 전도성와이어(10') 등을 외부의 환경으로부터 보호하기 위해 봉지재로 몸체(16')가 형성되어 있다. 여기서 상기 인쇄회로기판(2') 상면에 형성된 회로패턴(8')은 외부로 직접 노출되어 있고, 상기 회로패턴(8')에는 상부를 향하여 돌출된 돌출패드(18')가 형성되어 있다.
이러한 구조를 하는 BGA패키지는 각각의 독립된 형태로 마더보드에 실장될 수도 있으며, 그 실장 밀도를 증대하기 위해 하나의 BGA패키지 상면에 또다른 BGA패키지를 융착하되 상면의 BGA패키지의 하면에 형성된 솔더볼을 그 하면의 BGA패키지 상면에 형성된 돌출패드에 융착하는 방법으로 다수개를 적층함으로써 실장밀도를 증대시키고 있다.
그러나 이러한 종래의 적층형 반도체패키지는 각각의 BGA패키지 두께가 차지하는 부피가 큼으로써 전체 높이가 커지는 단점이 있다. 즉, 단순히 기존의 일반적인 BGA패키지의 인쇄회로기판 상부 주변 둘레에 돌출패드를 형성하고 그 돌출패드에 솔더볼을 융착하는 방법을 사용함으로써 실장 밀도는 증가하지만 그 높이가 커짐으로써 결국 전자기기의 부피를 축소하는데는 한계를 나타내고 있다. 또한 상기와 같이 다수의 BGA패키지를 적층함으로서 반도체칩으로부터 발생되는 열도 증가하지만 이를 적절히 방출시키는 수단이 없음으로서 그 동작속도가 현저히 저하되는 문제점이 있다. 아울러 상기 각각의 BGA패키지용 인쇄회로기판상에는 회로패턴이 길게 형성되어 있음으로서 전체 신호라인이 길어져 전기적 성능이 현저히 저하되는 단점이 있고 또한 고가의 인쇄회로기판을 사용함으로써 제조비용이 상승하는 문제점도 있다.
본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 상하돌출패드를 갖는 리드프레임을 이용하여 두께가 얇은 반도체패키지를 구비함과 아울러 전기적 성능 및 열방출성을 향상시킬 수 있고, 각각의 반도체패키지가 적층될 수 있도록 함으로써 실장밀도를 증대시킬 수 있는 반도체패키지를 제공하는데 있다.
도1은 종래의 적층형 반도체패키지를 도시한 단면도이다.
도2a 및 도2b는 본 발명에 의한 반도체패키지의 한실시예를 도시한 단면도이다.
도3은 도2a의 반도체패키지를 도시한 평면도이다.
도4는 본 발명에 의한 반도체패키지가 다수개 적층된 상태를 도시한 단면도이다.
도5a내지 도5d는 본 발명에 의한 반도체패키지의 다른 실시예들을 도시한 단면도이다.
도6a 내지 도6b는 본 발명에 의한 반도체패키지의 또다른 실시예들을 도시한 단면도이다.
- 도면중 주요 부분에 대한 부호의 설명 -
2 ; 반도체칩 4 ; 접착수단
6a ; 리드(Lead) 6b ; 상하돌출부
6c ; 반도체칩탑재판 8a ; 전도성와이어(Conductive Wire)
8b ; 전도성볼(Conductive Ball)
8c ; TAB(Tape Automated Bonding)본딩부
10 ; 솔더볼(Solder Ball) 12 ; 몸체
30,31,32,33,34,35,36,37 ; 본발명에 의한 반도체패키지
40 ; 본발명에 의한 반도체패키지가 적층된 상태
상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지는 다수의 입출력패드가 구비된 반도체칩과; 상기 반도체칩의 상면 외주연에 위치되어 있되, 일단에는 상하돌출부가 형성되어 있는 다수의 리드와; 상기 반도체칩의 입출력패드와 리드의 타단을 전기적으로 접속하는 접속수단과; 상기 리드의 상하돌출부 하면에 입출력단자로써 융착된 솔더볼과; 상기 반도체칩, 접속수단 등을 외부의 환경으로부터 보호하기 위해 봉지재로 감싸서 형성된 몸체를 포함하여 이루어진 것을 특징으로 한다.
여기서, 상기 리드는 반도체칩의 상면에까지 연장되어 반도체칩의 입출력패드와 접속수단으로 연결될 수 있는데, 상기 접속수단은 전도성볼, 전도성와이어를 이용하거나 상기 리드를 반도체칩의 입출력패드에 직접 열압착한 TAB본딩부를 이용할 수 있다.
또한, 상기 반도체칩의 상면에는 금속재의 반도체칩탑재판이 접착수단으로 접착될 수 있는데, 그 반도체칩탑재판은 상면이 외부로 노출되도록 하여 열방출성을 향상시킬 수 있다.
한편, 상기 반도체칩탑재판은 반도체칩의 넓이보다 넓게 형성하거나 또는 좁게 형성하는 것이 가능하며, 상기 리드와 반도체칩탑재판의 상면 모두가 외부를 향해 노출될 수 있으며, 이때에는 상기 리드와 반도체칩탑재판의 상면을 동일평면으로 형성한다.
그리고, 상기 몸체는 반도체칩의 저면이 외부로 직접 노출되도록 형성함으로서 상기 반도체칩탑재판과 상기 노출된 반도체칩의 일면으로 인해 열방출성을 더욱 향상시킬 수 있다.
이하 본 발명이 속하는 기술분야에서 통상의 지식을 가진자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.
도2a, 도2b 및 도3은 본 발명에 의한 반도체패키지(30,31)를 도시한 단면도 및 평면도이다.
먼저 도2a를 참조하면, 반도체칩(2) 상면의 중앙부에는 다수개의 입출력패드(도시되지 않음)가 형성되어 있고, 그 상부에는 리드(6a)가 접착수단(4)으로 접착되어 있다. 상기 리드(6a)는 상기 반도체칩(2)의 상면에 형성된 입출력패드 바깥둘레를 향하여 방사상으로 길게 연장되어 있고, 그 연장된 끝단 즉, 반도체칩(2)의 바깥둘레에 위치된 리드(6a) 단부에는 상하로 돌출된 상하돌출부(6b)가 형성되어 있다. 상기 상하돌출부(6b)는 통상 에칭(Etching) 기술로 형성되며 이는 구리원판을 이용하여 리드프레임의 제조시 리드(6a)부분에는 할프에칭(Half Etching)기술을 이용하여 에칭하고, 상기 상하돌출부(6b)에는 에칭을 적용시키지 않음으로써 상하돌출부(6b) 두께가 리드(6a)의 두께보다 약 3배 정도 커지도록 한 것이다. 이와 같이 상하돌출부(6b)의 두께를 리드(6a)두께보다 크게 형성한 이유는 차후에 솔더볼(10)의 융착시 그 솔더볼(10)이 위치된 부분의 두께가 반도체칩(2)이 위치된 부분의 두께보다 크게 되도록 함으로써 마더보드(Mother Board)에 실장하거나 다수의 반도체패키지(30)를 적층가능하게 하기 위함이다.
또한 상기 리드(6a)를 반도체칩(2)의 상면에 접착시키기 위한 접착수단(4)은 비전도성인 물질로써 일반적인 접착제를 이용하거나 또는 양면테이프를 이용한다.
한편, 상기 반도체칩(2)의 입출력패드와 리드(6a) 일단은 접속수단으로 전도성와이어(8) 즉, 골드(Au)와이어 또는 알루미늄(Al)와이어를 이용한다.
상기 리드(6a) 단부에 형성된 상하돌출부(6b)는 그 하면에 입출력단자로써 솔더볼(10)이 융착되어 있고, 상기 상하돌출부(6b)의 상부 표면을 제외한(도3 참조) 상기 반도체칩(2), 전도성와이어(8)로 된 접속수단, 리드(6a) 등은 외부의 환경으로부터 보호되도록 에폭시몰딩컴파운드(Epoxy Molding Compound) 또는 글럽탑(Glop Top)과 같은 봉지재로 봉지되어 몸체(12)를 형성하고 있다.
한편, 도2b는 상기 리드(6a)의 단부를 반도체칩(2)의 입출력패드상에 올려놓고 열압착하여 직접 연결시킴으로서 TAB본딩부(8c)를 형성한 것이며, 이것은 접속수단으로서 전도성와이어(8a)를 사용하지 않아도 되어 생산비를 절감할 수 있는 장점이 있다.
도4는 본 발명에 의한 반도체패키지(30)가 다수개로 적층된 상태를 도시한 단면도이다.
본 발명에 의한 반도체패키지(30)는 독립된 개체로써 마더보드에 직접 실장하는 것도 가능하지만 도시된 바와 같이 다수개를 적층한 상태(40)로 마더보드에 실장하는 것도 가능하다. 이와 같이 다수개의 반도체패키지(30)를 적층할 경우에는 리드(6a) 단부에 형성된 상하돌출부(6b)를 이용하게 되는데 상기 상하돌출부(6b)의 상부표면은 몸체(12)의 외부로 노출되어 있기 때문에 가능한 것이다. 즉, 상기 노출된 상하돌출부(6b)의 상부표면에 다른 반도체패키지(30)의 솔더볼(10)이 위치되도록 위치를 정렬한 다음 리플로우(Reflow)함으로써 적층을 하게 되고 그 적층된 반도체패키지(30)의 상면에 상기와 같은 과정을 재차 실시함으로써 다수개의 반도체패키지(30)를 수직으로 적층하여 사용할 수 있는 것이다.
한편, 도5a내지 도5d는 본 발명에 의한 반도체패키지의 다른 실시예들을 도시한 단면도이다.
먼저 도5a에 도시된 반도체패키지(32)는, 반도체칩(2)상에 그 반도체칩(2)의 상면 넓이보다 큰 반도체칩탑재판(6c)이 접착수단(4)에 의해 접착되어 있음으로서 반도체칩(2)으로부터 발생되는 열을 외부로 신속히 방출할 수 있도록 되어 있다. 또한 리드(6a)의 길이는 도2a에 도시된 것보다 작게 형성된채 반도체칩(2)의 상면 외주연에만 위치되어 있고, 상기 리드(6a)의 단부와 반도체칩(2)의 입출력패드는 접속수단으로서 전도성와이어(8a)에 의해 접속되어 있다. 여기서 상기 입출력패드는 반도체칩(2)의 하면에 형성되어 있다.
도5b에 도시된 반도체패키지(33)는, 반도체칩탑재판(6c)이 그 반도체칩(2)의 상면 넓이보다 작게 형성된채 접착수단(4)으로 접착되어 있고, 반도체칩(2)의 상면 외주연에 형성된 입출력패드와 리드(6a)의 단부는 접속수단으로서 전도성와이어(8a)에 의해 연결되어 있다. 여기서 상기와 같이 반도체칩탑재판(6c)이 반도체칩(2)의 상면 넓이보다 작게 형성됨으로서 상기 입출력패드가 반도체칩(2)의 상면 외주연에 위치하도록 하여 반도체패키지를 제조할 수 있는 장점이 있다.
도5c에 도시된 반도체패키지(34)는, 반도체칩(2)의 상면 넓이보다 작은 반도체칩탑재판(6c)이 접착수단(4)에 의해 접착되어 있으며, 상기 반도체칩(2)의 입출력패드와 리드(6a)의 단부는 접속수단으로서 전도성볼(8b)에 의해 연결되어 있음으로서 전기적 경로를 더욱 짧게 할 수 있다.
한편, 도5d에 도시된 반도체패키지(35)는 반도체칩(2)의 상면 넓이보다 작은 반도체칩탑재판(6c)이 접착수단(4)에 의해 접착되어 있되, 상기 반도체칩탑재판(6c)의 두께는 리드(6a)와 동일평면을 이루도록 되어 있다. 즉, 상기 리드(6a)의 상면 전체 및 반도체칩탑재판(6c)의 상면전체가 할프에칭되어 형성됨으로서 그 반도체패키지의 두께를 초박형으로 형성할 수 있고, 또한 상기 반도체칩탑재판(6c) 및 리드(6a)의 상면이 모두 외부에 직접 노출되어 있음으로서 반도체칩(2)으로부터의 열을 보다 용이하게 방출할 수 있는 효과가 있는 것이다.
다음으로 도6a 내지 도6b는 본 발명에 의한 반도체패키지의 또다른 실시예들을 도시한 단면도이다.
도6a의 반도체패키지(36)는 도5c와 마찬가지로 반도체칩(2)의 상면 넓이보다 작은 반도체칩탑재판(6c)이 접착수단(4)에 의해 접착되어 있고, 상기 반도체칩(2)의 입출력패드와 리드(6a)의 단부는 전도성볼(8b)에 의해 연결되어 있다. 여기서 상기 반도체칩(2)은 저면에는 외부로 노출된 노출면(2a)이 형성되어 있는데, 이것은 상기 반도체칩(2)의 주변에만 액상의 봉지재등을 도포하여 몸체(12)를 형성한 것이다. 상기와 같이 반도체칩(2)의 일면에 노출면(2a)이 형성됨으로서 상기 반도체칩탑재판(6c)의 작용과 더불어 반도체칩(2)의 열을 보다 양호하게 방출할 수 있게 된다.
또한 도6b의 반도체패키지(37)는 도5d와 마찬가지로 반도체칩(2)의 상면 넓이보다 작은 반도체칩탑재판(6c)이 접착수단(4)에 의해 접착되어 있되, 상기 반도체칩탑재판(6c)의 두께는 리드(6a)와 동일평면을 이루도록 되어 있는 동시에 반도체칩(2)의 주변에만 봉지재가 도포되어 몸체(12)를 형성함으로서, 반도체칩(2)의 노출면(2a)을 형성하여 상기의 도6a의 반도체패키지(36)와 같이 반도체칩의 열방출성을 더욱 향상시킬 수 있게 된다.
상기 도6a와 6b와 같이 반도체칩의 저면에 몸체외부로 노출된 노출면을 형성하는 것은 본 발명의 모든 실시예에 적용가능하며, 상기와 같이 반도체칩의 저면이 노출되도록 몸체를 형성하는 방법은 글럽탑과 같은 액상봉지재를 봉지하고자 하는 부분에만 도포함으로서 가능한 것이며 이러한 액상봉지재는 당업자에게 잘 알려져 있는 물질이므로 여기서는 설명을 생략한다.
이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기예만 한정되지 않으며 당업자가 본 발명의 내용을 숙지한 후에는 본 발명의 범주와 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예를 창작할 수 도 있을 것이다.
이상에서와 같이 본 발명에 의한 반도체패키지에 의하면, 인쇄회로기판 대신에 리드와 솔더볼을 사용함으로써 반도체패키지의 두께를 현저히 감소시킬 수 있으며, 전체적인 신호라인을 짧게 함으로서 그 전기적 성능을 향상시킬 수 있으며, 반도체칩탑재판을 외부로 노출시키거나 또는 반도체칩의 일면을 직접 외부로 노출시킴으로서 반도체칩으로부터의 열을 용이하게 방출할 수 있는 효과가 있다. 또한 본 발명에 의한 반도체패키지를 다수개 적층하여 메모리 소자로 사용함으로서 적은 면적에서 메모리용량을 극대화할 수 있는 효과가 있는 것이다.

Claims (10)

  1. 다수의 입출력패드가 구비된 반도체칩(2)과;
    상기 반도체칩(2)의 상면 외주연에 위치되어 있되, 일단에는 상하돌출부(6b)가 형성되어 있는 다수의 리드(6a)와;
    상기 반도체칩(2)의 입출력패드와 리드(6a)의 타단을 전기적으로 접속하는 접속수단과;
    상기 리드(6a)의 상하돌출부(6b) 하면에 입출력단자로써 융착된 솔더볼(10)과;
    상기 반도체칩(2), 접속수단 등을 외부의 환경으로부터 보호하기 위해 봉지재로 감싸서 형성된 몸체(12)를 포함하여 이루어진 것을 특징으로 하는 반도체패키지.
  2. 제1항에 있어서, 상기 리드(6a)는 반도체칩(2)의 상면에까지 연장되어 반도체칩(2)의 입출력패드와 접속수단으로 연결된 것을 특징으로 하는 반도체패키지.
  3. 제1항에 있어서, 상기 접속수단은 전도성볼(8a)인 것을 특징으로 하는 반도체패키지.
  4. 제1항에 있어서, 상기 접속수단은 전도성와이어(8b)인 것을 특징으로 하는 반도체패키지.
  5. 제1항에 있어서, 상기 접속수단은 리드 끝단을 열압착하여 반도체칩의 입출력패드에 직접 접속시킨 것을 특징으로 하는 반도체패키지.
  6. 제1항에 있어서, 상기 반도체칩(2)의 상면에는 금속재의 반도체칩탑재판(6c)이 접착수단(4)으로 접착되어 있는 것을 특징으로 하는 반도체패키지.
  7. 제6항에 있어서, 상기 반도체칩탑재판(6c)은 그 상면이 외부를 향해 노출되어 있는 것을 특징으로 하는 반도체패키지.
  8. 제6항에 있어서, 상기 리드(6a)와 반도체칩탑재판(6c)은 그 상면이 외부를 향해 노출되어 있는 것을 특징으로 하는 반도체패키지.
  9. 제8항에 있어서, 상기 리드(6a)와 반도체칩탑재판(6c)은 그 상면이 동일평면인 것을 특징으로 하는 반도체패키지.
  10. 제1항에 있어서, 상기 몸체(12)는 반도체칩(2)의 저면이 외부로 직접 노출되도록 형성된 것을 특징으로 하는 반도체패키지.
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US09/287,711 US6303997B1 (en) 1998-04-08 1999-04-07 Thin, stackable semiconductor packages

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KR100549311B1 (ko) * 2000-08-21 2006-02-02 앰코 테크놀로지 코리아 주식회사 반도체패키지

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US6303997B1 (en) 2001-10-16

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