KR100996725B1 - 변형된 디바이스 막을 구비한 실리콘-온-절연체 디바이스및 절연 산화물을 부분적으로 대체하여 상기 디바이스를생성하는 방법 - Google Patents

변형된 디바이스 막을 구비한 실리콘-온-절연체 디바이스및 절연 산화물을 부분적으로 대체하여 상기 디바이스를생성하는 방법 Download PDF

Info

Publication number
KR100996725B1
KR100996725B1 KR1020047021192A KR20047021192A KR100996725B1 KR 100996725 B1 KR100996725 B1 KR 100996725B1 KR 1020047021192 A KR1020047021192 A KR 1020047021192A KR 20047021192 A KR20047021192 A KR 20047021192A KR 100996725 B1 KR100996725 B1 KR 100996725B1
Authority
KR
South Korea
Prior art keywords
silicon
oxide layer
buried oxide
recesses
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020047021192A
Other languages
English (en)
Korean (ko)
Other versions
KR20050013248A (ko
Inventor
마스자라위톨드피.
Original Assignee
글로벌파운드리즈 인크.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 글로벌파운드리즈 인크. filed Critical 글로벌파운드리즈 인크.
Publication of KR20050013248A publication Critical patent/KR20050013248A/ko
Application granted granted Critical
Publication of KR100996725B1 publication Critical patent/KR100996725B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281Lateral isolation by selective oxidation of silicon
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/674Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743Silicon
    • H10D30/6744Monocrystalline silicon
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/791Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
KR1020047021192A 2002-06-25 2003-06-04 변형된 디바이스 막을 구비한 실리콘-온-절연체 디바이스및 절연 산화물을 부분적으로 대체하여 상기 디바이스를생성하는 방법 Expired - Fee Related KR100996725B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/178,542 2002-06-25
US10/178,542 US6680240B1 (en) 2002-06-25 2002-06-25 Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide
PCT/US2003/017824 WO2004001798A2 (en) 2002-06-25 2003-06-04 A silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide

Publications (2)

Publication Number Publication Date
KR20050013248A KR20050013248A (ko) 2005-02-03
KR100996725B1 true KR100996725B1 (ko) 2010-11-25

Family

ID=29999123

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020047021192A Expired - Fee Related KR100996725B1 (ko) 2002-06-25 2003-06-04 변형된 디바이스 막을 구비한 실리콘-온-절연체 디바이스및 절연 산화물을 부분적으로 대체하여 상기 디바이스를생성하는 방법

Country Status (8)

Country Link
US (1) US6680240B1 (enExample)
EP (1) EP1516362A2 (enExample)
JP (1) JP4452883B2 (enExample)
KR (1) KR100996725B1 (enExample)
CN (1) CN1333454C (enExample)
AU (1) AU2003238916A1 (enExample)
TW (1) TWI289895B (enExample)
WO (1) WO2004001798A2 (enExample)

Families Citing this family (74)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7227176B2 (en) 1998-04-10 2007-06-05 Massachusetts Institute Of Technology Etch stop layer system
US6573126B2 (en) * 2000-08-16 2003-06-03 Massachusetts Institute Of Technology Process for producing semiconductor article using graded epitaxial growth
US6940089B2 (en) * 2001-04-04 2005-09-06 Massachusetts Institute Of Technology Semiconductor device structure
WO2003079415A2 (en) * 2002-03-14 2003-09-25 Amberwave Systems Corporation Methods for fabricating strained layers on semiconductor substrates
US20030227057A1 (en) * 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
US6995430B2 (en) * 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US7307273B2 (en) * 2002-06-07 2007-12-11 Amberwave Systems Corporation Control of strain in device layers by selective relaxation
US7335545B2 (en) * 2002-06-07 2008-02-26 Amberwave Systems Corporation Control of strain in device layers by prevention of relaxation
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US7358121B2 (en) * 2002-08-23 2008-04-15 Intel Corporation Tri-gate devices and methods of fabrication
US6946373B2 (en) * 2002-11-20 2005-09-20 International Business Machines Corporation Relaxed, low-defect SGOI for strained Si CMOS applications
FR2847715B1 (fr) * 2002-11-25 2005-03-11 Commissariat Energie Atomique Circuit integre comportant des sous-ensembles connectes en serie
US6717216B1 (en) * 2002-12-12 2004-04-06 International Business Machines Corporation SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device
US7157774B2 (en) * 2003-01-31 2007-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Strained silicon-on-insulator transistors with mesa isolation
US6870179B2 (en) * 2003-03-31 2005-03-22 Intel Corporation Increasing stress-enhanced drive current in a MOS transistor
US7081395B2 (en) * 2003-05-23 2006-07-25 Taiwan Semiconductor Manufacturing Co., Ltd. Silicon strain engineering accomplished via use of specific shallow trench isolation fill materials
US6909151B2 (en) * 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US7456476B2 (en) * 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US7105390B2 (en) * 2003-12-30 2006-09-12 Intel Corporation Nonplanar transistors with metal gate electrodes
US7268058B2 (en) * 2004-01-16 2007-09-11 Intel Corporation Tri-gate transistors and methods to fabricate same
US20050186722A1 (en) * 2004-02-25 2005-08-25 Kuan-Lun Cheng Method and structure for CMOS device with stress relaxed by ion implantation of carbon or oxygen containing ions
US7154118B2 (en) * 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US20050266632A1 (en) * 2004-05-26 2005-12-01 Yun-Hsiu Chen Integrated circuit with strained and non-strained transistors, and method of forming thereof
US7579280B2 (en) * 2004-06-01 2009-08-25 Intel Corporation Method of patterning a film
US7042009B2 (en) * 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
US6991998B2 (en) * 2004-07-02 2006-01-31 International Business Machines Corporation Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer
US7348284B2 (en) 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US7135372B2 (en) * 2004-09-09 2006-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Strained silicon device manufacturing method
US7071064B2 (en) * 2004-09-23 2006-07-04 Intel Corporation U-gate transistors and methods of fabrication
US7332439B2 (en) * 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US7422946B2 (en) * 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US7361958B2 (en) * 2004-09-30 2008-04-22 Intel Corporation Nonplanar transistors with metal gate electrodes
JP4603845B2 (ja) * 2004-10-12 2010-12-22 Okiセミコンダクタ株式会社 半導体装置の製造方法
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7306997B2 (en) * 2004-11-10 2007-12-11 Advanced Micro Devices, Inc. Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor
US7393733B2 (en) * 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
US20060113603A1 (en) * 2004-12-01 2006-06-01 Amberwave Systems Corporation Hybrid semiconductor-on-insulator structures and related methods
US7193279B2 (en) * 2005-01-18 2007-03-20 Intel Corporation Non-planar MOS structure with a strained channel region
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US20060202266A1 (en) * 2005-03-14 2006-09-14 Marko Radosavljevic Field effect transistor with metal source/drain regions
US7563701B2 (en) * 2005-03-31 2009-07-21 Intel Corporation Self-aligned contacts for transistors
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7547637B2 (en) * 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7279375B2 (en) * 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US7402875B2 (en) * 2005-08-17 2008-07-22 Intel Corporation Lateral undercut of metal gate in SOI device
US20070090416A1 (en) * 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
US7479421B2 (en) 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US20070090408A1 (en) * 2005-09-29 2007-04-26 Amlan Majumdar Narrow-body multiple-gate FET with dominant body transistor for high performance
US7759739B2 (en) * 2005-10-27 2010-07-20 International Business Machines Corporation Transistor with dielectric stressor elements
GB2445511B (en) * 2005-10-31 2009-04-08 Advanced Micro Devices Inc An embedded strain layer in thin soi transistors and a method of forming the same
DE102005052055B3 (de) 2005-10-31 2007-04-26 Advanced Micro Devices, Inc., Sunnyvale Eingebettete Verformungsschicht in dünnen SOI-Transistoren und Verfahren zur Herstellung desselben
US7485503B2 (en) 2005-11-30 2009-02-03 Intel Corporation Dielectric interface for group III-V semiconductor device
US7396711B2 (en) * 2005-12-27 2008-07-08 Intel Corporation Method of fabricating a multi-cornered film
US7449373B2 (en) * 2006-03-31 2008-11-11 Intel Corporation Method of ion implanting for tri-gate devices
US7670928B2 (en) * 2006-06-14 2010-03-02 Intel Corporation Ultra-thin oxide bonding for S1 to S1 dual orientation bonding
US7544594B2 (en) * 2006-06-28 2009-06-09 Intel Corporation Method of forming a transistor having gate protection and transistor formed according to the method
US8143646B2 (en) 2006-08-02 2012-03-27 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si
KR100835413B1 (ko) * 2006-12-05 2008-06-04 동부일렉트로닉스 주식회사 반도체 소자의 미세 비아홀 형성방법
US20080157225A1 (en) * 2006-12-29 2008-07-03 Suman Datta SRAM and logic transistors with variable height multi-gate transistor architecture
US8558278B2 (en) * 2007-01-16 2013-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Strained transistor with optimized drive current and method of forming
KR101052868B1 (ko) * 2008-02-29 2011-07-29 주식회사 하이닉스반도체 Soi 소자 및 그의 제조방법
US7943961B2 (en) * 2008-03-13 2011-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Strain bars in stressed layers of MOS devices
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US20100019322A1 (en) * 2008-07-23 2010-01-28 International Business Machines Corporation Semiconductor device and method of manufacturing
US7808051B2 (en) * 2008-09-29 2010-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Standard cell without OD space effect in Y-direction
CN102024706B (zh) * 2009-09-22 2012-06-20 中芯国际集成电路制造(上海)有限公司 用于制造半导体器件的方法
US8258031B2 (en) * 2010-06-15 2012-09-04 International Business Machines Corporation Fabrication of a vertical heterojunction tunnel-FET
US9406798B2 (en) * 2010-08-27 2016-08-02 Acorn Technologies, Inc. Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer
JP6005364B2 (ja) * 2012-02-06 2016-10-12 ラピスセミコンダクタ株式会社 半導体装置の製造方法及び半導体装置
US9515181B2 (en) 2014-08-06 2016-12-06 Qualcomm Incorporated Semiconductor device with self-aligned back side features
JP6559745B2 (ja) 2017-08-23 2019-08-14 株式会社東芝 半導体デバイス検査装置、半導体デバイス検査方法、そのプログラム、半導体装置およびその製造方法
JP2018032877A (ja) * 2017-11-29 2018-03-01 ラピスセミコンダクタ株式会社 半導体装置
JP2019125747A (ja) 2018-01-18 2019-07-25 株式会社東芝 半導体装置およびその製造方法
KR102396978B1 (ko) * 2018-11-16 2022-05-11 삼성전자주식회사 반도체 장치

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1154756A (ja) * 1997-07-30 1999-02-26 Internatl Business Mach Corp <Ibm> 絶縁体上の半導体のキャリア移動度を強化する構造
JP2000294623A (ja) * 1999-04-02 2000-10-20 Fuji Electric Co Ltd 誘電体分離基板の製造方法
JP2000332099A (ja) * 1999-05-21 2000-11-30 Matsushita Electronics Industry Corp 半導体装置およびその製造方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4604162A (en) * 1983-06-13 1986-08-05 Ncr Corporation Formation and planarization of silicon-on-insulator structures
US5270265A (en) * 1992-09-01 1993-12-14 Harris Corporation Stress relief technique of removing oxide from surface of trench-patterned semiconductor-on-insulator structure
US5561302A (en) 1994-09-26 1996-10-01 Motorola, Inc. Enhanced mobility MOSFET device and method
US5811283A (en) * 1996-08-13 1998-09-22 United Microelectronics Corporation Silicon on insulator (SOI) dram cell structure and process
US6211039B1 (en) 1996-11-12 2001-04-03 Micron Technology, Inc. Silicon-on-insulator islands and method for their formation
US6045625A (en) * 1996-12-06 2000-04-04 Texas Instruments Incorporated Buried oxide with a thermal expansion matching layer for SOI
GB2327146A (en) * 1997-07-10 1999-01-13 Ericsson Telefon Ab L M Thermal insulation of integrated circuit components
US6054343A (en) * 1998-01-26 2000-04-25 Texas Instruments Incorporated Nitride trench fill process for increasing shallow trench isolation (STI) robustness
US6245600B1 (en) * 1999-07-01 2001-06-12 International Business Machines Corporation Method and structure for SOI wafers to avoid electrostatic discharge
US6573565B2 (en) * 1999-07-28 2003-06-03 International Business Machines Corporation Method and structure for providing improved thermal conduction for silicon semiconductor devices
US6426252B1 (en) * 1999-10-25 2002-07-30 International Business Machines Corporation Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap
US20020046985A1 (en) * 2000-03-24 2002-04-25 Daneman Michael J. Process for creating an electrically isolated electrode on a sidewall of a cavity in a base
US6403482B1 (en) * 2000-06-28 2002-06-11 International Business Machines Corporation Self-aligned junction isolation
TW501227B (en) * 2000-08-11 2002-09-01 Samsung Electronics Co Ltd SOI MOSFET having body contact for preventing floating body effect and method of fabricating the same
DE10040464A1 (de) * 2000-08-18 2002-02-28 Infineon Technologies Ag Grabenkondensator und Verfahren zu seiner Herstellung
JP2002076336A (ja) * 2000-09-01 2002-03-15 Mitsubishi Electric Corp 半導体装置およびsoi基板
GB0022329D0 (en) * 2000-09-12 2000-10-25 Mitel Semiconductor Ltd Semiconductor device
DE10054109C2 (de) * 2000-10-31 2003-07-10 Advanced Micro Devices Inc Verfahren zum Bilden eines Substratkontakts in einem Feldeffekttransistor, der über einer vergrabenen Isolierschicht gebildet ist
US6506620B1 (en) * 2000-11-27 2003-01-14 Microscan Systems Incorporated Process for manufacturing micromechanical and microoptomechanical structures with backside metalization
US6524929B1 (en) * 2001-02-26 2003-02-25 Advanced Micro Devices, Inc. Method for shallow trench isolation using passivation material for trench bottom liner

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1154756A (ja) * 1997-07-30 1999-02-26 Internatl Business Mach Corp <Ibm> 絶縁体上の半導体のキャリア移動度を強化する構造
JP2000294623A (ja) * 1999-04-02 2000-10-20 Fuji Electric Co Ltd 誘電体分離基板の製造方法
JP2000332099A (ja) * 1999-05-21 2000-11-30 Matsushita Electronics Industry Corp 半導体装置およびその製造方法

Also Published As

Publication number Publication date
WO2004001798A2 (en) 2003-12-31
TWI289895B (en) 2007-11-11
CN1659696A (zh) 2005-08-24
TW200400564A (en) 2004-01-01
JP4452883B2 (ja) 2010-04-21
KR20050013248A (ko) 2005-02-03
WO2004001798A3 (en) 2004-07-29
EP1516362A2 (en) 2005-03-23
JP2005531144A (ja) 2005-10-13
AU2003238916A8 (en) 2004-01-06
US20040018668A1 (en) 2004-01-29
AU2003238916A1 (en) 2004-01-06
US6680240B1 (en) 2004-01-20
CN1333454C (zh) 2007-08-22

Similar Documents

Publication Publication Date Title
KR100996725B1 (ko) 변형된 디바이스 막을 구비한 실리콘-온-절연체 디바이스및 절연 산화물을 부분적으로 대체하여 상기 디바이스를생성하는 방법
KR100340878B1 (ko) 에스오아이 소자의 제조방법
US6787423B1 (en) Strained-silicon semiconductor device
US6611023B1 (en) Field effect transistor with self alligned double gate and method of forming same
US7906381B2 (en) Method for integrating silicon-on-nothing devices with standard CMOS devices
US6949420B1 (en) Silicon-on-insulator (SOI) substrate having dual surface crystallographic orientations and method of forming same
US6551944B1 (en) Process for manufacturing a semiconductor material wafer comprising single-Crystal regions separated by insulating material regions
KR101340634B1 (ko) Soi 트랜지스터와 벌크 트랜지스터를 포함하여 구성된 반도체 디바이스 및 이것을 형성하는 방법
EP1927133A2 (en) Method of manufacturing a semiconductor device with an isolation region and a device manufactured by the method
US6617202B2 (en) Method for fabricating a full depletion type SOI device
KR100296130B1 (ko) 이중막 실리콘웨이퍼를 이용한 금속-산화막-반도체 전계효과트랜지스터 제조방법
US6642536B1 (en) Hybrid silicon on insulator/bulk strained silicon technology
JP2012501078A (ja) アクティブ層の厚み減少を伴う歪トランジスタを形成するための構造歪を与えられた基板
TW202044359A (zh) 半導體結構及其製造方法
JP2008041901A (ja) 半導体装置及びその製造方法
KR100374227B1 (ko) 반도체소자의 제조방법
KR100886708B1 (ko) Soi 소자 및 그의 제조방법
KR100319615B1 (ko) 반도체 장치에서의 소자격리방법
KR100263475B1 (ko) 반도체 소자의 구조 및 제조 방법
KR100356793B1 (ko) 비씨-에스오아이 소자의 제조방법
KR100815058B1 (ko) 셀로우 트랜치 소자분리영역 내부의 soi 형성방법 및구조
KR100333377B1 (ko) 채널 포위형 게이트 구조를 갖는 이중막 실리콘 소자의 제조 방법
WO2024237933A1 (en) Memory device formed on silicon-on-insulator substrate, and method of making same
JPH01214064A (ja) 絶縁ゲート電界効果トランジスタおよびその製造方法
KR100833594B1 (ko) 모스펫 소자 및 그 제조방법

Legal Events

Date Code Title Description
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

N231 Notification of change of applicant
PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

FPAY Annual fee payment

Payment date: 20131101

Year of fee payment: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

FPAY Annual fee payment

Payment date: 20141107

Year of fee payment: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

FPAY Annual fee payment

Payment date: 20151016

Year of fee payment: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

FPAY Annual fee payment

Payment date: 20161019

Year of fee payment: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

FPAY Annual fee payment

Payment date: 20171018

Year of fee payment: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20181120

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20181120