JP2005531144A - 絶縁酸化物が部分的に置換されたひずみデバイス膜を備えたシリコンオンインシュレータデバイス及びその製造方法 - Google Patents
絶縁酸化物が部分的に置換されたひずみデバイス膜を備えたシリコンオンインシュレータデバイス及びその製造方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 26
- 238000004519 manufacturing process Methods 0.000 title description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 71
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 71
- 239000010703 silicon Substances 0.000 claims abstract description 71
- 239000000463 material Substances 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims description 25
- 230000008569 process Effects 0.000 claims description 9
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000000969 carrier Substances 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 18
- 108091006146 Channels Proteins 0.000 description 7
- 239000002243 precursor Substances 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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- 238000007796 conventional method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
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- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76281—Lateral isolation by selective oxidation of silicon
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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Abstract
Description
Claims (10)
- 基板(10)、前記基板(10)上の埋め込み酸化層(12)、及び前記埋め込み酸化層(12)上のシリコン層(14)を備えたシリコンオンインシュレータ(SOI)構造における埋め込み層(12)にリセス部(22)をエッチングするステップを有し、前記シリコン層(14)はトレンチ(16)を有し、前記埋め込み層への前記リセス部(22)のエッチングでは、前記シリコン層(14)に前記トレンチ(16)を貫通してエッチングがなされ、
前記埋め込み層(12)及び前記トレンチ(16)の前記リセス部(22)に、前記シリコン層(14)に実質的にひずみ量を導入する材料(24)を充填するステップを有する、
ひずみデバイス膜の形成方法。 - 前記リセス部(22)をエッチングする前記ステップは、シリコン層の下にアンダーカット(20)エッチングする過程を含む、
請求項1記載の方法。 - 前記リセス部(22)をエッチングする前記ステップは、前記埋め込み酸化層(12)を等方性エッチングする過程を含む、
請求項2記載の方法。 - 前記材料(24)は、窒化物である、
請求項3記載の方法。 - 前記リセス部(22)は、トレンチ(16)においてのみエッチングされ、埋め込み酸化層(12)においてはエッチングされない、
請求項1記載の方法。 - 基板(10)を有し、
前記基板上の埋め込み酸化層(12)を有し、
前記埋め込み酸化層(12)上のシリコン島(18)を有し、このシリコン島(18)は、互いに間隙部(16)によって絶縁され、前記埋め込み酸化層(12)は、前記間隙部(16)の直下にリセス部(22)を備えるものであり、
前記リセス部(22)と前記間隙部(16)を充填する材料を含み、前記材料は、前記シリコン島(18)に実質的にひずみ量を導入するものである、
ひずみシリコン膜を備えたシリコンオンインシュレータ(SOI)デバイス。 - 更に、前記シリコン島(18)上に半導体デバイス(26)を含む、
請求項6記載のSOIデバイス。 - 前記材料(24)は、窒化物である、
請求項6記載のSOIデバイス。 - 前記リセス部(22)は、前記間隙部の直下の第一部分と、前記シリコン島(18)の下方の第二部分を含む、
請求項6記載のSOIデバイス。 - 前記リセス部(22)は、前記シリコン島(18)の下方に伸長している前記埋め込み酸化層(12)にアンダーカット領域(20)を含む、
請求項6記載のSOIデバイス。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/178,542 US6680240B1 (en) | 2002-06-25 | 2002-06-25 | Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide |
PCT/US2003/017824 WO2004001798A2 (en) | 2002-06-25 | 2003-06-04 | A silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide |
Publications (3)
Publication Number | Publication Date |
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JP2005531144A true JP2005531144A (ja) | 2005-10-13 |
JP2005531144A5 JP2005531144A5 (ja) | 2006-07-20 |
JP4452883B2 JP4452883B2 (ja) | 2010-04-21 |
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Application Number | Title | Priority Date | Filing Date |
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JP2004515743A Expired - Fee Related JP4452883B2 (ja) | 2002-06-25 | 2003-06-04 | 絶縁酸化物が部分的に置換されたひずみデバイス膜を備えたシリコンオンインシュレータデバイス及びその製造方法 |
Country Status (8)
Country | Link |
---|---|
US (1) | US6680240B1 (ja) |
EP (1) | EP1516362A2 (ja) |
JP (1) | JP4452883B2 (ja) |
KR (1) | KR100996725B1 (ja) |
CN (1) | CN1333454C (ja) |
AU (1) | AU2003238916A1 (ja) |
TW (1) | TWI289895B (ja) |
WO (1) | WO2004001798A2 (ja) |
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- 2003-06-04 AU AU2003238916A patent/AU2003238916A1/en not_active Abandoned
- 2003-06-04 EP EP03734436A patent/EP1516362A2/en not_active Withdrawn
- 2003-06-04 KR KR1020047021192A patent/KR100996725B1/ko not_active IP Right Cessation
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JP2013161966A (ja) * | 2012-02-06 | 2013-08-19 | Lapis Semiconductor Co Ltd | 半導体装置の製造方法及び半導体装置 |
US11156654B2 (en) | 2017-08-23 | 2021-10-26 | Kabushiki Kaisha Toshiba | Semiconductor device inspection apparatus, semiconductor device inspection method, program thereof, semiconductor apparatus, and manufacturing method therefor |
JP2018032877A (ja) * | 2017-11-29 | 2018-03-01 | ラピスセミコンダクタ株式会社 | 半導体装置 |
US10847620B2 (en) | 2018-01-18 | 2020-11-24 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
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AU2003238916A8 (en) | 2004-01-06 |
TWI289895B (en) | 2007-11-11 |
US6680240B1 (en) | 2004-01-20 |
US20040018668A1 (en) | 2004-01-29 |
JP4452883B2 (ja) | 2010-04-21 |
CN1659696A (zh) | 2005-08-24 |
AU2003238916A1 (en) | 2004-01-06 |
KR20050013248A (ko) | 2005-02-03 |
WO2004001798A2 (en) | 2003-12-31 |
CN1333454C (zh) | 2007-08-22 |
TW200400564A (en) | 2004-01-01 |
EP1516362A2 (en) | 2005-03-23 |
WO2004001798A3 (en) | 2004-07-29 |
KR100996725B1 (ko) | 2010-11-25 |
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