KR100930556B1 - 반도체 장치 및 그 제조 방법 - Google Patents
반도체 장치 및 그 제조 방법 Download PDFInfo
- Publication number
- KR100930556B1 KR100930556B1 KR1020030035584A KR20030035584A KR100930556B1 KR 100930556 B1 KR100930556 B1 KR 100930556B1 KR 1020030035584 A KR1020030035584 A KR 1020030035584A KR 20030035584 A KR20030035584 A KR 20030035584A KR 100930556 B1 KR100930556 B1 KR 100930556B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- pattern
- barrier metal
- metal film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
- H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/564—Details not otherwise provided for, e.g. protection against moisture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
- H01L2221/1015—Forming openings in dielectrics for dual damascene structures
- H01L2221/1036—Dual damascene with different via-level and trench-level dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JPJP-P-2002-00165818 | 2002-06-06 | ||
| JP2002165818 | 2002-06-06 | ||
| JP2003076962A JP4250006B2 (ja) | 2002-06-06 | 2003-03-20 | 半導体装置及びその製造方法 |
| JPJP-P-2003-00076962 | 2003-03-20 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020090067257A Division KR100964263B1 (ko) | 2002-06-06 | 2009-07-23 | 반도체 장치 및 그 제조 방법 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20030095245A KR20030095245A (ko) | 2003-12-18 |
| KR100930556B1 true KR100930556B1 (ko) | 2009-12-09 |
Family
ID=29714357
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020030035584A Expired - Fee Related KR100930556B1 (ko) | 2002-06-06 | 2003-06-03 | 반도체 장치 및 그 제조 방법 |
| KR1020090067257A Expired - Fee Related KR100964263B1 (ko) | 2002-06-06 | 2009-07-23 | 반도체 장치 및 그 제조 방법 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020090067257A Expired - Fee Related KR100964263B1 (ko) | 2002-06-06 | 2009-07-23 | 반도체 장치 및 그 제조 방법 |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US7119439B2 (enExample) |
| JP (1) | JP4250006B2 (enExample) |
| KR (2) | KR100930556B1 (enExample) |
| CN (1) | CN1290186C (enExample) |
| TW (1) | TWI296434B (enExample) |
Families Citing this family (47)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4360881B2 (ja) * | 2003-03-24 | 2009-11-11 | Necエレクトロニクス株式会社 | 多層配線を含む半導体装置およびその製造方法 |
| US20040245636A1 (en) * | 2003-06-06 | 2004-12-09 | International Business Machines Corporation | Full removal of dual damascene metal level |
| US7387960B2 (en) * | 2003-09-16 | 2008-06-17 | Texas Instruments Incorporated | Dual depth trench termination method for improving Cu-based interconnect integrity |
| WO2005034234A1 (ja) * | 2003-10-02 | 2005-04-14 | Fujitsu Limited | 半導体装置及びその製造方法 |
| JP2005136215A (ja) * | 2003-10-30 | 2005-05-26 | Toshiba Corp | 半導体装置 |
| JP2005142262A (ja) * | 2003-11-05 | 2005-06-02 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
| JP4946436B2 (ja) * | 2004-03-31 | 2012-06-06 | 日本電気株式会社 | 半導体装置及びその製造方法 |
| JP4603281B2 (ja) | 2004-03-31 | 2010-12-22 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP4280204B2 (ja) | 2004-06-15 | 2009-06-17 | Okiセミコンダクタ株式会社 | 半導体装置 |
| JP2006073891A (ja) * | 2004-09-03 | 2006-03-16 | Renesas Technology Corp | 半導体装置及び半導体装置の製造方法 |
| US7777338B2 (en) * | 2004-09-13 | 2010-08-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Seal ring structure for integrated circuit chips |
| US7125791B2 (en) * | 2004-10-12 | 2006-10-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Advanced copper damascene structure |
| US20060202336A1 (en) | 2005-02-25 | 2006-09-14 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating a semiconductor device |
| US7479447B2 (en) * | 2005-04-04 | 2009-01-20 | International Business Machines Corporation | Method of forming a crack stop void in a low-k dielectric layer between adjacent fuses |
| JP2007012996A (ja) * | 2005-07-01 | 2007-01-18 | Toshiba Corp | 半導体装置 |
| JP2007019188A (ja) | 2005-07-06 | 2007-01-25 | Renesas Technology Corp | 半導体集積回路装置およびその製造方法 |
| JP4282646B2 (ja) * | 2005-09-09 | 2009-06-24 | 株式会社東芝 | 半導体装置の製造方法 |
| JP4699172B2 (ja) * | 2005-10-25 | 2011-06-08 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US7449785B2 (en) * | 2006-02-06 | 2008-11-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Solder bump on a semiconductor substrate |
| JP2008016638A (ja) * | 2006-07-06 | 2008-01-24 | Sony Corp | 半導体装置 |
| JP4864608B2 (ja) * | 2006-08-28 | 2012-02-01 | 東京エレクトロン株式会社 | 課金方法、記憶媒体及び半導体デバイス製造装置 |
| JP4506767B2 (ja) * | 2007-02-28 | 2010-07-21 | カシオ計算機株式会社 | 半導体装置の製造方法 |
| KR100995558B1 (ko) | 2007-03-22 | 2010-11-22 | 후지쯔 세미컨덕터 가부시키가이샤 | 반도체 장치 및 반도체 장치의 제조 방법 |
| JP5332200B2 (ja) * | 2007-03-22 | 2013-11-06 | 富士通セミコンダクター株式会社 | 半導体装置及び半導体装置の製造方法 |
| JP5365514B2 (ja) * | 2007-03-30 | 2013-12-11 | 富士通セミコンダクター株式会社 | 半導体装置およびその製造方法 |
| JP5117791B2 (ja) * | 2007-08-22 | 2013-01-16 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP2009076782A (ja) * | 2007-09-21 | 2009-04-09 | Sharp Corp | 半導体基板、その製造方法、および半導体チップ |
| JP2009088269A (ja) * | 2007-09-28 | 2009-04-23 | Toshiba Corp | 半導体装置、およびその製造方法 |
| JP2009135139A (ja) * | 2007-11-28 | 2009-06-18 | Toshiba Corp | 半導体装置及びその製造方法 |
| US7704804B2 (en) | 2007-12-10 | 2010-04-27 | International Business Machines Corporation | Method of forming a crack stop laser fuse with fixed passivation layer coverage |
| US7956466B2 (en) | 2008-05-09 | 2011-06-07 | International Business Machines Corporation | Structure for interconnect structure containing various capping materials for electrical fuse and other related applications |
| US8772156B2 (en) * | 2008-05-09 | 2014-07-08 | International Business Machines Corporation | Methods of fabricating interconnect structures containing various capping materials for electrical fuse and other related applications |
| JP2010153543A (ja) * | 2008-12-25 | 2010-07-08 | Fujitsu Ltd | 半導体装置およびその製造方法 |
| US7892926B2 (en) | 2009-07-24 | 2011-02-22 | International Business Machines Corporation | Fuse link structures using film stress for programming and methods of manufacture |
| US8124448B2 (en) | 2009-09-18 | 2012-02-28 | Advanced Micro Devices, Inc. | Semiconductor chip with crack deflection structure |
| US8592941B2 (en) | 2010-07-19 | 2013-11-26 | International Business Machines Corporation | Fuse structure having crack stop void, method for forming and programming same, and design structure |
| CN103185998B (zh) * | 2011-12-30 | 2015-07-15 | 上海天马微电子有限公司 | 非晶硅栅极驱动线路的形成方法及液晶显示器形成方法 |
| JP5834934B2 (ja) | 2012-01-17 | 2015-12-24 | 富士通セミコンダクター株式会社 | 半導体装置及び半導体装置の製造方法 |
| US8906801B2 (en) * | 2012-03-12 | 2014-12-09 | GlobalFoundries, Inc. | Processes for forming integrated circuits and integrated circuits formed thereby |
| JP5504311B2 (ja) * | 2012-08-06 | 2014-05-28 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| US8916461B2 (en) | 2012-09-20 | 2014-12-23 | International Business Machines Corporation | Electronic fuse vias in interconnect structures |
| TWI495074B (zh) | 2012-11-30 | 2015-08-01 | 財團法人工業技術研究院 | 減能結構 |
| US9691719B2 (en) * | 2013-01-11 | 2017-06-27 | Renesas Electronics Corporation | Semiconductor device |
| JP2016018879A (ja) * | 2014-07-08 | 2016-02-01 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
| US10461149B1 (en) | 2018-06-28 | 2019-10-29 | Micron Technology, Inc. | Elevationally-elongated conductive structure of integrated circuitry, method of forming an array of capacitors, method of forming DRAM circuitry, and method of forming an elevationally-elongated conductive structure of integrated circuitry |
| US10475796B1 (en) * | 2018-06-28 | 2019-11-12 | Micron Technology, Inc. | Method of forming an array of capacitors, a method of forming DRAM circuitry, and a method of forming an elevationally-elongated conductive structure of integrated circuitry |
| US11373962B2 (en) | 2020-08-14 | 2022-06-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Advanced seal ring structure and method of making the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990078156A (ko) * | 1998-03-24 | 1999-10-25 | 아끼구사 나오유끼 | 반도체장치 및 그 제조방법 |
| KR19990083622A (ko) * | 1998-04-30 | 1999-11-25 | 카네코 히사시 | 배선구조의형성방법 |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6291891B1 (en) * | 1998-01-13 | 2001-09-18 | Kabushiki Kaisha Toshiba | Semiconductor device manufacturing method and semiconductor device |
| JP3293792B2 (ja) | 1999-01-12 | 2002-06-17 | 日本電気株式会社 | 半導体装置及びその製造方法 |
| JP4108228B2 (ja) | 1999-07-15 | 2008-06-25 | 富士通株式会社 | 半導体装置の製造方法 |
| JP4192348B2 (ja) | 1999-08-09 | 2008-12-10 | 株式会社デンソー | 半導体装置 |
| US6566258B1 (en) | 2000-05-10 | 2003-05-20 | Applied Materials, Inc. | Bi-layer etch stop for inter-level via |
| US6362524B1 (en) * | 2000-07-26 | 2002-03-26 | Advanced Micro Devices, Inc. | Edge seal ring for copper damascene process and method for fabrication thereof |
| JP2002076114A (ja) | 2000-08-30 | 2002-03-15 | Hitachi Ltd | 半導体装置の製造方法 |
| JP4118029B2 (ja) * | 2001-03-09 | 2008-07-16 | 富士通株式会社 | 半導体集積回路装置とその製造方法 |
| JP4523194B2 (ja) * | 2001-04-13 | 2010-08-11 | 富士通セミコンダクター株式会社 | 半導体装置とその製造方法 |
| US6566171B1 (en) * | 2001-06-12 | 2003-05-20 | Lsi Logic Corporation | Fuse construction for integrated circuit structure having low dielectric constant dielectric material |
| JP4948715B2 (ja) * | 2001-06-29 | 2012-06-06 | 富士通セミコンダクター株式会社 | 半導体ウエハ装置およびその製造方法 |
| JP2003115535A (ja) * | 2001-10-04 | 2003-04-18 | Hitachi Ltd | 半導体集積回路装置 |
| JP3757143B2 (ja) * | 2001-10-11 | 2006-03-22 | 富士通株式会社 | 半導体装置の製造方法及び半導体装置 |
| US6734090B2 (en) * | 2002-02-20 | 2004-05-11 | International Business Machines Corporation | Method of making an edge seal for a semiconductor device |
| JP3813562B2 (ja) * | 2002-03-15 | 2006-08-23 | 富士通株式会社 | 半導体装置及びその製造方法 |
| JP4088120B2 (ja) * | 2002-08-12 | 2008-05-21 | 株式会社ルネサステクノロジ | 半導体装置 |
-
2003
- 2003-03-20 JP JP2003076962A patent/JP4250006B2/ja not_active Expired - Fee Related
- 2003-06-03 KR KR1020030035584A patent/KR100930556B1/ko not_active Expired - Fee Related
- 2003-06-05 TW TW092115253A patent/TWI296434B/zh not_active IP Right Cessation
- 2003-06-05 US US10/454,667 patent/US7119439B2/en not_active Expired - Lifetime
- 2003-06-06 CN CNB031424244A patent/CN1290186C/zh not_active Expired - Fee Related
-
2004
- 2004-09-24 US US10/948,569 patent/US7241676B2/en not_active Expired - Lifetime
-
2009
- 2009-07-23 KR KR1020090067257A patent/KR100964263B1/ko not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990078156A (ko) * | 1998-03-24 | 1999-10-25 | 아끼구사 나오유끼 | 반도체장치 및 그 제조방법 |
| KR19990083622A (ko) * | 1998-04-30 | 1999-11-25 | 카네코 히사시 | 배선구조의형성방법 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2004064046A (ja) | 2004-02-26 |
| US20050042816A1 (en) | 2005-02-24 |
| US20030227089A1 (en) | 2003-12-11 |
| JP4250006B2 (ja) | 2009-04-08 |
| TWI296434B (en) | 2008-05-01 |
| CN1290186C (zh) | 2006-12-13 |
| KR20090094204A (ko) | 2009-09-04 |
| CN1467837A (zh) | 2004-01-14 |
| KR100964263B1 (ko) | 2010-06-16 |
| US7119439B2 (en) | 2006-10-10 |
| TW200401403A (en) | 2004-01-16 |
| KR20030095245A (ko) | 2003-12-18 |
| US7241676B2 (en) | 2007-07-10 |
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