KR100730326B1 - 비어 홀을 충전하는 도금 방법 - Google Patents
비어 홀을 충전하는 도금 방법 Download PDFInfo
- Publication number
- KR100730326B1 KR100730326B1 KR20010004601A KR20010004601A KR100730326B1 KR 100730326 B1 KR100730326 B1 KR 100730326B1 KR 20010004601 A KR20010004601 A KR 20010004601A KR 20010004601 A KR20010004601 A KR 20010004601A KR 100730326 B1 KR100730326 B1 KR 100730326B1
- Authority
- KR
- South Korea
- Prior art keywords
- plating
- copper
- via hole
- substrate
- promoter
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/12—Semiconductors
- C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/18—Electroplating using modulated, pulsed or reversing current
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/34—Pretreatment of metallic surfaces to be electroplated
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S205/00—Electrolysis: processes, compositions used therein, and methods of preparing the compositions
- Y10S205/917—Treatment of workpiece between coating steps
Abstract
Description
Claims (11)
- 비어 홀(via hole)을 충전하는 도금 방법으로서, 기판을 덮는 절연층에 형성되어 기판 상에 위치한 도체층의 부분을 하부에서 노출시키는 각각의 비어 홀이 구리로 도금되어 도금된 금속으로 충전되는 비어 홀 충전 도금 방법에 있어서,상기 기판을 덮는 상기 절연층의 상면, 및 상기 각 비어 홀의 측벽과 하부 상에 구리막을 형성하는 과정과,상기 구리막의 상기 표면에 구리의 스트라이크 도금(strike plating)을 형성하는 과정과,상기 구리막과 그 위에 형성된 구리 스트라이크 도금을 갖는 상기 기판을 도금 촉진제를 함유하는 수용액 내에 담금으로써 상기 구리 스트라이크 도금의 표면 상에 상기 도금 촉진제를 퇴적시키는 과정과,상기 각 비어 홀의 상기 측벽과 하부 상에 상기 도금 촉진제를 남기고 상기 절연층 상면에 위치한 상기 구리 스트라이크 도금의 표면으로부터 상기 도금 촉진제를 제거하는 과정과,상기 구리막과 상기 구리 스트라이크 도금을 갖는 상기 기판을 구리로 전기 도금함으로써 상기 비아 홀을 상기 도금된 구리로 충전하고 동시에 상기 도금된 구리로 충전된 상기 비아 홀뿐만 아니라 상기 절연층의 상기 상면에 이전에 형성된 상기 구리 스트라이크를 평탄하게 덮는 연속적인 구리막을 형성하는 과정을 포함하는 것을 특징으로 하는 비어 홀 충전 도금 방법.
- 제 2항에 있어서,상기 황 화합물은 소듐 3-머캅토-1-프로판설포네이트, 소듐 2-머캅토에탄설포네이트, 및 디소듐 비스-(3-설포프로필)-디설파이드로 이루어진 군에서 선택되는 것을 특징으로 하는 비어 홀 충전 도금 방법.
- 제 1항에 있어서,상기 도금 촉진제를 함유하는 수용액은 비이온 계면 활성제를 더 포함하는 것을 특징으로 하는 비어 홀 충전 도금 방법.
- 제 4항에 있어서,상기 비이온 계면 활성제는 폴리에틸렌 글리콜 또는 폴리프로필렌 글리콜인 것을 특징으로 하는 비어 홀 충전 도금 방법.
- 제 1항에 있어서,상기 도금 촉진제는, (1) 구리용 에칭 용액을 사용하는 에칭 공정, (2) 시아나이드 전해조(electrolytic bath)를 사용하는 시아나이드 전해 처리, (3) 상기 절연층 상의 상기 구리 스트라이크 도금을 자외선 방사로 비스듬히 조사하는 자외선 방사 처리, 및 (4) 상기 절연층 상부의 상기 구리 스트라이크 도금을 연마하는 처리로 구성되는 그룹으로부터 프로세스 또는 선택된 처리에 의해 제거되는 것을 특징으로 하는 비어 홀 충전 도금 방법.
- 삭제
- 삭제
- 제 1항에 있어서,상기 구리로 상기 전기 도금하는 과정은 도금 촉진제가 없는 전기 도금 용액을 사용하여 이행되는 것을 특징으로 하는 비어 홀 충전 도금 방법.
- 삭제
- 삭제
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000-23794 | 2000-02-01 | ||
JP2000023794 | 2000-02-01 | ||
JP2000-334044 | 2000-11-01 | ||
JP2000334044A JP3594894B2 (ja) | 2000-02-01 | 2000-11-01 | ビアフィリングめっき方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20010078217A KR20010078217A (ko) | 2001-08-20 |
KR100730326B1 true KR100730326B1 (ko) | 2007-06-19 |
Family
ID=26584623
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR20010004601A KR100730326B1 (ko) | 2000-02-01 | 2001-01-31 | 비어 홀을 충전하는 도금 방법 |
Country Status (6)
Country | Link |
---|---|
US (1) | US6755957B2 (ko) |
EP (1) | EP1122989B1 (ko) |
JP (1) | JP3594894B2 (ko) |
KR (1) | KR100730326B1 (ko) |
DE (1) | DE60126853T2 (ko) |
TW (1) | TW574438B (ko) |
Cited By (1)
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---|---|---|---|---|
KR102254649B1 (ko) | 2020-04-14 | 2021-05-24 | 주식회사 디에이피 | 인쇄회로기판의 전기 동도금 방법 |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7449098B1 (en) | 1999-10-05 | 2008-11-11 | Novellus Systems, Inc. | Method for planar electroplating |
US7531079B1 (en) | 1998-10-26 | 2009-05-12 | Novellus Systems, Inc. | Method and apparatus for uniform electropolishing of damascene IC structures by selective agitation |
US6534116B2 (en) | 2000-08-10 | 2003-03-18 | Nutool, Inc. | Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence |
US6491806B1 (en) | 2000-04-27 | 2002-12-10 | Intel Corporation | Electroplating bath composition |
US6921551B2 (en) | 2000-08-10 | 2005-07-26 | Asm Nutool, Inc. | Plating method and apparatus for controlling deposition on predetermined portions of a workpiece |
US6858121B2 (en) * | 2000-08-10 | 2005-02-22 | Nutool, Inc. | Method and apparatus for filling low aspect ratio cavities with conductive material at high rate |
EP1307905A2 (en) * | 2000-08-10 | 2003-05-07 | Nutool, Inc. | Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence |
US6863795B2 (en) * | 2001-03-23 | 2005-03-08 | Interuniversitair Microelektronica Centrum (Imec) | Multi-step method for metal deposition |
JP4000796B2 (ja) * | 2001-08-08 | 2007-10-31 | 株式会社豊田自動織機 | ビアホールの銅メッキ方法 |
KR20040045390A (ko) * | 2001-10-16 | 2004-06-01 | 신꼬오덴기 고교 가부시키가이샤 | 소경홀의 구리 도금 방법 |
JP2003168860A (ja) * | 2001-11-30 | 2003-06-13 | Cmk Corp | プリント配線板及びその製造方法 |
JP3976564B2 (ja) * | 2001-12-20 | 2007-09-19 | 日本リーロナール有限会社 | ビアフィリング方法 |
JP3964263B2 (ja) * | 2002-05-17 | 2007-08-22 | 株式会社デンソー | ブラインドビアホール充填方法及び貫通電極形成方法 |
US7799200B1 (en) | 2002-07-29 | 2010-09-21 | Novellus Systems, Inc. | Selective electrochemical accelerator removal |
US7405163B1 (en) * | 2003-12-17 | 2008-07-29 | Novellus Systems, Inc. | Selectively accelerated plating of metal features |
US7449099B1 (en) * | 2004-04-13 | 2008-11-11 | Novellus Systems, Inc. | Selectively accelerated plating of metal features |
JP2004342750A (ja) | 2003-05-14 | 2004-12-02 | Toshiba Corp | 電子デバイスの製造方法 |
US8530359B2 (en) | 2003-10-20 | 2013-09-10 | Novellus Systems, Inc. | Modulated metal removal using localized wet etching |
US8158532B2 (en) * | 2003-10-20 | 2012-04-17 | Novellus Systems, Inc. | Topography reduction and control by selective accelerator removal |
DE102004005300A1 (de) * | 2004-01-29 | 2005-09-08 | Atotech Deutschland Gmbh | Verfahren zum Behandeln von Trägermaterial zur Herstellung von Schltungsträgern und Anwendung des Verfahrens |
US20050224358A1 (en) * | 2004-03-30 | 2005-10-13 | Lsi Logic Corporation | Method for improved local planarity control during electropolishing |
JP4150930B2 (ja) * | 2004-10-21 | 2008-09-17 | 日立電線株式会社 | 半導体装置用両面配線テープキャリアの製造方法 |
CN101189921A (zh) * | 2005-06-01 | 2008-05-28 | 松下电器产业株式会社 | 电路基板和其制造方法以及使用该电路基板的电子部件 |
US7550070B2 (en) | 2006-02-03 | 2009-06-23 | Novellus Systems, Inc. | Electrode and pad assembly for processing conductive layers |
JP4759416B2 (ja) * | 2006-03-20 | 2011-08-31 | 新光電気工業株式会社 | 非シアン無電解金めっき液及び無電解金めっき方法 |
US7405154B2 (en) * | 2006-03-24 | 2008-07-29 | International Business Machines Corporation | Structure and method of forming electrodeposited contacts |
US7575666B2 (en) * | 2006-04-05 | 2009-08-18 | James Watkowski | Process for electrolytically plating copper |
JP4862508B2 (ja) * | 2006-06-12 | 2012-01-25 | 日立電線株式会社 | 導体パターン形成方法 |
US8500985B2 (en) | 2006-07-21 | 2013-08-06 | Novellus Systems, Inc. | Photoresist-free metal deposition |
US7732329B2 (en) | 2006-08-30 | 2010-06-08 | Ipgrip, Llc | Method and apparatus for workpiece surface modification for selective material deposition |
US20080148561A1 (en) * | 2006-12-22 | 2008-06-26 | Motorola, Inc. | Methods for making printed wiring boards |
KR100832705B1 (ko) * | 2006-12-23 | 2008-05-28 | 동부일렉트로닉스 주식회사 | 시스템 인 패키지의 비아 도금방법 및 그 시스템 |
KR200454218Y1 (ko) * | 2008-10-08 | 2011-06-23 | 주식회사강산 | 핸드레일 |
AT506583B9 (de) | 2008-10-23 | 2009-12-15 | Happy Plating Gmbh | Elektrochemisches beschichtungsverfahren |
US8168540B1 (en) | 2009-12-29 | 2012-05-01 | Novellus Systems, Inc. | Methods and apparatus for depositing copper on tungsten |
KR101705734B1 (ko) | 2011-02-18 | 2017-02-14 | 삼성전자주식회사 | 구리 도금 용액 및 이것을 이용한 구리 도금 방법 |
EP2551375A1 (en) * | 2011-07-26 | 2013-01-30 | Atotech Deutschland GmbH | Electroless nickel plating bath composition |
US9598787B2 (en) * | 2013-03-14 | 2017-03-21 | Rohm And Haas Electronic Materials Llc | Method of filling through-holes |
US20140262801A1 (en) * | 2013-03-14 | 2014-09-18 | Rohm And Haas Electronic Materials Llc | Method of filling through-holes |
JP6327463B2 (ja) * | 2013-10-09 | 2018-05-23 | 日立化成株式会社 | 多層配線基板の製造方法 |
JP6350064B2 (ja) * | 2013-10-09 | 2018-07-04 | 日立化成株式会社 | 多層配線基板の製造方法 |
JP6350063B2 (ja) * | 2013-10-09 | 2018-07-04 | 日立化成株式会社 | 多層配線基板 |
US10154598B2 (en) * | 2014-10-13 | 2018-12-11 | Rohm And Haas Electronic Materials Llc | Filling through-holes |
JP6625872B2 (ja) | 2015-11-25 | 2019-12-25 | 新光電気工業株式会社 | 配線基板及び配線基板の製造方法 |
US10508357B2 (en) | 2016-02-15 | 2019-12-17 | Rohm And Haas Electronic Materials Llc | Method of filling through-holes to reduce voids and other defects |
US10512174B2 (en) * | 2016-02-15 | 2019-12-17 | Rohm And Haas Electronic Materials Llc | Method of filling through-holes to reduce voids and other defects |
JP2017162895A (ja) * | 2016-03-08 | 2017-09-14 | 株式会社ジェイデバイス | 配線構造、プリント基板、半導体装置及び配線構造の製造方法 |
EP3826439A1 (en) * | 2019-11-19 | 2021-05-26 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Laminated component carrier with blind hole having wedges filled with filling medium by sputtering and back-sputtering |
CN113747664B (zh) * | 2020-05-29 | 2024-01-05 | 深南电路股份有限公司 | 一种印制线路板及其制作方法 |
CN113795086B (zh) * | 2021-10-19 | 2023-04-14 | 重庆新固兴科技有限公司 | 双面假贴机 |
CN115003032B (zh) * | 2022-06-21 | 2023-03-07 | 东莞市国盈电子有限公司 | 一种马达驱动控制线路板及其制造工艺 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01143797A (ja) * | 1987-11-30 | 1989-06-06 | Mitsumi Electric Co Ltd | プレス装置 |
JPH1143797A (ja) * | 1997-07-25 | 1999-02-16 | Hideo Honma | ビアフィリング方法 |
JPH11298141A (ja) * | 1998-04-08 | 1999-10-29 | Hitachi Ltd | 電子装置の製造方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
BE534701A (ko) * | 1954-03-22 | |||
US5174886A (en) | 1991-02-22 | 1992-12-29 | Mcgean-Rohco, Inc. | High-throw acid copper plating using inert electrolyte |
US5252196A (en) | 1991-12-05 | 1993-10-12 | Shipley Company Inc. | Copper electroplating solutions and processes |
KR100336829B1 (ko) | 1998-04-10 | 2002-05-16 | 모기 쥰이찌 | 다층 배선 기판의 제조 방법 |
EP1091024A4 (en) | 1998-04-30 | 2006-03-22 | Ebara Corp | METHOD AND DEVICE FOR COATING SUBSTRATES |
US6534116B2 (en) * | 2000-08-10 | 2003-03-18 | Nutool, Inc. | Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence |
JP3124523B2 (ja) | 1999-01-28 | 2001-01-15 | 日本エレクトロプレイテイング・エンジニヤース株式会社 | 銅メッキ方法 |
US6224737B1 (en) * | 1999-08-19 | 2001-05-01 | Taiwan Semiconductor Manufacturing Company | Method for improvement of gap filling capability of electrochemical deposition of copper |
-
2000
- 2000-11-01 JP JP2000334044A patent/JP3594894B2/ja not_active Expired - Fee Related
-
2001
- 2001-01-30 US US09/772,457 patent/US6755957B2/en not_active Expired - Lifetime
- 2001-01-31 TW TW90101961A patent/TW574438B/zh not_active IP Right Cessation
- 2001-01-31 KR KR20010004601A patent/KR100730326B1/ko active IP Right Grant
- 2001-01-31 EP EP01300837A patent/EP1122989B1/en not_active Expired - Lifetime
- 2001-01-31 DE DE60126853T patent/DE60126853T2/de not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01143797A (ja) * | 1987-11-30 | 1989-06-06 | Mitsumi Electric Co Ltd | プレス装置 |
JPH1143797A (ja) * | 1997-07-25 | 1999-02-16 | Hideo Honma | ビアフィリング方法 |
JPH11298141A (ja) * | 1998-04-08 | 1999-10-29 | Hitachi Ltd | 電子装置の製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102254649B1 (ko) | 2020-04-14 | 2021-05-24 | 주식회사 디에이피 | 인쇄회로기판의 전기 동도금 방법 |
Also Published As
Publication number | Publication date |
---|---|
DE60126853T2 (de) | 2007-08-30 |
TW574438B (en) | 2004-02-01 |
JP2001291954A (ja) | 2001-10-19 |
US20010013472A1 (en) | 2001-08-16 |
JP3594894B2 (ja) | 2004-12-02 |
DE60126853D1 (de) | 2007-04-12 |
KR20010078217A (ko) | 2001-08-20 |
US6755957B2 (en) | 2004-06-29 |
EP1122989A2 (en) | 2001-08-08 |
EP1122989A3 (en) | 2002-07-03 |
EP1122989B1 (en) | 2007-02-28 |
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