KR100681665B9 - 칩용 보호막 형성용 시트 및 반도체 칩의 제조 방법 - Google Patents

칩용 보호막 형성용 시트 및 반도체 칩의 제조 방법

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Publication number
KR100681665B9
KR100681665B9 KR20020014961A KR20020014961A KR100681665B9 KR 100681665 B9 KR100681665 B9 KR 100681665B9 KR 20020014961 A KR20020014961 A KR 20020014961A KR 20020014961 A KR20020014961 A KR 20020014961A KR 100681665 B9 KR100681665 B9 KR 100681665B9
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KR
South Korea
Prior art keywords
chips
sheet
protective film
producing semiconductor
semiconductor chips
Prior art date
Application number
KR20020014961A
Other languages
English (en)
Other versions
KR20020075256A (ko
KR100681665B1 (ko
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Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=18937369&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=KR100681665(B9) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed filed Critical
Publication of KR20020075256A publication Critical patent/KR20020075256A/ko
Application granted granted Critical
Publication of KR100681665B1 publication Critical patent/KR100681665B1/ko
Publication of KR100681665B9 publication Critical patent/KR100681665B9/ko

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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3164—Partial encapsulation or coating the coating being a foil
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    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L23/293—Organic, e.g. plastic
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    • H01L2224/29001—Core members of the layer connector
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    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
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    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/14—Layer or component removable to expose adhesive

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
  • Laminated Bodies (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Adhesives Or Adhesive Processes (AREA)
  • Adhesive Tapes (AREA)
KR1020020014961A 2001-03-21 2002-03-20 칩용 보호막 형성용 시트 및 반도체 칩의 제조 방법 KR100681665B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2001-00081226 2001-03-21
JP2001081226A JP3544362B2 (ja) 2001-03-21 2001-03-21 半導体チップの製造方法

Publications (3)

Publication Number Publication Date
KR20020075256A KR20020075256A (ko) 2002-10-04
KR100681665B1 KR100681665B1 (ko) 2007-02-09
KR100681665B9 true KR100681665B9 (ko) 2021-07-08

Family

ID=18937369

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020020014961A KR100681665B1 (ko) 2001-03-21 2002-03-20 칩용 보호막 형성용 시트 및 반도체 칩의 제조 방법

Country Status (10)

Country Link
US (4) US6919262B2 (ko)
EP (3) EP1852906B1 (ko)
JP (1) JP3544362B2 (ko)
KR (1) KR100681665B1 (ko)
CN (2) CN100370581C (ko)
DE (1) DE60225084T2 (ko)
MX (1) MXPA02003032A (ko)
MY (2) MY135433A (ko)
PT (3) PT2911189T (ko)
TW (1) TW533532B (ko)

Families Citing this family (112)

* Cited by examiner, † Cited by third party
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JP3544362B2 (ja) * 2001-03-21 2004-07-21 リンテック株式会社 半導体チップの製造方法
JP4341343B2 (ja) * 2002-10-04 2009-10-07 日立化成工業株式会社 表面保護フィルム及びその製造方法
GB2404280B (en) 2003-07-03 2006-09-27 Xsil Technology Ltd Die bonding
JP4093930B2 (ja) * 2003-07-17 2008-06-04 株式会社東京精密 フレーム搬送プローバ
JP2005051018A (ja) * 2003-07-28 2005-02-24 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP2005197572A (ja) * 2004-01-09 2005-07-21 Renesas Technology Corp 半導体チップの製造方法並びに液晶表示装置の製造方法
JP4523777B2 (ja) * 2004-01-09 2010-08-11 リンテック株式会社 剥離シート
JP4523778B2 (ja) * 2004-01-16 2010-08-11 リンテック株式会社 剥離シート
JP4523780B2 (ja) * 2004-01-26 2010-08-11 リンテック株式会社 剥離シート
JP2005223244A (ja) * 2004-02-09 2005-08-18 Tokyo Seimitsu Co Ltd チップの飛び出し位置検出方法
WO2005093829A1 (en) * 2004-03-16 2005-10-06 Infineon Technologies Ag Semiconductor package having an interfacial adhesive layer
JP2005327789A (ja) * 2004-05-12 2005-11-24 Sharp Corp ダイシング・ダイボンド兼用粘接着シートおよびこれを用いた半導体装置の製造方法
JP4754185B2 (ja) * 2004-05-27 2011-08-24 リンテック株式会社 半導体封止用樹脂シートおよびこれを用いた半導体装置の製造方法
JP4642436B2 (ja) * 2004-11-12 2011-03-02 リンテック株式会社 マーキング方法および保護膜形成兼ダイシング用シート
DE102005024431B4 (de) 2005-05-24 2009-08-06 Infineon Technologies Ag Verfahren zur Herstellung von Halbleiterbauteilen unter Verwendung einer Trägerplatte mit doppelseitig klebender Klebstofffolie
JP4731241B2 (ja) * 2005-08-02 2011-07-20 株式会社ディスコ ウエーハの分割方法
DE102005046479B4 (de) * 2005-09-28 2008-12-18 Infineon Technologies Austria Ag Verfahren zum Spalten von spröden Materialien mittels Trenching Technologie
JP4812392B2 (ja) * 2005-10-14 2011-11-09 日東電工株式会社 熱硬化性樹脂シート
JP5046366B2 (ja) * 2005-10-20 2012-10-10 信越化学工業株式会社 接着剤組成物及び該接着剤からなる接着層を備えたシート
US7371674B2 (en) * 2005-12-22 2008-05-13 Intel Corporation Nanostructure-based package interconnect
JP2007250970A (ja) * 2006-03-17 2007-09-27 Hitachi Chem Co Ltd 半導体素子裏面保護用フィルム及びそれを用いた半導体装置とその製造法
JP4846406B2 (ja) * 2006-03-28 2011-12-28 リンテック株式会社 チップ用保護膜形成用シート
TWI381433B (zh) 2006-07-27 2013-01-01 Princo Corp 結合ｉｃ整合基板與載板之結構及其製造方法與電子裝置之製造方法
DE102006035644A1 (de) * 2006-07-31 2008-02-14 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Reduzieren der Kontamination durch Vorsehen einer zu entfernenden Polymerschutzschicht während der Bearbeitung von Mikrostrukturen
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CN100485909C (zh) * 2006-08-18 2009-05-06 巨擘科技股份有限公司 结合ic整合基板与载板的结构及其与电子装置的制造方法
KR100831968B1 (ko) * 2006-09-01 2008-05-27 엠텍비젼 주식회사 반도체 패키징 방법 및 이에 의해 제조되는 반도체 패키지
JP5054954B2 (ja) * 2006-09-22 2012-10-24 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP4439507B2 (ja) * 2006-10-23 2010-03-24 Ｏｋｉセミコンダクタ株式会社 センサチップの製造方法
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