KR100530242B1 - 집적회로제조시감소된측벽축적을갖는금속에칭방법 - Google Patents

집적회로제조시감소된측벽축적을갖는금속에칭방법 Download PDF

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Publication number
KR100530242B1
KR100530242B1 KR1019980023053A KR19980023053A KR100530242B1 KR 100530242 B1 KR100530242 B1 KR 100530242B1 KR 1019980023053 A KR1019980023053 A KR 1019980023053A KR 19980023053 A KR19980023053 A KR 19980023053A KR 100530242 B1 KR100530242 B1 KR 100530242B1
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KR
South Korea
Prior art keywords
etching
barrier layer
layer
sputter component
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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KR1019980023053A
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English (en)
Korean (ko)
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KR19990007125A (ko
Inventor
무니어 디. 나엠
스튜어트 엠. 번스
낸시 그레코
스티브 그레코
비린더 그레발
어니스트 레빈
마사끼 나리타
브루노 스풀러
Original Assignee
인터내셔널 비지네스 머신즈 코포레이션
가부시끼가이샤 도시바
지멘스 악티엔게젤샤프트
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First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=15777909&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=KR100530242(B1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by 인터내셔널 비지네스 머신즈 코포레이션, 가부시끼가이샤 도시바, 지멘스 악티엔게젤샤프트 filed Critical 인터내셔널 비지네스 머신즈 코포레이션
Publication of KR19990007125A publication Critical patent/KR19990007125A/ko
Application granted granted Critical
Publication of KR100530242B1 publication Critical patent/KR100530242B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/20Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/08Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/14Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/14Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Drying Of Semiconductors (AREA)
KR1019980023053A 1997-06-20 1998-06-19 집적회로제조시감소된측벽축적을갖는금속에칭방법 Expired - Fee Related KR100530242B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/879,727 1997-06-20
JP97-163646 1997-06-20
JP16364697A JP4056107B2 (ja) 1997-06-20 1997-06-20 半導体集積回路

Publications (2)

Publication Number Publication Date
KR19990007125A KR19990007125A (ko) 1999-01-25
KR100530242B1 true KR100530242B1 (ko) 2006-01-27

Family

ID=15777909

Family Applications (2)

Application Number Title Priority Date Filing Date
KR1019980023053A Expired - Fee Related KR100530242B1 (ko) 1997-06-20 1998-06-19 집적회로제조시감소된측벽축적을갖는금속에칭방법
KR1019980023054A Expired - Lifetime KR100566410B1 (ko) 1997-06-20 1998-06-19 반도체 집적회로

Family Applications After (1)

Application Number Title Priority Date Filing Date
KR1019980023054A Expired - Lifetime KR100566410B1 (ko) 1997-06-20 1998-06-19 반도체 집적회로

Country Status (4)

Country Link
US (4) US6107869A (https=)
JP (1) JP4056107B2 (https=)
KR (2) KR100530242B1 (https=)
TW (1) TW382802B (https=)

Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4056107B2 (ja) * 1997-06-20 2008-03-05 エルピーダメモリ株式会社 半導体集積回路
JP4014708B2 (ja) * 1997-08-21 2007-11-28 株式会社ルネサステクノロジ 半導体集積回路装置の設計方法
JP2001118999A (ja) * 1999-10-15 2001-04-27 Hitachi Ltd ダイナミック型ramと半導体装置
JP3609003B2 (ja) * 2000-05-02 2005-01-12 シャープ株式会社 Cmos半導体集積回路
KR100395876B1 (ko) * 2000-10-18 2003-08-25 삼성전자주식회사 디램 장치의 접지 전압 공급 라인 구조
DE10120790A1 (de) * 2001-04-27 2002-11-21 Infineon Technologies Ag Schaltungsanordnung zur Verringerung der Versorgungsspannung eines Schaltungsteils sowie Verfahren zum Aktivieren eines Schaltungsteils
US6759873B2 (en) 2001-05-22 2004-07-06 The Board Of Trustees Of The University Of Illinois Reverse biasing logic circuit
US6946901B2 (en) * 2001-05-22 2005-09-20 The Regents Of The University Of California Low-power high-performance integrated circuit and related methods
KR100403631B1 (ko) * 2001-07-20 2003-10-30 삼성전자주식회사 비트라인 센스앰프 드라이버의 배치방법
US6621756B2 (en) * 2001-11-26 2003-09-16 Macronix International Co., Ltd. Compact integrated circuit with memory array
US6781892B2 (en) * 2001-12-26 2004-08-24 Intel Corporation Active leakage control in single-ended full-swing caches
JP3786608B2 (ja) * 2002-01-28 2006-06-14 株式会社ルネサステクノロジ 半導体集積回路装置
KR100993517B1 (ko) * 2002-03-27 2010-11-10 더 리전트 오브 더 유니버시티 오브 캘리포니아 집적 회로, 집적 회로 구동 회로, 및 관련방법
JP2004022647A (ja) 2002-06-13 2004-01-22 Fujitsu Ltd 半導体集積回路
JP4632625B2 (ja) * 2002-11-14 2011-02-16 ルネサスエレクトロニクス株式会社 薄膜磁性体記憶装置
US6927429B2 (en) * 2003-02-14 2005-08-09 Freescale Semiconductor, Inc. Integrated circuit well bias circuity
US7707255B2 (en) 2003-07-01 2010-04-27 Microsoft Corporation Automatic grouping of electronic mail
JP2005101522A (ja) * 2003-08-21 2005-04-14 Matsushita Electric Ind Co Ltd 半導体集積回路装置
US7026843B1 (en) * 2004-01-16 2006-04-11 Spansion Llc Flexible cascode amplifier circuit with high gain for flash memory cells
JP4200926B2 (ja) 2004-03-10 2008-12-24 ソニー株式会社 半導体集積回路
US8255828B2 (en) 2004-08-16 2012-08-28 Microsoft Corporation Command user interface for displaying selectable software functionality controls
US8146016B2 (en) 2004-08-16 2012-03-27 Microsoft Corporation User interface for displaying a gallery of formatting options applicable to a selected object
US7703036B2 (en) 2004-08-16 2010-04-20 Microsoft Corporation User interface for displaying selectable software functionality controls that are relevant to a selected object
US7527446B2 (en) * 2005-04-29 2009-05-05 The Procter & Gamble Company Children's combination toothbrush and toothpaste dispenser, and method
US8627222B2 (en) 2005-09-12 2014-01-07 Microsoft Corporation Expanded search and find user interface
KR100704039B1 (ko) * 2006-01-20 2007-04-04 삼성전자주식회사 디코딩 신호가 워드라인 방향으로 버싱되는 반도체 메모리장치
JP2007227625A (ja) * 2006-02-23 2007-09-06 Toshiba Microelectronics Corp 半導体集積回路及びそのレイアウト設計方法
US7791406B1 (en) 2006-04-04 2010-09-07 Marvell International Ltd. Low leakage power management
US7606057B2 (en) * 2006-05-31 2009-10-20 Arm Limited Metal line layout in a memory cell
US9727989B2 (en) 2006-06-01 2017-08-08 Microsoft Technology Licensing, Llc Modifying and formatting a chart using pictorially provided chart elements
US7408830B2 (en) * 2006-11-07 2008-08-05 Taiwan Semiconductor Manufacturing Co. Dynamic power supplies for semiconductor devices
US7808804B2 (en) * 2006-11-10 2010-10-05 Samsung Electronics Co., Ltd. Power line layout
US8762880B2 (en) 2007-06-29 2014-06-24 Microsoft Corporation Exposing non-authoring features through document status information in an out-space user interface
US8484578B2 (en) 2007-06-29 2013-07-09 Microsoft Corporation Communication between a document editor in-space user interface and a document editor out-space user interface
JP2009038306A (ja) * 2007-08-03 2009-02-19 Elpida Memory Inc 半導体記憶装置
JP5528662B2 (ja) 2007-09-18 2014-06-25 ソニー株式会社 半導体集積回路
JP4636077B2 (ja) 2007-11-07 2011-02-23 ソニー株式会社 半導体集積回路
FR2927468B1 (fr) * 2008-02-08 2010-04-23 E2V Semiconductors Circuit integre a grand nombre de circuits elementaires identiques alimentes en parallele.
JP4492736B2 (ja) * 2008-06-12 2010-06-30 ソニー株式会社 半導体集積回路
US9665850B2 (en) 2008-06-20 2017-05-30 Microsoft Technology Licensing, Llc Synchronized conversation-centric message list and message reading pane
US8717093B2 (en) * 2010-01-08 2014-05-06 Mindspeed Technologies, Inc. System on chip power management through package configuration
JP5709197B2 (ja) * 2010-05-21 2015-04-30 国立大学法人 東京大学 集積回路装置
JP2015076111A (ja) * 2013-10-08 2015-04-20 マイクロン テクノロジー, インク. 半導体装置
US10020252B2 (en) 2016-11-04 2018-07-10 Micron Technology, Inc. Wiring with external terminal
US10354705B2 (en) 2017-07-05 2019-07-16 Micron Technology, Inc. Apparatuses and methods for controlling word lines and sense amplifiers
US10141932B1 (en) * 2017-08-04 2018-11-27 Micron Technology, Inc. Wiring with external terminal
US10304497B2 (en) 2017-08-17 2019-05-28 Micron Technology, Inc. Power supply wiring in a semiconductor memory device
TWI646515B (zh) * 2018-01-19 2019-01-01 友達光電股份有限公司 顯示裝置
US10877908B2 (en) * 2018-09-25 2020-12-29 Micron Technology, Inc. Isolation component
US11361814B2 (en) * 2020-10-29 2022-06-14 Micron Technology, Inc. Column selector architecture with edge mat optimization
US12482519B2 (en) 2023-01-19 2025-11-25 Micron Technology, Inc. Microelectronic devices and memory devices

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0435064A (ja) * 1990-05-31 1992-02-05 Oki Electric Ind Co Ltd 半導体記憶装置
US5160407A (en) * 1991-01-02 1992-11-03 Applied Materials, Inc. Low pressure anisotropic etch process for tantalum silicide or titanium silicide layer formed over polysilicon layer deposited on silicon oxide layer on semiconductor wafer
US5280450A (en) * 1990-05-14 1994-01-18 Hitachi, Ltd. High-speed semicondustor memory integrated circuit arrangement having power and signal lines with reduced resistance
JPH08195083A (ja) * 1995-01-17 1996-07-30 Toshiba Microelectron Corp 半導体記憶装置
JPH0974175A (ja) * 1995-09-04 1997-03-18 Texas Instr Japan Ltd 半導体装置及び半導体メモリ装置

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5309040A (en) * 1989-11-07 1994-05-03 Fujitsu Limited Voltage reducing circuit
JP2896197B2 (ja) 1990-06-01 1999-05-31 日本テキサス・インスツルメンツ株式会社 半導体装置
JP3112047B2 (ja) * 1991-11-08 2000-11-27 株式会社日立製作所 半導体集積回路
US5583457A (en) * 1992-04-14 1996-12-10 Hitachi, Ltd. Semiconductor integrated circuit device having power reduction mechanism
US5614847A (en) * 1992-04-14 1997-03-25 Hitachi, Ltd. Semiconductor integrated circuit device having power reduction mechanism
JP3216925B2 (ja) * 1992-04-14 2001-10-09 株式会社日立製作所 半導体集積回路
JP3347766B2 (ja) 1992-06-08 2002-11-20 日本トムソン株式会社 リニアエンコーダ及びこれを具備した案内ユニット
US5408144A (en) * 1993-01-07 1995-04-18 Hitachi, Ltd. Semiconductor integrated circuits with power reduction mechanism
JP3102179B2 (ja) * 1993-01-07 2000-10-23 株式会社日立製作所 半導体集積回路
JP3047659B2 (ja) * 1993-02-02 2000-05-29 株式会社日立製作所 半導体集積回路
KR0169157B1 (ko) * 1993-11-29 1999-02-01 기다오까 다까시 반도체 회로 및 mos-dram
JP3561012B2 (ja) * 1994-11-07 2004-09-02 株式会社ルネサステクノロジ 半導体集積回路装置
JP2931776B2 (ja) * 1995-08-21 1999-08-09 三菱電機株式会社 半導体集積回路
JP3869045B2 (ja) 1995-11-09 2007-01-17 株式会社日立製作所 半導体記憶装置
TW324101B (en) * 1995-12-21 1998-01-01 Hitachi Ltd Semiconductor integrated circuit and its working method
JP3684748B2 (ja) * 1997-01-22 2005-08-17 アンデン株式会社 負荷駆動回路
JP4056107B2 (ja) * 1997-06-20 2008-03-05 エルピーダメモリ株式会社 半導体集積回路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5280450A (en) * 1990-05-14 1994-01-18 Hitachi, Ltd. High-speed semicondustor memory integrated circuit arrangement having power and signal lines with reduced resistance
JPH0435064A (ja) * 1990-05-31 1992-02-05 Oki Electric Ind Co Ltd 半導体記憶装置
US5160407A (en) * 1991-01-02 1992-11-03 Applied Materials, Inc. Low pressure anisotropic etch process for tantalum silicide or titanium silicide layer formed over polysilicon layer deposited on silicon oxide layer on semiconductor wafer
JPH08195083A (ja) * 1995-01-17 1996-07-30 Toshiba Microelectron Corp 半導体記憶装置
JPH0974175A (ja) * 1995-09-04 1997-03-18 Texas Instr Japan Ltd 半導体装置及び半導体メモリ装置

Also Published As

Publication number Publication date
TW382802B (en) 2000-02-21
US6339358B1 (en) 2002-01-15
US6747509B2 (en) 2004-06-08
US7199648B2 (en) 2007-04-03
US20040217776A1 (en) 2004-11-04
KR100566410B1 (ko) 2007-08-16
US6107869A (en) 2000-08-22
JP4056107B2 (ja) 2008-03-05
JPH1117135A (ja) 1999-01-22
KR19990007126A (ko) 1999-01-25
US20020057129A1 (en) 2002-05-16
KR19990007125A (ko) 1999-01-25

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