KR100315740B1 - 반도체장치및그제조방법 - Google Patents

반도체장치및그제조방법 Download PDF

Info

Publication number
KR100315740B1
KR100315740B1 KR1019970049100A KR19970049100A KR100315740B1 KR 100315740 B1 KR100315740 B1 KR 100315740B1 KR 1019970049100 A KR1019970049100 A KR 1019970049100A KR 19970049100 A KR19970049100 A KR 19970049100A KR 100315740 B1 KR100315740 B1 KR 100315740B1
Authority
KR
South Korea
Prior art keywords
layer
oxide film
gate electrode
nitrogen
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019970049100A
Other languages
English (en)
Korean (ko)
Other versions
KR19980086383A (ko
Inventor
슈이치 우에노
시게토 마에가와
요시노리 오쿠무라
시게노부 마에다
Original Assignee
다니구찌 이찌로오, 기타오카 다카시
미쓰비시덴키 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 다니구찌 이찌로오, 기타오카 다카시, 미쓰비시덴키 가부시키가이샤 filed Critical 다니구찌 이찌로오, 기타오카 다카시
Publication of KR19980086383A publication Critical patent/KR19980086383A/ko
Application granted granted Critical
Publication of KR100315740B1 publication Critical patent/KR100315740B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H01L21/76218—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers introducing both types of electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers, e.g. for isolation of complementary doped regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
KR1019970049100A 1997-05-14 1997-09-26 반도체장치및그제조방법 Expired - Fee Related KR100315740B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP12394197A JP3648015B2 (ja) 1997-05-14 1997-05-14 半導体装置
JP123941 1997-05-14

Publications (2)

Publication Number Publication Date
KR19980086383A KR19980086383A (ko) 1998-12-05
KR100315740B1 true KR100315740B1 (ko) 2002-05-30

Family

ID=14873149

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970049100A Expired - Fee Related KR100315740B1 (ko) 1997-05-14 1997-09-26 반도체장치및그제조방법

Country Status (7)

Country Link
US (1) US5998828A (enExample)
JP (1) JP3648015B2 (enExample)
KR (1) KR100315740B1 (enExample)
CN (1) CN100401527C (enExample)
DE (1) DE19800089A1 (enExample)
FR (1) FR2763425B1 (enExample)
TW (1) TW393768B (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101050034B1 (ko) * 2006-12-22 2011-07-19 인텔 코오퍼레이션 상이한 도전성 타입 영역들에 유리한 게이트들을 포함하는플로팅 바디 메모리 셀
KR101355282B1 (ko) 2006-02-07 2014-01-27 세이코 인스트루 가부시키가이샤 반도체 장치 및 그 제조 방법

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3602679B2 (ja) * 1997-02-26 2004-12-15 株式会社ルネサステクノロジ 半導体装置およびその製造方法
US6188101B1 (en) * 1998-01-14 2001-02-13 Advanced Micro Devices, Inc. Flash EPROM cell with reduced short channel effect and method for providing same
JP3769120B2 (ja) * 1998-05-08 2006-04-19 株式会社東芝 半導体素子
US6249841B1 (en) * 1998-12-03 2001-06-19 Ramtron International Corporation Integrated circuit memory device and method incorporating flash and ferroelectric random access memory arrays
JP2001093903A (ja) 1999-09-24 2001-04-06 Toshiba Corp 半導体装置及びその製造方法
JP3613113B2 (ja) * 2000-01-21 2005-01-26 日本電気株式会社 半導体装置およびその製造方法
US6333244B1 (en) * 2000-01-26 2001-12-25 Advanced Micro Devices, Inc. CMOS fabrication process with differential rapid thermal anneal scheme
JP4823408B2 (ja) * 2000-06-08 2011-11-24 ルネサスエレクトロニクス株式会社 不揮発性半導体記憶装置
US6956757B2 (en) 2000-06-22 2005-10-18 Contour Semiconductor, Inc. Low cost high density rectifier matrix memory
US6630386B1 (en) 2000-07-18 2003-10-07 Advanced Micro Devices, Inc CMOS manufacturing process with self-amorphized source/drain junctions and extensions
US6521502B1 (en) 2000-08-07 2003-02-18 Advanced Micro Devices, Inc. Solid phase epitaxy activation process for source/drain junction extensions and halo regions
JP2002208645A (ja) * 2001-01-09 2002-07-26 Mitsubishi Electric Corp 不揮発性半導体記憶装置およびその製造方法
US6747318B1 (en) * 2001-12-13 2004-06-08 Lsi Logic Corporation Buried channel devices and a process for their fabrication simultaneously with surface channel devices to produce transistors and capacitors with multiple electrical gate oxides
US7314812B2 (en) 2003-08-28 2008-01-01 Micron Technology, Inc. Method for reducing the effective thickness of gate oxides by nitrogen implantation and anneal
JP2005101466A (ja) * 2003-09-26 2005-04-14 Renesas Technology Corp 半導体記憶装置
JP4513497B2 (ja) * 2004-10-19 2010-07-28 ソニー株式会社 固体撮像装置
US7488635B2 (en) * 2005-10-26 2009-02-10 Freescale Semiconductor, Inc. Semiconductor structure with reduced gate doping and methods for forming thereof
KR100742758B1 (ko) * 2005-11-02 2007-07-26 경북대학교 산학협력단 플래시 메모리 소자 및 그 제조방법
US7573095B2 (en) * 2006-12-05 2009-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Memory cells with improved program/erase windows
US7652923B2 (en) * 2007-02-02 2010-01-26 Macronix International Co., Ltd. Semiconductor device and memory and method of operating thereof
US7933133B2 (en) * 2007-11-05 2011-04-26 Contour Semiconductor, Inc. Low cost, high-density rectifier matrix memory
US8969969B2 (en) * 2009-03-20 2015-03-03 International Business Machines Corporation High threshold voltage NMOS transistors for low power IC technology
JP2012028790A (ja) * 2011-08-19 2012-02-09 Renesas Electronics Corp 半導体装置
CN103107076B (zh) * 2011-11-11 2015-04-29 中芯国际集成电路制造(上海)有限公司 分离栅极式快闪存储器及存储器组的制作方法
CN103377901A (zh) * 2012-04-28 2013-10-30 无锡华润上华科技有限公司 多晶硅栅极的形成方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04157766A (ja) * 1990-10-20 1992-05-29 Sony Corp シリコンゲートｐチャンネルＭＯＳ半導体装置の製造方法
JPH07176743A (ja) * 1993-09-02 1995-07-14 Mitsubishi Electric Corp 半導体装置及びその製造方法
JPH0922999A (ja) * 1995-07-07 1997-01-21 Seiko Epson Corp Ｍｉｓ型半導体装置及びその製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4774197A (en) * 1986-06-17 1988-09-27 Advanced Micro Devices, Inc. Method of improving silicon dioxide
US5514902A (en) * 1993-09-16 1996-05-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having MOS transistor
JPH07335883A (ja) * 1994-06-15 1995-12-22 Toshiba Corp 半導体装置の製造方法
JPH08139315A (ja) * 1994-11-09 1996-05-31 Mitsubishi Electric Corp Ｍｏｓトランジスタ、半導体装置及びそれらの製造方法
US5674788A (en) * 1995-06-06 1997-10-07 Advanced Micro Devices, Inc. Method of forming high pressure silicon oxynitride gate dielectrics
US5567638A (en) * 1995-06-14 1996-10-22 National Science Council Method for suppressing boron penetration in PMOS with nitridized polysilicon gate
US5734186A (en) * 1996-09-16 1998-03-31 Delco Electronics Corporation CMOS voltage clamp

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04157766A (ja) * 1990-10-20 1992-05-29 Sony Corp シリコンゲートｐチャンネルＭＯＳ半導体装置の製造方法
JPH07176743A (ja) * 1993-09-02 1995-07-14 Mitsubishi Electric Corp 半導体装置及びその製造方法
JPH0922999A (ja) * 1995-07-07 1997-01-21 Seiko Epson Corp Ｍｉｓ型半導体装置及びその製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101355282B1 (ko) 2006-02-07 2014-01-27 세이코 인스트루 가부시키가이샤 반도체 장치 및 그 제조 방법
KR101050034B1 (ko) * 2006-12-22 2011-07-19 인텔 코오퍼레이션 상이한 도전성 타입 영역들에 유리한 게이트들을 포함하는플로팅 바디 메모리 셀
US10720434B2 (en) 2006-12-22 2020-07-21 Intel Corporation Floating body memory cell having gates favoring different conductivity type regions
US10916547B2 (en) 2006-12-22 2021-02-09 Intel Corporation Floating body memory cell having gates favoring different conductivity type regions
US11462540B2 (en) 2006-12-22 2022-10-04 Intel Corporation Floating body memory cell having gates favoring different conductivity type regions
US11785759B2 (en) 2006-12-22 2023-10-10 Intel Corporation Floating body memory cell having gates favoring different conductivity type regions

Also Published As

Publication number Publication date
US5998828A (en) 1999-12-07
TW393768B (en) 2000-06-11
JPH10313098A (ja) 1998-11-24
KR19980086383A (ko) 1998-12-05
CN1199248A (zh) 1998-11-18
FR2763425B1 (fr) 2002-01-04
DE19800089A1 (de) 1998-11-19
FR2763425A1 (fr) 1998-11-20
JP3648015B2 (ja) 2005-05-18
CN100401527C (zh) 2008-07-09

Similar Documents

Publication Publication Date Title
KR100315740B1 (ko) 반도체장치및그제조방법
KR19980079317A (ko) 반도체 장치 및 그 제조방법
EP0550404B1 (en) A method of making a capacitive coupling device, especially in an EEPROM
US5702988A (en) Blending integrated circuit technology
US5403764A (en) Method for producing a ROM on a semiconductor device having a nonvolatile memory
US6376879B2 (en) Semiconductor device having MISFETs
DE102006021070B4 (de) Halbleitervorrichtungen mit tiefen Grabenisolationsstrukturen und Verfahren zu deren Anfertigung
US20010045590A1 (en) Nonvolatile semiconductor memory device and process for producing the same
US7364973B2 (en) Method of manufacturing NOR-type mask ROM device and semiconductor device including the same
US6770934B1 (en) Flash memory device structure and manufacturing method thereof
JPH10313098A5 (enExample)
US20210225757A1 (en) Co-integrated vertically structured capacitive element and fabrication process
US5359218A (en) Semiconductor memory device with selection gate in a groove
US10825522B2 (en) Method for fabricating low and high/medium voltage transistors on substrate
US6570212B1 (en) Complementary avalanche injection EEPROM cell
KR100292278B1 (ko) 반도체장치및그제조방법
US6815295B1 (en) Method of manufacturing field effect transistors
US6531366B1 (en) Method and structure for high-voltage device with self-aligned graded junctions
JP2005136434A (ja) 半導体装置
US6346441B1 (en) Method of fabricating flash memory cell using two tilt implantation steps
US5908308A (en) Use of borophosphorous tetraethyl orthosilicate (BPTEOS) to improve isolation in a transistor array
US20050263815A1 (en) Memory device and method of manufacturing the same
JPH1140775A (ja) 半導体装置およびその製造方法
KR100475033B1 (ko) 불휘발성 메모리소자 제조방법
KR20040010445A (ko) 고전압 모오스 트랜지스터의 구조 및 그 제조방법

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 10

FPAY Annual fee payment

Payment date: 20111019

Year of fee payment: 11

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 11

FPAY Annual fee payment

Payment date: 20121023

Year of fee payment: 12

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 12

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20131114

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20131114

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000