KR0174029B1 - Insulated gate semiconductor device and process for fabricating the same - Google Patents

Abstract

Inverse staggered thin film transistors having improved properties but obtained by a simple process are selectively doped with source, drain, and channel forming regions by ion implantation, ion doping, or doping of plasma ions, and then short-term UV, visible, or near infrared rays. It is prepared by carrying out rapid open annealing by irradiation. The source, drain and channel forming regions are actually formed in a single plane.

Description

Insulated gate semiconductor device and manufacturing method thereof

1 (a) to 1 (d) are sectional views showing the TFT fabrication method according to the present invention.

2 (a) to 2 (d) are cross-sectional views showing a TFT manufacturing method according to the prior art.

3 is a chart showing the process sequence of the TFT fabrication method according to Example 1. FIG.

4 is a chart showing a process sequence of a TFT fabrication method according to Example 2. FIG.

5 is a chart showing a process sequence of a TFT fabrication method according to the prior art.

6 is a table showing a process sequence of another TFT fabrication method according to the prior art.

7 (a) and 7 (b) are graphs showing an example of temperature setting in Example 1. FIG.

* Explanation of symbols for main parts of the drawings

101 substrate 102 gate electrode

103: oxide film 104: gate insulating film

105: semiconductor region 106: silicon nitride film

107 photoresist 108 impurity region

109: channel forming region 110: metal wiring and electrode

111: pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metal-insulator-semiconductor (MIS) type semiconductor device, in particular a MIS transistor and a method of manufacturing the same. In particular, the present invention relates to a thin-film MIS type semiconductor device formed on an insulating substrate, in particular, a thin film transistor (TFT). In particular, the present invention relates to a MIS type semiconductor device having a so-called reverse staggered structure in which a channel formation region is located above the gate electrode. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit formed on an insulating substrate, for example, an active matrix circuit used in a liquid crystal display device, a driving circuit of an image sensor, or the like.

Recently, a device including a thin film MIS type semiconductor device formed on an insulating substrate has been actually used. Such devices can be seen, for example, in Actis matrix type liquid crystal display politics. There are two types of active matrix circuits currently on the market using TFTs and diodes such as MIM. In particular, the former active matrix type circuit is actively produced because high quality images are obtained.

As an active matrix circuit using TFTs, there are known TFTs using polycrystalline semiconductors such as polycrystalline silicon and TFTs using amorphous semiconductors such as amorphous silicon (hereinafter referred to as amorphous silicon TFTs). However, the former TFT cannot be applied to a large-area display device because of problems in the manufacturing process, and the latter, which can be manufactured at a process temperature of 350 ° C. or less, is mainly used for the large-area display device.

The manufacturing process of the conventional reverse staggered amorphous silicon TFT is shown by FIG. 2 (a)-2 (d). As the substrate 201, a heat-resistant alkali free glass such as Corning 7059 glass is used. Since the maximum process temperature of the amorphous silicon TFT is about 350 ° C, a material that can withstand this temperature should be used. In particular, when the TFT is used in a liquid crystal display panel, a furnace having a sufficiently high heat resistance and a high glass transition temperature should be used so that the substrate is not deformed by heat treatment. In this respect, Corning 7059 glass is suitable as a substrate material because its glass transition temperature is slightly lower than 600 ° C.

In addition, in order to stabilize the operation of the TFT, it is not preferable that movable ions such as sodium are contained in the substrate. Corning 7059 glass does not have a problem because the concentration of alkali ions is sufficiently low. However, when a large amount of alkali ions such as sodium ions are contained in the substrate, silicon nitride, aluminum oxide, or the like is prevented from entering into the TFT. It is necessary to form a passivation film.

First, a film is formed on a substrate with a conductive material such as aluminum or tantalum, and then the gate electrode 202 is formed by patterning using a mask ①. In particular, in order to prevent a short circuit between the gate electrode and the wiring and the upper wiring, an oxide film 203 may be formed on the surface of the gate electrode. As the formation method of the oxide film, anodization is mainly used. In that case, the oxide film is formed by applying a positive voltage to the gate electrode 202 in the electrolytic solution to oxidize the surface of the gate electrode.

Thereafter, a gate insulating film 204 is formed. Although silicon nitride is generally used as this gate insulating film, it is not limited to this, A silicon oxide may be sufficient, or the silicide containing nitrogen and oxygen in arbitrary ratios may be sufficient as it. The gate insulating film may be a single layer film or a multilayer film. When silicon nitride is used as the gate insulating film, for example, a plasma CVD method can be used. In the case of using the plasma CVD method, the process temperature is about 350 ° C, which is the maximum temperature of the present process. The structure thus obtained is shown in Fig. 2 (a).

Thereafter, an amorphous silicon film is formed. When the amorphous silicon film is formed by the plasma CVD method, the substrate is heated to a temperature of 250 to 300 ° C. The thickness of the film is preferably as thin as possible, and usually 10 to 100 nm, preferably 10 to 30 nm. Then, the amorphous silicon film is patterned using the mask ② to form the amorphous silicon region 205. This amorphous silicon region 205 provides a channel forming region of the TFT in a later step. The state thus far is shown in FIG. 2 (b).

Next, a silicon nitride film is formed on the entire surface, and the silicon nitride film is patterned using a mask 3 to provide an etching stopper 206. This etching stopper is provided to prevent the etching of the amorphous silicon region 205 of the channel forming region by mistake in a later process, since the amorphous silicon region 205 is thin to a thickness of 10 to 100 nm as described above. to be. In addition, since the amorphous silicon region under the etch stopper functions as a channel forming region, the etch stopper is designed to overlap the gate electrode as much as possible. However, since some deviation occurs in normal mask fitting, the etching stopper is patterned so as to overlap the gate electrode sufficiently (that is, smaller than the gate electrode).

Thereafter, a silicon film of N type or P type conductivity is formed. Normal amorphous silicon TFTs are of N-channel type. Since the silicon film has an insufficiently low conductivity in amorphous silicon, a silicon film in a microcrystalline state is used instead. The N-type conductive microcrystalline silicon film can be produced at a temperature of 350 ° C. or lower by the plasma CVD method. However, since the resistance is not sufficiently low, the N-type microcrystalline silicon film needs to be formed to a thickness of 200 nm or more. The P-type microcrystalline silicon film cannot be used as it is because the resistance is remarkably large, and therefore, it is difficult to fabricate the P-channel TFT from amorphous silicon.

Thereafter, the silicon film thus formed is patterned using a mask ④ to form an N-type microcrystalline silicon region 207. The state thus far is shown in FIG. 2 (c).

However, the structure of FIG. 2 (c) cannot function as a TFT because the N-type microcrystalline silicon film is bonded onto the etching stopper. Therefore, it is necessary to divide this joint. Thus, the mask ⑤ is divided to form a groove 208. If the etch stopper is not provided on the amorphous silicon film, there is a risk of accidentally etching the underlying amorphous silicon region 205, because the thickness of the microcrystalline silicon region 207 is below that. This is because it is several times to several ten times or more thicker than the silicon region.

Then, the wiring 209 and the pixel electrode 210 were formed using the mask (6) and (7) by a well-known method. This state is shown in FIG. 2 (d).

However, in the above method, since a large number of masks of up to seven sheets are used, the production yield may decrease. Thus, a method of reducing the number of masks has also been proposed, as shown below. First, the gate electrode portion is patterned on the substrate using a first mask, then an insulating film is formed, and then an amorphous silicon film or a silicon nitride film (hereinafter referred to as an etching stopper) is continuously formed. Then, by exposing from the backside, only the silicon nitride film is selectively etched using the gate electrode portion as a mask to form an etching stopper self-aligning. Then, after the microcrystalline silicon film is formed thereon, a TFT region including grooves (corresponding to region 208 in FIG. 2) above the channel is formed. Then, the wirings and the electrodes are formed using the third and fourth masks. Finally, a structure equivalent to that shown in FIG. 2 (d) is obtained. In this way, by fully utilizing the self-aligning process, a complete structure can be obtained using a small number of masks, that is, three masks.

The TFT thus formed has a very severe unevenness as shown in the figure. This is mainly due to the gate electrode portion (including the oxide film 203 of the gate electrode), the etching stopper and the microcrystalline silicon region. More specifically, for example, when the thickness of the gate electrode portion is 300 nm, the thickness of the etching stopper is 200 nm, and the thickness of the microcrystalline silicon region 207 is 300 nm, unevenness as high as 800 nm is generated on the substrate.

For example, in the case of using a TFT as an active matrix circuit of a liquid crystal display panel, the thickness of a cell is generally 5 to 6 µm, and its thickness is controlled within an accuracy of 0.1 µm or less. Under such conditions, unevenness up to 1 μm in height greatly compromises the uniformity of the cell thickness.

Factors affecting thickness uniformity cannot be easily removed. For example, when the microcrystalline silicon film is formed thin, the resistances of the source and the drain become inversely high, resulting in deterioration of the characteristics of the device.

On the other hand, when the etching stopper is thin, there is a possibility that the microcrystalline silicon region is erroneously etched to the amorphous silicon region below it in the process of etching, and in such a case, the production yield decreases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described conventional problems, and one of the objects of the present invention is to simplify a semiconductor device manufacturing process. For example, the production yield is improved by reducing the number of masks compared with the conventional method. Or it aims at improving a throughput (throughput) by reducing the number of film-forming processes, and reducing cost.

Another object of the present invention is to provide a semiconductor device such as a TFT having a more flattened surface. A TFT having a flat surface not only solves the problem of using it in a liquid crystal display panel, but also solves an important technical problem in other applications. TFTs having a flattened structure can be applied to new applications, which are difficult to apply in conventional TFTs.

Another object of the present invention is to improve the characteristics of the TFT. In the TFT shown in FIG. 2, the sheet resistance of the source / drain regions is high, which adversely affects the characteristics of the TFT. Moreover, since the source / drain regions and the channel forming regions are formed of different materials, the bonding state between these regions is very poor. In addition, it is impossible to form the source / drain regions continuously after forming the channel forming region. Therefore, ideally, it is necessary to improve the junction between these regions by forming the source / drain regions and the channel forming regions by a single film in the same plane as in the MOS transistor of the semiconductor integrated circuit.

In order to solve the above problems, the present invention provides a novel method for manufacturing a TFT without using an etching stopper and a TFT manufactured by the method. That is, the resistance of the microcrystalline region (source / drain) is sufficiently lowered and the thickness thereof is made thinner. Further, in the present invention, instead of the conventional two-step process of forming an amorphous silicon region (film) serving as a channel forming region and forming a microcrystalline silicon region (film) serving as a source / drain region, a single process is employed. After the silicon film is formed, a source / drain region is formed in one portion of the silicon film and a channel forming region is formed separately in the other portion.

In order to improve the throughput, it is most important to reduce the deposition process. The film forming process not only takes time for film forming but also takes about the same time for cleaning in the film forming chamber, and in a modern semiconductor process requiring an extremely clean environment, the film forming process is performed while the film forming chamber is cleaned. It is true. Therefore, it can be seen that forming a thin film rather than forming a thick film and forming a single layer film rather than forming a multilayer film are necessary to improve the throughput. In that sense, it is preferable to reduce the film forming step.

In the TFT according to the embodiment of the present invention, a gate insulating film is formed to cover the gate electrode, and a semiconductor film is formed thereon, and a portion of the semiconductor film on the gate electrode is substantially intrinsic to function as a channel forming region. The other part of the semiconductor film, which is made of an amorphous semiconductor, is an inverted staggered TFT that functions as a source / drain region having an N type or a P type and higher order than the amorphous semiconductor in the channel forming region. An N-type or P-type semiconductor is a crystalline semiconductor exhibiting order when observed by the peak of the Raman scattering spectrum. In addition, the portion serving as the channel forming region may be amorphous, semi-amorphous, microcrystalline, polycrystalline, or may take their intermediate state. In the case where the off current is to be suppressed, it is preferable to use an amorphous semiconductor. On the other hand, the region serving as the source / drain is made of crystalline silicon having a sufficiently low resistance. In addition, this region is crystalline, and irradiates the region for a short time with intense light having a wavelength of 4 to 0.5 µm, that is, ultraviolet light, visible light, or near infrared light, which is equivalent to laser light or laser light. This improves its crystal structure. This region becomes P-type or N-type by irradiation of ultraviolet light, visible light or near infrared light, depending on the impurity introduced.

The above structure can be realized by a single semiconductor film, and it can be seen that the above process is suitable for mass production. Further, in the present invention, since the thick microcrystalline silicon film is not formed unlike the conventional process, the surface irregularities of the TFT can be reduced. Of course, the present invention does not always require the formation of an impurity region, for example, a channel formation region and a source / drain region in a single semiconductor layer. It is natural that a multi-layer structure including two or more semiconductor layers may be taken to further improve. However, also in that case, the source / drain region and the channel forming region need to be substantially in the same layer.

A TFT according to another embodiment of the present invention is characterized by not having an etching stopper on the upper portion of the channel formation region. The presence of the etch stopper is an important factor of the surface irregularities of the TFTs.

The TFT according to the present invention can be manufactured by a process schematically shown in FIGS. 1 (a) to 1 (d), but is not limited thereto, and necessary modifications can be made. As shown in FIG. 1 (a), a gate electrode 102 is patterned and formed using a mask ① on an insulating substrate 101 to be heat-resistant alkali-free glass (for example, Corning 7059 glass). If necessary, the oxide film 103 may be formed on the surface of the gate electrode to increase the insulation. Thereafter, a gate insulating film 104 is formed on the entire surface of the wafer to obtain a structure as shown in FIG. 1 (a).

Next, a silicon thin film of amorphous, semi-amorphous, microcrystalline, polycrystalline, or intermediate state thereof is formed, and patterning is performed using a mask (2) to form the semiconductor region 105. In practice, an amorphous silicon film is often formed in consideration of the film formation temperature and the off current (leak current). However, a low-temperature crystallization process such as laser annealing is further performed on the thus-obtained amorphous silicon film to form a polycrystalline or semi-amorphous silicon film. It may be formed. When polycrystalline or semi-amorphous silicon is used, the electric field mobility increases, but the off current also increases, which is not suitable for the active matrix circuit of the liquid crystal display panel.

Subsequently, a film which becomes a mask material, for example, a silicon nitride film having a lot of silicon, is formed to a thickness of 50 nm or more with respect to ultraviolet light, visible light, or near infrared light, and this is patterned using a mask (3). At this time, the photoresist may remain on the silicon nitride film. That is, in FIG. 1 (c), 106 is silicon nitride and 107 is a photoresist. Assuming the following ion implantation step, the thickness of the photoresist is 100 nm or more, preferably 500 nm or more.

In this state, impurities are selectively implanted into the semiconductor region 105 by a method such as ion implantation, ion doping, or plasma doping. Thus, the impurity region 108 is formed. However, due to the impurity implantation, the crystallinity of the semiconductor film is greatly impaired and it does not function as a semiconductor. Thus, crystallization (i.e., lamp annealing, rapid opening) (RTA) is performed by irradiating ultraviolet light, visible light, near infrared light, or laser light from the upper part to the damaged film for a short time. By this step, the ordering of the semiconductor is restored, and a state with better ordering than the state before the impurity introduction is obtained. In this lamp annealing step, by controlling the irradiation time of the light used, the temperature of the irradiated object and the atmosphere appropriately, silicon in various states can be formed from a polycrystalline state close to an extremely single crystal state to a semi-amorphous state. The crystallinity of the silicon obtained by the lamp annealing process can be confirmed by examining the scattering peaks peculiar to the crystalline silicon by Raman scattering spectroscopy.

Specifically, light from the ultraviolet region to the visible region and further to the near infrared region, preferably light having a wavelength of 4 to 0.5 μm (e.g., at a wavelength of 1.3 μm) Branch infrared light) to a relatively short time of about 10 to 1000 seconds, the crystallinity of the silicon film can be improved. Such light can be irradiated to an N-type or P-type semiconductor. The wavelength of the light used in this process is absorbed by the silicon film, but is preferably substantially not absorbed by the glass substrate. Alternatively, laser light may be irradiated onto the silicon film to improve the crystallinity of the silicon film.

Light having a wavelength in the visible range, particularly light having a short wavelength of less than 0.5 μm, can be easily absorbed by intrinsic or substantially intrinsic amorphous silicon, but in longer wavelengths of light the absorption rate of intrinsic or substantially intrinsic amorphous silicon is Lowers. On the other hand, light having a wavelength of 0.5 to 4 μm is effectively absorbed by the amorphous silicon film doped with impurities, but hardly absorbed by the glass substrate. Therefore, when light of 0.5 to 4 탆 wavelength is used, only the impurity doped region of the TFT can be effectively heated. In addition, in lamp annealing, it is needless to say that light may be irradiated from either the upper side or the board | substrate side, and may be irradiated from both sides.

In such heat treatment, the silicon film is often peeled from the substrate due to a difference in thermal expansion rate between the silicon film and the substrate or a temperature difference between the interface of the substrate / silicon film and the surface of the siliceous tree. In particular, such peeling is remarkable when the area of the film is large over the entire surface of the substrate. However, in the present invention, since the membrane is divided into a plurality of portions having a sufficiently small area, it is possible to prevent peeling of the membrane or the like. In addition, since the entire surface of the substrate is not heated through the silicon film, thermal shrinkage of the substrate can be sufficiently suppressed. In addition, in heat processing, in order to minimize the thermal effect on the board | substrate etc. by lamp annealing, it is preferable to make lamp annealing time as short as possible.

The gate electrode should be made of a material that withstands the lamp annealing process. Therefore, high melting point metals such as tantalum and titanium are preferred. In addition, aluminum is easily deformed at a high temperature, but when it is coated with an anodized film of sufficient thickness, it withstands short annealing.

According to the findings of the present inventors, in the lamp annealing step, when the sample is heated to about 250 to 500 ° C., the activation of impurities proceeds to the inside of the sample, and the impurity concentration can be sufficiently increased. Too high a temperature is not preferable for keeping the silicon in the channel formation region in an amorphous state, and a constraint is imposed on the glass substrate. Therefore, it is preferable to keep the sample at a temperature of about 250 to 350 ° C.

After doping in this manner, the silicon nitride film 106 and the photoresist 017 are removed. The silicon nitride film 106 can be left as it is. Thereafter, the metal wiring / electrode 110 and the ITO pixel electrode 111 are formed using the mask ④ and the mask ⑤ by a known method. The total number of masks required for the above process is five in total, but can be reduced to four by using the self-aligning method using the exposure technique from the back side of the gate electrode as in the prior art. Specifically, one mask is required to form the gate electrode and the semiconductor region, and two masks are required to form the pixel electrode and the wiring electrode. The silicon nitride film 106 can be patterned by performing back exposure using the gate electrode as a mask.

As is apparent from FIG. 1 (d), the TFT according to the present invention has less surface irregularities than the conventional TFT. This is because the main reason for the unevenness of the entire TFT is only the unevenness of the gate electrode portion. Since the thickness of the semiconductor region 105 is very thin and is 10 to 100 nm as in the conventional TFT, it does not contribute significantly to the unevenness.

As described above, the present invention is characterized in that the semiconductor region, that is, the source / drain region, has a sufficiently high impurity concentration and good crystallinity, so that the region can be provided very thinly. This is achieved because a lamp annealing step is used in the present invention. In addition, the etch stopper, which is indispensable in the prior art processes, may be omitted in the inventive process. Further, since the masking agent used in the process according to the present invention does not need to be left after the completion of the TFT, the unevenness can be significantly reduced in the TFT of the present invention.

Unlike the conventional TFTs, in the present invention, since the channel forming region and the source / drain regions are formed of the same film, the bonding between these regions is good, and thus the electric field mobility and sub-dhreshold characteristic values are obtained. TFT characteristics such as leakage current are improved. Impurities introduced into the source and drain can be activated by irradiating ultraviolet light, visible light or near infrared surgery.

EMBODIMENT OF THE INVENTION Below, this invention is demonstrated in detail based on an Example.

Example 1

TFT was manufactured according to the process shown in the flowchart of FIG. 1 (a) to 1 (d) show schematic cross-sectional views of the fabrication process up to the formation process of the metal wiring / electrode 110 in the TFT fabrication method according to the embodiment of the present invention. The process of forming the ITO pixel electrode 11 is not included in FIG. The gate electrode was tantalum, and in step 5, an anodization film having a thickness of about 200 nm was formed on the surface of the gate electrode to improve insulation. The anodic oxide film is made of an oxide of a material constituting the gate electrode. As the impurity doping means, an ion doping method was used. The total number of masks used in the entire process of 26 processes was 4 in total.

3 to 6, sputtering, PCVD, and RIE denote sputtering film formation, plasma CVD, and reactive ion etching, respectively. Conditions such as the film thickness and the gas used as the material are shown after the colon opportunity.

The manufacturing process of the prior art corresponding to this embodiment is shown in sectional views in FIGS. 2 (a) to 2 (d) and in process chart in FIG. The number of masks used in this process is 6 sheets in total, and the whole process consists of 29 processes. Thus, it can be seen that the process according to the invention is shortened compared to the process of the prior art.

Hereinafter, this embodiment is explained in detail according to the sectional drawing of FIG. 1 (a)-FIG. 1 (d), and the process diagram of FIG. Corning 7059 glass was used as the substrate. The substrate 101 was washed (step 1), and a tantalum film was formed thereon by a sputtering method to a thickness of 200 nm (step 2). After that, the tantalum film was patterned using a mask ① (step 3) and etched with a mixed acid of 5% nitric acid and phosphoric acid (step 4) to form a tantalum gate electrode 102. Then, anodization was performed by applying a current to the gate electrode, and the voltage was raised up to 120V, whereby anodization film 103 was formed to a thickness of 200 nm (step 5). Details of the anodic oxidation process are described in Japanese Patent Application Nos. Hei 3-237100 and Hei 3-238713, and will not be described in detail here.

Thereafter, the resist was removed (peeled) (step 6), and a silicon nitride film 104 having a thickness of 200 nm was formed by plasma CVD as a gate insulating film (step 7). The substrate temperature at this time was 300 degreeC. After the substrate was cleaned (step 8), an amorphous silicon film having a thickness of 30 nm was formed by plasma CVD (step 9). The substrate temperature at this time was 300 degreeC.

Then, the amorphous silicon film was patterned by using the mask (2) (step 10), and the amorphous silicon film was etched by the reactive ion etching method using CF ₄ as the reaction gas (step 11) to form a semiconductor region 105. The remaining resist was removed (step 12), and the substrate was washed (step 13).

Thereafter, a silicon nitride film having a thickness of 200 nm was formed by plasma CVD (step 14). The substrate temperature at this time was 300 degreeC. Then, the silicon nitride film was patterned by the mask ③ (step 15), and the silicon nitride film was etched with a buffer hydrofluoric acid (buffered hydrofluoric acid) (step 16) to form a silicon nitride mask 106. The resist 107 of approximately 500 nm thickness remained on the silicon nitride mask.

Subsequently, phosphorus ions were introduced at a dose of 3 x 10 ¹⁵ cm ^-2 at an acceleration energy of 10 keV by the ion doping method (step 17) to form an impurity region 108. Thereafter, the substrate was prepared (step 18), and the remaining resist was removed (step 19).

Thereafter, lamp annealing was performed using a halogen tungsten lamp (step 20), and the silicon nitride mask 106 was etched and removed with a buffer hydrofluoric acid (step 21). In the lamp annealing step (step 20), the intensity of ultraviolet light, visible light, or near infrared light is adjusted so that the temperature on the single crystal silicon wafer of the monitor is in the range of 800 to 1300 ° C, typically 900 to 1200 ° C. More specifically, the temperature of the thermocouple embedded in the silicon wafer was monitored and the signal thus obtained was fed back to the infrared light source. The temperature rise and fall at this time were performed according to the figure shown in FIG. 7 (a) or 7 (b). The heating rate at the time of temperature rising was constant in the range of 50-200 degreeC / sec. The temperature drop was performed by natural cooling, and thus the cooling rate was 20 to 100 ° C / sec.

7 (a) shows a general temperature cycle comprising a heating step a, a holding step b and a cooling step c. In this case, however, since the sample is rapidly heated and cooled from room temperature to a high temperature of about 1000 ° C., and then from a high temperature state to room temperature, the effect of the heating and cooling steps on the silicon film and the substrate is large, and the silicon film is peeled off. It's very likely.

In order to solve this problem, as shown in Fig. 7 (b), a preheating step d or a postheating step f before or after the holding step e is carried out so that the substrate or the film does not significantly affect the temperature of 200 to 250 ° C. It is preferable to keep the substrate at a temperature of. In addition, the lamp annealing is carried out in a H ₂ atmosphere. Of 0.1 to 10% in H ₂ atmosphere, the hydrogen chloride, other hydrogen halide, or fluorine, may be incorporated into a compound of chlorine or canceled. Thereafter, the substrate was washed (step 22).

Thereafter, an aluminum film was formed to a thickness of 400 nm by the sputtering method (step 23), and the aluminum wiring was patterned using the mask (4) (step 24). Next, the aluminum film was etched by the mixed acid (step 25) to form the aluminum wiring 100. Then, the remaining register was removed (step 26). Finally, annealing was performed at 350 ° C. for 30 minutes in a hydrogen atmosphere of 1 atm.

In particular, in this embodiment, it is important to neutralize dangling bonds formed in a lamp annealing process using ultraviolet light, visible light or near infrared light by heating to 250 to 400 ° C. in a hydrogen atmosphere in a subsequent step. Do. Through the above steps, an N-channel TFT was completed.

Example 2

TFTs were fabricated in accordance with the fabrication process shown in FIG. The fabrication process of this embodiment is essentially the same as that shown in FIGS. 1 (a) to 1 (d), except that the exposure technique from the back side is used in this embodiment. As in the case of Example 1, FIG. 4 shows up to the metal wiring and electrode 110 formation process. The gate electrode is aluminum, and on the surface of the gate electrode, an anodization film having a thickness of about 200 nm was formed in step 5 to improve insulation. The exposure technique from the back side was used for the formation of the silicon nitride mask, and the ion doping method was used for the introduction of impurities. The number of masks used in this process was reduced to three by using the back exposure technique. The whole process consists of 26 processes.

The prior art process corresponding to this embodiment is shown in FIG. 6, where the number of masks used is three, and the whole process consists of 23 processes. In the process according to the present embodiment shown in FIG. 4, the total number of steps is increased, but the number of film forming steps for limiting the throughput (throughput) is five, which is less than the six steps of the prior art shown in FIG. The productivity is improved.

Hereinafter, the present embodiment will be described in detail with reference to FIGS. 4 and 1 (a) to 1 (d). Corning 7059 glass was used as the substrate. The substrate 101 was cleaned (step 1), and an aluminum film was formed thereon by a sputtering method to a thickness of 400 nm (step 2). Thereafter, the aluminum film was patterned using a mask ① (step 3), and then etched with a mixed acid of 5% nitric acid and phosphoric acid (step 4) to form a gate electrode 102. Then, anodization was performed by applying a current to the gate electrode, and the voltage was raised up to 120V to form anodic oxide film 103 having a thickness of 200 nm (step 5).

Thereafter, the resist was removed (step 6), and the silicon nitride film 104 was formed to a thickness of 200 nm by the plasma CVD method (step 7) as a gate insulating film. The substrate temperature at this time was 300 degreeC. After the substrate was cleaned (step 8), an amorphous silicon film having a thickness of 30 nm was formed by plasma CVD (step 9). The substrate temperature at this time was 300 degreeC.

Then, the amorphous silicon semiconductor region is patterned using a mask (2) (step 10), and the amorphous silicon film is etched by a reactive ion etching method using CF ₄ gas as a reaction gas (step 11), thereby forming the semiconductor region 105. Formed. The remaining resist was removed (step 12), and the substrate was washed (step 13).

Thereafter, a silicon nitride film having a thickness of 200 nm was formed by plasma CVD (step 14). The substrate temperature at this time was 300 degreeC. Then, the substrate is exposed from the back side of the substrate in the state where the resist is applied, the silicon nitride mask is patterned in a self-aligned manner with the gate electrode as a mask (step 15), and the silicon nitride film is etched with a buffer hydrofluoric acid (step 16), thereby producing a silicon nitride mask. (106) was formed. The resist 107 of about 500 nm thickness remained on the silicon nitride mask.

Subsequently, phosphorus ions were introduced at a dose of 2 x 10 ¹⁵ cm ^-2 at an acceleration energy of 10 keV by the ion doping method (step 17) to form an impurity region 108. Thereafter, the substrate was washed (step 18), and the remaining resist was removed (step 19).

Thereafter, annealing was performed with a halogen tungsten lamp (step 20), and the silicon nitride mask 106 was etched and removed with a buffer hydrofluoric acid (step 21). The conditions of the lamp annealing were the same as in Example 1. Thereafter, the substrate was washed (step 22).

Thereafter, an aluminum film is formed to a thickness of 400 nm by sputtering (step 23), the aluminum wiring is patterned using a mask (4) (step 24), and the aluminum film is further etched with a mixed acid (step 25), and the aluminum wiring The electrode 110 was formed. Then, the remaining resist was removed (step 26). Finally, annealing was performed at 350 ° C. for 30 minutes in a hydrogen atmosphere of 1 atm. Through the above process, an N channel type TFT was produced.

As described above, the present invention is not only characterized by the simplification of the process, but also because the sheet resistance of the source / drain regions is small, it is possible to provide a high quality TFT having a low threshold voltage and capable of high speed operation. Accordingly, the present invention is an industrially advantageous invention.

Claims (19)

An insulated gate semiconductor device of an inverted staggered MIS semiconductor device provided on an insulated substrate, comprising: a channel forming region of substantially intrinsic amorphous semiconductor; And source and drain regions made of an N-type or P-type semiconductor having higher order than the amorphous semiconductor, wherein the N-type or P-type semiconductor is irradiated with ultraviolet light, visible light or near infrared light. Gate type semiconductor device. The insulated gate semiconductor device according to claim 1, further comprising a gate electrode coated with an insulator made of an oxide of a material constituting the gate electrode. The insulated gate semiconductor device of claim 2, wherein the gate electrode comprises tantalum. The insulating gate type semiconductor according to claim 1, wherein the channel forming region and the source and drain regions are provided in a single semiconductor film. The insulated gate semiconductor device according to claim 1, wherein the channel forming region and the source and drain regions are provided as two or more semiconductor layers. The insulated gate semiconductor device according to claim 2, wherein said insulator made of an oxide of a material constituting said gate electrode is an anode oxide. Forming a gate electrode on the substrate; Forming a gate insulating film on the gate electrode; Forming an amorphous or polycrystalline semiconductor film on the gate insulating film, and providing a mask material on the semiconductor film; Introducing an impurity into the semiconductor film using the mask material as a mask; And imparting order to the semiconductor film by irradiating ultraviolet light, visible light, or near infrared light to the semiconductor film. 8. The method of claim 7, wherein a source region, a drain region, and a channel forming region are formed in the semiconductor film. 8. The method of claim 7, wherein the ultraviolet light, the visible light or the near infrared light is absorbed by the semiconductor film. 8. A method according to claim 7, wherein a wavelength of 0.5 to 4 m is used for irradiation of the ultraviolet light, the visible light or the near infrared light. 8. The method of manufacturing an insulated gate semiconductor device according to claim 7, wherein said substrate is heated to a temperature of 250 to 500 캜 during said light irradiation. Forming a gate electrode on the substrate; Forming a gate insulating film on the gate electrode; Forming an amorphous or polycrystalline semiconductor film on the gate insulating film; Providing a mask material on the semiconductor film; Introducing an impurity into the semiconductor film using the mask material as a mask; And irradiating at least a portion of the semiconductor film with ultraviolet light, visible light, or near infrared light to modify at least a portion of the semiconductor film into a P-type or N-type conductive type according to the introduced impurities. Type semiconductor manufacturing method. 13. The method of claim 12, wherein a source region, a drain region, and a channel forming region are formed in the semiconductor film. 13. The method according to claim 12, wherein the ultraviolet light, the visible light or the near infrared light is absorbed by the semiconductor film. 13. A method according to claim 12, wherein a wavelength of 0.5 to 4 m is used for irradiation of the ultraviolet light, the visible light or the near infrared light. The method of claim 12, wherein the substrate is heated to a temperature of 250 to 500 ° C. during the light irradiation. Forming a gate electrode on the substrate; Forming a gate insulating layer on the gate electrode, and forming a semiconductor film on the gate electrode with the gate insulating layer interposed therebetween; Forming source and drain regions in the semiconductor film by introducing impurities into a portion of the semiconductor film; And irradiating ultraviolet light, visible light, or near-infrared to activate the introduced impurity. An insulated gate insulated gate type semiconductor device of an inverted staggered MIS type semiconductor device provided on an insulated substrate, comprising: a channel forming region of substantially intrinsic amorphous semiconductor, and an N-type semiconductor having higher order than that of the amorphous semiconductor. A source and drain region, wherein the channel formation region and the source and drain region are provided in a single semiconductor film, and ultraviolet light, visible light, or near infrared light is irradiated to the N-type or P-type semiconductor. An insulated gate semiconductor device. An insulated gate semiconductor device of an inverted staggered MIS semiconductor device provided on an insulated substrate, comprising: a channel forming region of substantially intrinsic amorphous semiconductor; A source and drain region made of an N-type or P-type semiconductor having higher order than that of the amorphous semiconductor, wherein light having a wavelength of 4 to 0.5 μm is irradiated to the N-type or P-type semiconductor. Insulated gate semiconductor device.