JPH04269837A - Manufacture of thin-film transistor - Google Patents

Abstract

PURPOSE:To reduce a photomask and a manufacturing process by a method wherein the pattern of a channel protective film is formed by the rear exposure operation of a gate electrode, ions are implanted into a semiconductor layer, a contact layer is formed and the pattern of the contact layer is formed simultaneously by using a resist used to form the pattern of a source electrode. CONSTITUTION:Ta is deposited on a glass substrate 1; the pattern of a gate electrode 2 is formed by using a photomask. Then, a gate insulating film 3, an amorphous silicon layer 4 and a channel protective film 5 are deposited sequentially on the whole surface of the substrate 1 so as to cover the gate electrode 2. Then, the protective film 5 is coated with a resist 10; the rear exposure operation of the gate electrode is executed. In succession, the resist 10 is developed; after that, an etching operation is performed by making use of the remaining resist 10; the prescribed protective film 5 is obtained. Without stripping a resist 11, P<+> ions are implanted from the upper part of the protective film 5; contact layers 6a, 6b are formed. In addition, the resist 11 is stripped; after that, metal layers 7, 8 are formed on the whole surface of the substrate 1.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing thin film transistors, which are switching elements suitable for active matrix substrates used in shutter arrays, liquid crystal display devices, EL display devices, and the like.

0002

2. Description of the Related Art FIG. 5 shows a cross-sectional view of a conventional thin film transistor, and FIG. 6 is a cross-sectional view illustrating a method of manufacturing a thin film transistor by a conventional ion implantation method.

As shown in FIG. 6(I), a gate electrode 2 is patterned on a glass substrate 1, and then the gate electrode 2 is patterned on a glass substrate 1.
A gate insulating film 3 is formed thereon, and then a semiconductor layer 4 is formed on the gate insulating film 3 above the gate electrode 2. A channel protective film 5 is patterned on the semiconductor layer 4 using photolithography and etching. Note that in this photolithography method, exposure is performed from above the resist formed on the channel protective film. From above the channel protective film 5 from which this resist has been removed, as shown by the arrow in FIG.
Ion implantation is performed to form contact layers 6a and 6b.

Furthermore, as shown in FIG. 6 (II), the contact layers 6a and 6b are patterned in contact with the semiconductor layer 4 using a photolithography method, and then an electrode 7 and a drain electrode 8 are formed. A pattern is formed using a photolithography method or the like, and as shown in FIG. 5, contact layers 6a and 6b are electrically connected to a source electrode 7 and a drain electrode, respectively.

In this way, the gate electrode 2, the gate insulating film 3,
A thin film transistor is constituted by the semiconductor layer 4, contact layers 6a, 6b, channel protection film 5, source electrode 7, and drain electrode 8. Furthermore, a pattern is formed so that the picture element electrode 9 is electrically connected to the drain electrode 8, thereby forming an active matrix substrate. A plan view of this active matrix substrate is shown in FIG. 7. In this figure, the picture element electrode 9 is shown by a dashed line, and the cross-sectional view taken from the cutting line II in FIG. FIG.

[0006]

[Problems to be Solved by the Invention] Recently, HD
2. Description of the Related Art Large-capacity, high-density active matrix display devices aimed at TVs, graphic displays, and the like are being actively developed and put into practical use. Such display devices require large area,
It is necessary to simplify the manufacturing method in order to realize large capacity, high density, and reduce the defective rate during production. In other words, it is better to reduce the number of photomasks and exposure processes as much as possible.

However, in the case of the manufacturing method of a thin film transistor (hereinafter abbreviated as TFT) as shown in FIG. Six sheets and six patterning processes are required.

The present invention was made to simplify the manufacturing process of TFTs, and more specifically, the purpose of the present invention is to simplify the manufacturing process by using an ion implantation method and a backside exposure method. An object of the present invention is to provide a method for manufacturing a thin film transistor.

[0009]

[Means for Solving the Problems] The present invention provides a gate electrode, a gate insulating film, a semiconductor layer, a contact layer located on both sides thereof, a channel protective film, and electrically connected to at least the contact layer on a transparent insulating substrate. In a method of manufacturing a thin film transistor having a source electrode and a drain electrode, a resist formed above the gate electrode on a transparent insulating substrate through at least a gate insulating film, a semiconductor layer, and a channel protective film is provided by the gate electrode. A first step of patterning by backside exposure, a second step of patterning a channel protective film using the resist patterned in the step, and a step of patterning the channel protective film while leaving at least the channel protective film. and a third step of implanting ions into the semiconductor layer from above to form a contact layer, thereby achieving the above object.

Furthermore, the present invention achieves the above object by including a fourth step of patterning a contact layer using a resist used in patterning the source electrode and gate electrode after the third step. . Furthermore, the present invention achieves the above object by forming a contact layer by implanting ions into the semiconductor layer from above the resist while leaving the resist used for patterning the channel protective film in the third step. can be achieved.

[0011]

[Operation] According to the above process of the present invention, the patterning of the channel protective film is performed by backside exposure using the gate electrode, so the gate electrode plays the role of a photomask, so the photomask can be omitted. .

After the contact layer is formed by ion implantation into the semiconductor layer, the contact layer is simultaneously patterned using the resist used in forming the source electrode pattern, so that the pattern for forming the source electrode is changed to the contact layer. Because it is used in conjunction with the pattern for pattern formation, one photomask can be omitted and the patterning process can also be omitted.

Furthermore, according to the above process, it is not necessary to consider margins due to misalignment during patterning in the design, so it is possible to increase the definition of the pattern.

[0014] Furthermore, by performing ion implantation while leaving the resist on the channel protective film, the amount of ions implanted into the channel protective film is greatly reduced or almost eliminated compared to the case without the resist. This also makes it possible to prevent current leakage between the source electrode and drain electrode that will be formed later.

[0015]

[Embodiment] FIG. 1, FIG. 2, and FIG. 3 show cross-sectional views illustrating an embodiment of the method for manufacturing a thin film transistor of the present invention.
An active matrix substrate on which thin film transistors shown in FIG. 4 are formed is formed through the steps shown below.

As shown in FIG. 1(I), Ta is deposited on a glass substrate 1 to a thickness of 2000 Å to 40 Å by sputtering.
The gate electrode 2 is deposited to a thickness of 00 Å, for example, 3000 Å, and a gate electrode 2 is patterned using a photomask. Next, a film of SiNx with a thickness of 2000 Å to 2000 Å is deposited on the entire surface of the substrate 1, covering the gate electrode 2, by plasma CVD.
A gate insulating film 3 with a thickness of 5000 Å, for example 3000 Å, an amorphous silicon (hereinafter referred to as "a-Si") layer 4 and a Si layer with a thickness of 200 Å to 500 Å, for example 300 Å.
Nx with a thickness of 1000 Å to 3000 Å, e.g. 20
A channel protective film 5 having a thickness of 0.00 Å is deposited in this order.

Next, a resist 10 is formed on the channel protective film 5.
is applied to expose the back side of the gate electrode. This backside exposure is performed from below the glass substrate 1 as shown by the arrow in FIG.
Since exposure is performed with light that passes through the a-Si layer 4 and the channel protective film 5, the amount of exposure is increased compared to the conventional case of performing from above the resist 10 as shown in FIG. 6(I), and proper exposure can be achieved. It is necessary to take care to ensure that

Here, the resist 10 is a commonly used positive resist (a resist whose portions exposed to light are dissolved by development). The thickness of the gate electrode 2 is selected to be a value necessary to block light from backside exposure, and in the above example, the thickness of the gate voltage is set to 3000 Å.

By developing this resist 10,
The exposed part is dissolved by backside exposure, and as shown in Fig. 1 (II)
As shown in the figure, a predetermined shape appears.

Next, by etching using the resist 10, a channel protective film 5 patterned as shown in FIG. 2(I) is obtained. In addition, this figure 2 (
In I), the shape of the resist 10 may become somewhat smaller due to the influence of etching, so to indicate this, it is also written as (11) here, and will be referred to as the resist 11 hereinafter.

Next, as shown by the arrow in FIG. 2 (II), P+ ions are implanted from above the channel protective film 5 patterned as described above without peeling off the resist (implantation mask) 11. , forming contact layers 6a and 6b. The contact layers 6a and 6b are formed from regions of the a-Si layer 4 into which P+ ions are implanted. During this ion implantation, resist 1
1 is left when there is no resist 11 (Figure 6 (
Compared to I)), the number of P+ ions implanted into the channel protective film 5 is reduced, and electrical leakage between the source electrode 7 and the drain electrode 8, which will be described later, can be reduced. This causes a minute current to flow between the source electrode 7 and drain electrode 8 when P+ ions are implanted into the channel protective film 5, but if the resist 11 is left as described above during ion implantation, the resist This is because the number of P+ ions implanted into the channel protective film 5 can be reduced compared to the case where the channel protection film 11 is not provided.

After that, the resist 11 is peeled off and then sputtered to form a film with a thickness of 2000 Å to 40 Å as shown in FIG. 3(I).
Metal layers 7 and 8 of Ti or Mo with a thickness of 00 Å, for example, Mo with a thickness of 2000 Å, are formed on the entire surface of the glass substrate 1.

Furthermore, this metal layer and the contact layer were patterned using a photomask to obtain a source electrode 7, a drain electrode 8, and contact layers 6a and 6b as shown in FIG. 3(II). In addition, at this time, the source bus wiring 7
′ is also patterned at the same time. When forming this pattern, a photolithography method is used, and one exposure process is sufficient. That is, first, a resist is applied, then exposed using a photomask, then developed, and then etched to pattern not only the metal layer but also the contact layer at the same time, resulting in contact with the source electrode 7 and drain electrode 8. Layers 6a and 6b are obtained. As a result, not only does one photomask (exposure mask) suffice, but when the source and drain electrodes and the contact layer are patterned separately as in the past, the source and drain electrodes can be placed on the contact layer. Alignment of exposure mask for
can also be omitted. Regarding etching, for example, wet etching (fluoro-nitric acid) or dry etching (carbon tetrachloride) can be used to simultaneously etch the source electrode, drain electrode, and contact layer.Here, we used dry etching, which is preferable for accuracy. . Note that it is sufficient if the thickness of the resist is 1 μm or more.

As described above, a thin film transistor having the cross-sectional structure shown in FIG. 3 (II) was formed.
), the electrical leakage between the source electrode 7 and the drain electrode 8 is small, and the source electrode 7
Since the contact layer 6a also exists under the source bus wiring 7' which is continuous with the source bus wiring 7', disconnection is unlikely to occur.

Furthermore, a transparent film made of indium tin oxide (ITO) is deposited to a thickness of 500 Å to 1000 Å, for example 800 Å, on the entire surface of the glass substrate 1 on which the thin film transistor is formed as described above. Next, patterning is performed using a photomask as shown in FIG. 4A to form picture element electrodes 9 to obtain an active matrix substrate. 4(A) and 4(B) show a plan view of the active matrix substrate and a sectional view taken along cutting line II in FIG. 4(A). As shown in FIG. 4A, the thin film transistors and picture element electrodes 9 are arranged in a matrix in correspondence with the gate bus wiring 2' connected to the gate electrode 2 and the source bus wiring 7' connected to the source electrode 7. .

In the embodiments of the present invention, an a-Si layer is used as the semiconductor layer, but it is not limited to this, and polycrystalline silicon or the like may of course be used.The material and structure of the thin film transistor are not limited to the above example, but may be any conventional material. It will be understood that the materials and structures suggested can be used.

[0027]

[Effects of the Invention] According to the method for manufacturing a thin film transistor of the present invention, photomasks for the channel protective film and the contact layer are not required, so not only the number of photomasks is reduced, but also the exposure process is reduced. It is possible to improve practicality by reducing the manufacturing process. Furthermore, since misalignment during patterning can be prevented, there is also the effect that a high-definition thin film transistor can be easily obtained.

[Brief explanation of the drawing]

FIGS. 1 (I) and (II) are cross-sectional views illustrating a method for manufacturing a thin film transistor of the present invention.

FIGS. 2(I) and (II) are cross-sectional views illustrating the method for manufacturing a thin film transistor of the present invention.

FIGS. 3(I) and (II) are cross-sectional views illustrating the method for manufacturing a thin film transistor of the present invention.

FIGS. 4A and 4B are a plan view of an active matrix substrate having a thin film transistor manufactured using the thin film transistor manufacturing method of the present invention, and I of the plan view;
It is a sectional view along the -I cutting line.

FIG. 5 is a cross-sectional view of a thin film transistor manufactured using a conventional thin film transistor manufacturing method.

FIGS. 6(I) and (II) are cross-sectional views illustrating a conventional method for manufacturing a thin film transistor.

FIG. 7 is a plan view of an active matrix substrate having thin film transistors manufactured by a conventional manufacturing method.

[Explanation of symbols]

1 Glass substrate 2 Gate electrode 3 Gate insulating film 4 Semiconductor layer (amorphous silicon layer) 5 Channel protective film 6a, 6b Contact layer 7 Source electrode 8 Drain electrode 10 Resist 11 Resist (implantation mask)

Claims (3)

[Claims] 1. A gate electrode, a gate insulating film, a semiconductor layer, a contact layer located on both sides thereof, a channel protective film, and a source electrode and a drain electrode electrically connected to at least the contact layer on a transparent insulating substrate. In the method for manufacturing a thin film transistor, a resist formed above a gate electrode on a transparent insulating film substrate through at least a gate insulating film, a semiconductor layer, and a channel protective film is patterned by backside exposure using the gate electrode. a first step, a second step of patterning a channel protective film using the resist patterned in the step, and ion ions into the semiconductor layer from above the channel protective film while leaving at least the channel protective film. A method for manufacturing a thin film transistor, comprising a third step of performing implantation to form a contact layer. 2. The manufacturing method according to claim 1, further comprising, after the third step, a fourth step of patterning a contact layer using a resist used in patterning at least one of a source electrode and a gate electrode. A method for manufacturing a thin film transistor characterized by: 3. In the manufacturing method according to claim 1, the third step is to form a contact layer by implanting ions into the semiconductor layer from above the resist while leaving the resist when patterning the channel protective film. 1. A method for manufacturing a thin film transistor, the method comprising: