KR950003939B1 - Making method of active matrix substrante - Google Patents

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Description

Method for manufacturing active mattress substrate

1 is a series of cross-sectional views illustrating a method of manufacturing an active matrix substrate in accordance with embodiments of the present invention. FIGS. 1A-1D, 2, 3A, 3B, 4A, 4B, 5-8 are FIGS.

FIG. 2 is a sectional view showing an active matrix substrate manufactured by the method of FIG.

1, 3A and 3B are cross-sectional views illustrating a method of manufacturing an active matrix substrate according to another embodiment of the present invention.

4A and 4B are cross-sectional views illustrating a method of manufacturing an active matrix substrate according to another embodiment of the present invention.

5 is a cross-sectional view showing an active matrix substrate manufactured by the method shown in FIG.

6 is a cross-sectional view showing an active matrix substrate manufactured by another method of the present invention.

FIG. 7 is a cross-sectional view showing the active matrix substrate shown in FIG.

FIG. 8 is an enlarged view showing the contact layer of the active matrix substrate shown in FIG.

9 is a sectional view showing a contact layer manufactured by a known method.

10 is a sectional view showing a contact layer of an active matrix substrate manufactured by a known method.

11 is a plan view showing an active matrix substrate manufactured by another method of the present invention.

12 is a cross-sectional view taken along the line A-A shown in FIG.

FIG. 13 is a cross-sectional view showing a method of manufacturing the active matrix substrate shown in FIG.

14 is a plan view showing an active matrix substrate manufactured by another method of the present invention.

FIG. 15 is a cross-sectional view taken along the line B-B shown in FIG.

FIG. 16 is a cross-sectional view showing a method of manufacturing the active matrix substrate shown in FIG. FIG. 17 is a flowchart of manufacturing the active matrix substrate shown in FIG.

18 is a plan view showing an active matrix substrate manufactured by another method of the present invention.

19 is a cross-sectional view taken along the line C-C shown in FIG.

20A to 20D are a series of cross sectional views showing a method of manufacturing the active matrix substrate shown in FIG.

21 is a plan view showing an active matrix substrate manufactured by another method of the present invention.

FIG. 22 is a cross-sectional view taken along the line D-D shown in FIG.

23A to 23D are a series of active matrices shown in FIG.

24 is a cross-sectional view taken along the line E-E shown in FIG.

25 is a plan view showing an active matrix substrate manufactured by another method of the present invention.

FIG. 26 is a cross sectional view taken along the line F-F shown in FIG.

27 is a plan view showing an active matrix substrate manufactured by another method of the present invention.

28A and 28B are cross-sectional views showing a method of manufacturing an active matrix substrate by another method of the present invention.

29A and 29B are cross sectional views continuing from FIG. 28;

30A and 30B are cross sectional views continuing from FIG. 29;

FIG. 31A is a plan view showing an active matrix substrate manufactured by the method of FIGS. 28-30.

FIG. 31B is a cross-sectional view taken along the line I-I of FIG. 31A.

32A and 32B are cross sectional views showing a method of manufacturing a conventional active matrix substrate.

33 is a cross sectional view showing a conventional active matrix substrate manufactured by the method shown in FIG.

34A and 32B are cross-sectional views showing a method of manufacturing another conventional active matrix substrate.

FIG. 35 is a sectional view showing a conventional active matrix substrate manufactured by the method shown in FIG.

36 is a cross sectional view used to describe the problem of the prior art.

* Explanation of symbols for the main parts of the drawings

1,21,31: glass substrate 2,24,34: gate electrode

3,23,33: gate insulating layer 4,22,32: semiconductor layer

5: channel protective layer 6a, 6b: contact layer

7,25a: source electrode 8,25b: drain electrode

11: resist 10: pixel electrode

27,37: gate electrode wiring 28: source electrode wiring

The present invention relates to a method of manufacturing an active matrix substrate for use in a liquid crystal display device.

As is well known in the art, an active matrix substrate has a relatively large single substrate having a plurality of gate buses and source buses arranged in a matrix and a pixel electrode formed in an area surrounded by the gate meet source bus, where the pixel electrode is a gate. It is driven by a thin film transistor (TFT) disposed near the junction of the bus and the source bus. The TFT is electrically connected to the gate electrode and the source electrode connected to the gate bus, and the drain electrode is connected to the source bus to which the pixel electrode is electrically connected.

A typical example of manufacturing a known active matrix substrate will be described with reference to FIGS. 32A and 32B.

As shown in FIG. 32A, the gate electrode 102 is formed on the glass substrate 101, and the gate insulating layer 103 is formed thereon. The semiconductor layer 104 is formed on the gate insulating layer 103. The channel protection layer 105 is patterned on the semiconductor layer 104 in the region corresponding to the gate electrode 102. Finally, P ⁺ ions are implanted to form contact layers 106a and 106b in the semiconductor layer 104.

Unnecessary portions of the contact layers 106a and 106b are removed by photolithography and etching to pattern the contact layers 106a and 106b shown in FIG. 32B. 33 shows a final state in which the source electrode 107 and the drain electrode 108 are patterned.

The substrate 101 is completely covered with an interlayer insulating layer 109 having a contact hole 111, through which the pixel electrode is electrically connected to the drain electrode 108. In this way, an active matrix substrate is obtained.

Known active matrix substrates of this type are susceptible to damage when regions around contact layers 106a and 106b implant P ⁺ ions into semiconductor layer 104 to form these layers, and these regions tend to diffuse carriers. Has the disadvantage of having.

In particular, in FIG. 33, when the insulating layer 103 located in the region where the gate electrode 102 and the source electrode 107 overlap each other or the region where the gate electrode 102 and the drain electrode 108 overlap each other is damaged. Because of the electrons being trapped in the gate insulating layer 103, the shift of the threshold voltage, which may occur, does not achieve the desired transistor characteristics of the TFT. This results in unstable operation.

One proposal to solve this problem is to doping under a low acceleration voltage to prevent impurities from reaching the gate insulating layer 103 during P ⁺ ion implantation, as shown in FIG. However, under this method, as shown in FIG. 34A, the semiconductor layer 104 has contact layers 106a and 106b that do not reach the gate insulating layer 103. If such a semiconductor layer 104 is patterned as shown in FIG. 34B, contact layers 106a and 106b are not formed on the side of the semiconductor layer 104. As shown in FIG. 35, when the source electrode 107 and the drain electrode 108 are formed on the contact layers 106a and 106b, between the contact layer 106a and the source electrode l07 and between the contact layer 106b and the drain. Electrical leakage may occur between the electrodes 1008, thereby degrading transistor characteristics.

This known method also has the disadvantage that impurities are diffused into the channel protective layer 105 when P ⁺ ions are implanted onto the patterned protective layer 105. Impurities in the channel protective layer degrade transistor characteristics by causing current to leak between the contact layer 106a and the source electrode 107 and between the contact layer 106b and the drain electrode 108.

Another problem is that the semiconductor layer 104 and the source electrode 107 are located too close to each other so that one end of the channel protection layer 105 is only sandwiched between them, as shown in FIG. Similarly, the drain electrode 108 of the semiconductor layer 104 is positioned too close to each other such that the other end of the channel protective layer 105 is only sandwiched between them. As a result, electric leakage is likely to occur between the source electrode 107 and the drain electrode 1008, resulting in malfunction of the display operation. Such leakage tends to occur and continue in the area indicated by the arrow in FIG. 36, since the contact layers 106a and 106b are absent in this area.

Recently, large-capacity active matrix display devices for use in high-definition TV sets, graphic display devices, and the like have been developed and used. Known TFTs cannot be used in such high capacity active matrix display devices because of the electrical leakage of 10 ^-9 to 10 ^-1 A A.

In order to prevent the occurrence of electrical leakage, Japanese Patent Laid-Open No. 3-4566 discloses a TFT having a structure in which a contact layer having low concentration of impurities is formed by implanting ions between a semiconductor layer and a source electrode and between a semiconductor layer and a drain electrode. Was released. Such a TFT structure has the advantage of eliminating the non-linear current generated by the contact between the semiconductor layer and the electrode constituting the source region or the drain region of the transistor and the off current generated by the hole and electron flow caused by the irradiation of the semiconductor layer. Have This shortens the channel of the TFT, while increasing the number of photomasks and processes, resulting in poor production yield and reliability.

The present invention relates to a method of manufacturing an active matrix substrate which overcomes the above and other disadvantages and deficiencies of the prior art. The active matrix substrate of the present invention includes a gate electrode on an insulating substrate covered with a gate insulating layer, a semiconductor layer on a gate insulating layer, a channel protective layer on a semiconductor layer, the gate insulating layer, a semiconductor layer, and a channel protective layer therebetween. A thin film transistor is used having a drain electrode having a portion overlying a gate electrode and a source electrode having a portion overlying the gate electrode with the gate insulating layer, the semiconductor layer and the channel protective layer interposed therebetween. The method of the present invention for manufacturing such an active matrix substrate includes the steps of patterning a channel protective layer and implanting ions into a semiconductor layer by using a resist film as an implantation mask after pattern formation of the channel protective layer to form a contact layer. Include.

In a preferred embodiment, the contact layer is formed by patterning the semiconductor layer.

In a preferred embodiment, a resist is formed on the channel protective layer by patterning, ions are implanted into the semiconductor layer by using a resist film as an implantation mask, and the resist is removed to pattern the drain and source electrodes.

In an alternative embodiment, the thin film transistor has a gate electrode on an insulating substrate covered with a gate insulating layer, a semiconductor layer on the gate insulating layer, and a portion to be placed on the gate electrode with the gate insulating layer and the semiconductor layer interposed therebetween. A source electrode having a drain electrode and a source electrode having a portion to be placed on the gate electrode with the gate insulating layer and the semiconductor layer interposed therebetween, a method for manufacturing an active matrix substrate is to pattern a resist on the semiconductor layer and as an injection mask. By using a resist film, ions are injected into the semiconductor layer to form a contact layer, and a conductive layer used for the drain electrode and the source electrode is formed without removing the resist, and the drain electrode and the source electrode are formed separately by removing the resist. Including the steps of

In an alternative embodiment, the thin film transistor comprises a gate electrode on an insulating substrate covered with a gate insulating layer, a semiconductor layer on the gate insulating layer, a channel protective layer on the semiconductor layer, the gate insulating layer, a semiconductor layer and a channel protective layer. An active matrix substrate is produced, having a drain electrode having a portion sandwiched over the gate electrode, and a source electrode having a portion sandwiched over the gate electrode with the gate insulating layer, the semiconductor layer, and the channel protective layer interposed therebetween. The method includes patterning the channel protective layer and implanting ions into the semiconductor layer using the patterned channel protective layer as a mask to form a contact layer.

In a preferred embodiment, the contact layer is formed by implanting ions under an accelerating voltage so that impurities do not reach the gate insulating layer.

In a preferred embodiment, ions are implanted such that the contact layer has the same thickness as the semiconductor layer.

As an alternative embodiment, the gate electrodes on the insulating substrate, all of which are covered with a gate insulating layer, with the semiconductor layer over the gate insulating layer, the channel protective layer over the semiconductor layer, the gate insulating layer and the semiconductor layer and the channel protective layer interposed therebetween. Manufacture of an active matrix substrate using a thin film transistor having a drain electrode having a portion overlying a low gate electrode and a source electrode having a portion overlying the gate electrode with the gate insulating layer, a semiconductor layer, and a channel protective layer interposed therebetween. To this end, the method includes implanting ions into the semiconductor layer through the channel protection layer such that a contact layer is formed at a portion of the semiconductor layers just below the edges of the inclined sides of the trapezoidal channel protection layer.

In an alternative embodiment, the thin film transistor comprises a gate electrode on an insulating substrate covered with a gate insulating layer, a semiconductor layer on the gate insulating layer, a channel protective layer on the semiconductor layer, the gate insulating layer, a semiconductor layer and a channel protective layer. An active matrix substrate is produced, having a drain electrode having a portion sandwiched over the gate electrode, and a source electrode having a portion sandwiched over the gate electrode with the gate insulating layer, the semiconductor layer, and the channel protective layer interposed therebetween. The method for forming a channel protective layer by patterning and implanting ions along the diagonal direction into a semiconductor layer having a protective layer implanted from the top with respect to the substrate to the inside of the opposite end of the channel protective layer from the opposite end of the semiconductor layer Forming a contact layer in the area under the channel protective layer extending to the area located at It includes.

As an alternative embodiment, the thin film transistor can comprise a gate electrode on an insulating substrate covered with a gate insulating layer, a semiconductor layer on the gate insulating layer, a channel protective layer on the semiconductor layer, the gate insulating layer, a semiconductor layer and a channel protective layer. A drain electrode having a portion overlying the gate electrode, and a source electrode having a portion overlying the gate electrode with the gate insulating layer, the semiconductor layer, and the channel protective layer interposed therebetween, wherein the semiconductor The layer has a concave in the center in the width direction of the gate insulating layer, and the channel protective layer has a narrower width than the semiconductor layer and a transverse portion thinner than its central portion, and the side inside of the channel protective layer from the opposite end of the semiconductor layer. Ions are implanted into the semiconductor layer through the channel protective layer so that the contact layer is formed in the region extending to the region located at .

In an alternative embodiment, the thin film transistor comprises a gate electrode on an insulating substrate covered with a gate insulating layer, a semiconductor layer on the gate insulating layer, a channel protective layer on the semiconductor layer, the gate insulating layer, a semiconductor layer and a channel protective layer. And a drain electrode having a portion sandwiched over the gate electrode, and a source electrode having a portion overlying the gate electrode with the gate insulating layer, the semiconductor layer, and the channel protective layer interposed therebetween, wherein the gate insulating layer is The gate insulating layer has a concave surface at the center in the width direction so as to cover the gate electrode, the semiconductor layer has a stepped portion along the contour of the gate insulating layer, and the channel protective layer has a narrower width and a central portion thereof than the semiconductor layer. Having a thinner transverse section and located within the side of the channel protective layer from opposite ends of the semiconductor layer Far the ions through the channel protective layer so that the contact layer formed in a region which extends is injected into the semiconductor layer.

As an alternative embodiment, the thin film transistor includes a semiconductor layer having a contact region and a channel region, a gate insulating layer, a gate electrode formed on the substrate in this order, a source electrode and a drain electrode respectively in contact with the contact region, The source electrode and the drain electrode partially overlap the ends of the semiconductor layer and the ends are wider than the gate insulating layer and the gate electrode, the gate insulating layer having inclined sides, wherein the sides adjacent to the gate electrode are the substrate. Ions are formed from the gate electrode such that a contact surface is formed at a portion of the semiconductor layer which overlaps with at least a portion of the inclined sides of the gate insulating layer and a portion of the semiconductor layer extending beyond the insulating layer. It is implanted into the semiconductor layer.

As an alternative embodiment, the thin film transistor has a semiconductor layer having a contact region and a channel region, a gate insulating layer, a gate electrode formed on the substrate in this order, a source electrode and a drain electrode respectively in contact with the contact region. The source electrode and the drain electrode partially overlap with the cross section of the gate insulating layer and the semiconductor layer wider than the gate electrode, and the gate insulating layer is wider than the gate electrode, and the portion of the semiconductor layer located below the cross section of the gate electrode. Ions are implanted from the gate electrode into the semiconductor layer so that the contact layer is formed in the region extending from the edge to the opposite side of the semiconductor layer.

In a preferred embodiment, the resist is patterned by exposing the back side of the gate electrode to light.

In a preferred embodiment, the resist is patterned by exposing the backside of the gate electrode to light, followed by patterning the channel protective layer using the patterned resist, and implanting ions into the semiconductor layer through the channel protective layer to form a contact layer. And form a contact layer using a second resist, wherein the second resist is used to pattern at least one of a source electrode and a drain electrode.

In a preferred embodiment, the resist used to make the channel protective layer is patterned by exposing the back side of the gate electrode to light, followed by patterning the channel protective layer using the patterned resist and using the remaining resist. Ions are concentrated in the semiconductor layer to form a contact layer.

As such, the invention described herein; (1) Ion provides a method of manufacturing an active matrix substrate that prevents impurities from being implanted into the channel protective layer during implantation, thereby preventing electrical leakage between the source electrode and the drain electrode, and (2) the side of the semiconductor layer is impurity. Forming a contact layer by implanting ions after patterning the semiconductor layer to be doped, even if the source electrode and the drain electrode is formed after the ion implantation to provide a method of manufacturing an active matrix substrate to reduce the electrical leakage between the source electrode and the drain electrode Fulfills the purpose of doing so.

The invention is illustrated using the following examples.

(Example 1)

This embodiment relates to the improvement of transistor characteristics of an active matrix substrate.

As shown in FIG. 1A, Ta is deposited to a thickness of 200 nm to 400 nm, preferably 300 nm on a transparent insulating substrate 1 such as a glass panel by sputtering. A photomask is then formed and patterned on this Ta layer to obtain a gate electrode 2. Subsequently, a gate insulating layer 3 of 200 nm to 400 nm, preferably 300 nm thick, made of SiNx on the entire surface of the glass substrate 1 so as to cover the gate electrode 2, amorphous silicon (hereinafter “a-Si”). 20 nm to 50 nm, preferably 30 nm thick, semiconductor layer 4, and 100 nm to 300 nm, preferably 200 nm thick, channel protective layer 5 made of SiNx by plasma CVD The resists 11 are coated on the channel protective layer 5 disposed on the top surface, and a photolithographic method is applied using a-Si pattern. The semiconductor layer 4 shown in FIG. ) And the channel protective layer 5 are patterned. Subsequently, a resist 11 is formed in a part of the gate insulating layer 3 which is not covered with the semiconductor layer 4 and the channel layer 5.

Photographic flats are then performed and the channel protective layer 5 is patterned as shown in FIG. 1C. In this state, the resist is positioned on the channel protective layer 5 in a uniform pattern.

As shown in FIG. 1C, P ⁺ ions are implanted from the surface of the channel protective layer 5 into the semiconductor layer 4 without stripping the resist 11, thereby forming a contact layer as shown in FIG. 6a) and 6b).

Subsequently, a metal layer of Ti or Mo of 200 nm to 400 nm, preferably 300 nm thick, is formed on the entire substrate 1 by sputtering and patterned using a photomask to form a source electrode as shown in FIG. 7) and drain electrode 8 are formed. A transparent electrode made of tin indium oxide layer (ITO) is laminated on the entire substrate 1 to a thickness of 50 nm to 100 nm, preferably 80 nm, and patterned using a photomask to form the pixel electrode 10. Thus, the active matrix substrate of the present embodiment is formed.

In the active matrix manufactured as described above, the ions are implanted while leaving the resist 11 on the channel protective layer 5, so that impurities are not contained on the channel protective layer 5. Therefore, the current leakage between the contact layer 6a and the source electrode 7 and between the contact layer 6b and the drain electrode 8 is significantly reduced. Impurities are also doped in the side of the semiconductor layer 4 because ions are implanted after patterning the semiconductor layer 4 to form the contact layers 6a and 6b. Therefore, current leakage between the side of the injected contact layer 6a and the source electrode 7 and between the side of the injected contact layer 6b and the drain electrode 8 causes the source electrode 7 and the drain electrode 8 to be discharged. Even if patterned after ion implantation, it can be reduced. Therefore, the off current is reduced and thus an active matrix having very good transistor characteristics can be obtained.

In addition to the above-described embodiments, the present invention can be similarly applied to thin transistors having a structure without the channel protective layer 5.

The source electrode 7 and the drain electrode 8 can be formed by the following method. The resist 11 is formed on the channel protective layer 5 on the entire substrate 1 as shown in FIG. 1D, and the metal layer 13 having a thickness of 200 nm to 400 nm made of Ti or Mo is placed thereon. It is formed to cover the above-described contact layer (6a) and (6b). Then, as shown in FIG. 3B, the source electrode 7 and the drain electrode 8 are formed by removing the above-described resist 11 of the metal layer 13.

In this case, the patterning process can be omitted. Therefore, the number of process steps and the process time can be shortened, thereby obtaining a simplified and efficient manufacturing process. This process can be applied even when the manufacture of the channel protective layer 5 is omitted.

(Example 2)

This embodiment relates to a method of manufacturing an active matrix substrate having very good transistor characteristics. More particularly, this embodiment describes a manufacturing method that is effective when implantation is performed using the channel protective layer as a mask.

4A and 4B show a method of manufacturing an active matrix substrate. The active matrix shown in FIG. 5 is formed by the process described below.

As shown in FIG. 4A, Ta is deposited on the transparent insulating substrate 1 such as a glass substrate by sputtering so as to have a thickness of 200 nm to 400 nm, preferably 300 nm. A photomask is then formed and patterned thereon to obtain a gate electrode 2. Then, on the entire surface of the glass substrate 1 to cover the gate electrode 2, the gate insulating layer 3 made of SiNx, preferably 300 nm thick, 30 nm to 200 nm thick made of a-Si Of the semiconductor layer 4 and the channel protective layer 5 having a thickness of 100 nm to 300 nm, preferably 200 nm, made of SiNx, are laminated in this order by the plasma CVD method. The channel protective layer 5 is then patterned to have a structure as shown in FIG. 4A.

Then, as shown in FIG. 4B, the semiconductor layer 4 is patterned, and P ⁺ ions are implanted into the semiconductor layer 4 from the side of the channel protective layer 5, thereby contacting the contact layer 6a and (6b) is formed. At this time, the rising voltage of the ions is adjusted so as not to reach the gate insulating layer 3. The value of the rising voltage varies depending on the thickness of the semiconductor layer 4. For example, if the thickness of the semiconductor 4 is 30 nm, which is the minimum value of the present embodiment, the rising voltage is fixed around 30 kV. When ions are implanted under the condition that impurities are doped to the side of the semiconductor layer 4 as shown in FIG. 4B, between the side of the semiconductor layer 4 and the source electrode 7 as shown in FIG. Large current leakage does not occur between the side surface of the semiconductor layer 4 and the drain electrode 8.

The channel protective layer 5 is surface cleaned using, for example, buffered HF (etch buffer, a mixture of hydrogen fluoride and ammonium fluoride) to remove the damage 50. By removing the damaged portion 50, current leakage between the source electrode 7 and the drain electrode 8 formed later can be reduced. It is not necessary to remove the entire part of the channel protective layer 5, but it is important that only the damaged part 50 be removed.

After the surface treatment is completed, a metal layer made of Ti or Mo is formed on the entire surface of the substrate by a sputtering method at a thickness of 200 nm to 400 nm, preferably 300 nm. By using a photomask, the metal layer is patterned to form the source electrode 7 and the drain electrode 8 shown in FIG. 5 to obtain a thin film transistor.

A transparent electrode made of tin indium oxide layer (ITO) was laminated on the entire surface of the substrate 1 at a thickness of 500 nm to 100 nm, preferably 80 nm, and patterned using a photomask to form the pixel electrode 10. By forming the active matrix of the present invention.

In this embodiment, current leakage is significantly reduced because ions are implanted after pattern formation of the semiconductor layer, and impurities are implanted on the side of the semiconductor layer 4 and at the same time the channel protective layer 5 used as a mask by cleaning. ), Remove the damaged part. Thus, an active matrix having excellent transistor characteristics can be obtained. In addition, the gate insulating layer 3 is not damaged because the gate insulating layer 3 is disposed so that impurities are not affected when ions are implanted. Thus, no threshold voltage fluctuations occur, resulting in excellent transistor characteristics and improved stability as an active matrix substrate.

(Example 3)

This embodiment relates to a method for fabricating an active matrix capable of removing off current using electrons and holes as carriers to obtain excellent transistor characteristics.

6 shows an active matrix. The active matrix substrate is manufactured by the method as described below. First, the gate electrode 2 is formed on the insulating substrate 1 made of transparent glass. In detail, a single layer or a plurality of layers made of Ta, Ti, Al, Cr, or the like is laminated on the insulating substrate 1 by a thickness of 200 nm to 400 nm and then patterned. At this time, the gate electrode 2 is branched to form a gate bus line.

Subsequently, the gate insulating layer 3 and the semiconductor layer 4 made of a-Si are stacked on the insulating substrate 1 on which the gate electrode 2 is disposed. The gate insulating layer 3 is formed to a thickness of 200 nm to 500 nm by laminating SiNx by plasma CVD. The semiconductor layer 4 thereon contains contact layers 6a and 6b on both sides of the semiconductor layer 4a made of a-sI at the center in the width direction. The contact layers 6a and 6b are formed by injecting ions into the semiconductor layer 4. The thickness of the contact layer can vary with ion implantation.

When the semiconductor layer 4 is made of a-Si, as shown in FIG. 7, the thickness of 20 nm to l50 nm, preferably 25 nm to 100 nm, and more preferably 25 to 50 nm on the gate insulating layer 3 is shown. Laminated and then patterned to form the semiconductor layer 4. Subsequently, a channel protective layer made of SiNx, SiO, or the like is similarly formed to a thickness of 100 nm to 300 nm. The impurity of, for example, a group V element or a compound thereof, or a group III element or a compound thereof is ion-implanted into the semiconductor layer 4 at a rising voltage of 1 kV to 100 kV through the channel protection certificate 5. If the semiconductor layer 4 has a thickness of 500 nm, the preferable rise voltage for ion implantation is l0kV to 50kV.

By ion implantation, both sides of the semiconductor layer 4 which are not covered with the channel protective layer 5 layer become contact layers 6a and 6b in which impurities are injected at a high density. The portion immediately below the channel protective layer 5 is separated from the channel protective layer 5 to form the semiconductor layer 4a having an original state.

In addition, contact layers 6a and 6b are formed on both sides through the semiconductor layer 4. The thicknesses of the contact layers 6a and 6b are the same as the thicknesses of the semiconductor layers 4a and 4b.

A source electrode 7 and a drain electrode 8 having a channel protective layer 5 at one end are formed on the insulating substrate 1 and placed on the contact layers 6a and 6b as described above. The electrode 7 and the drain electrode 8 are manufactured by laminating a metal layer made of Ti, Al, Mo, Cr, etc. to a thickness of 200 nm to 400 nm, and patterning it to manufacture a thin film transistor.

The active matrix is manufactured by forming a pixel electrode electrically connected to the drain electrode 8 of the thin film transistor. This pixel electrode forms an indium oxide layer (ITO) with a thickness of 50 nm to 100 nm.

FIG. 8 is an enlarged view of the side of the junction between the contact layer 6a and the semiconductor layer 4a of the active matrix formed as described above. As is apparent from the figure, the thickness of the cross-sectional area occupied by the side surface of the junction portion J is almost equal to the thickness of the semiconductor layer 4. In contrast, the contact layer 16a is formed by laminating a semiconductor thin layer containing an impurity such as a group V element as shown in FIG. 9, or by ion implantation as shown in FIG. If the thickness of the formed contact layer is thinner than the semiconductor layer 104, the area occupied by the side surface of the junction portion J becomes large.

Therefore, in the present embodiment, as shown in FIG. 8, it can be seen that the area occupied by the side surface of the junction portion J is significantly reduced as compared with FIG. 9 and FIG. Therefore, the off current, in which the carrier is a plurality of electrons generated in the semiconductor layer by light irradiation or a hole corresponding to the electrons, can be reduced to one to two digits as compared with the case shown in FIGS. 9 and 10. It is possible to obtain an active matrix substrate which exhibits stable properties even upon light irradiation. In the conventional case, the total thickness had to be adjusted to about 30 nm because the current is increased by the increase in light absorption depending on whether the distance through which light passes is increased. However, in the present embodiment, the thickness of the semiconductor layer can be manufactured to 50 nm or more because of the stable property against light, thereby reducing the light absorption which worsens the off current and improving the transistor characteristics.

The taper is not formed as a channel protective layer in this embodiment, but a paper channel protective layer can be used in the present invention.

(Example 4)

This embodiment shows a case where a part of the semiconductor layer disposed directly below the channel protection layer has a drain electrode and a contact layer, and contact layers for preventing current leakage by separating the source electrode and the contact layer.

FIG. 11 is a plan view showing an active matrix substrate, and FIG. 12 is a cross-sectional view taken along the line A-A. The active matrix substrate of this embodiment has a gate electrode on a transparent insulating substrate 1 such as a glass substrate. A single layer or a plurality of layers of metals made of Ta, Ti, Al, Cr, etc. are laminated on the transparent insulating substrate 1 with a thickness of 200 nm to 400 nm by sputtering and then patterned to obtain a gate electrode 2. A gate bus line 2a containing a gate electrode 2 branched from the gate bus line is also formed in this step (see FIG. 11).

The gate insulating layer 3 and the semiconductor layer 4 made of a-Si are formed on the substrate 1 having the gate electrode thereon. The gate insulating layer 3 is laminated with SiNx in a thickness of 200 nm to 500 nm, for example, by plasma CVD. Gate insulation between the contact layers 6a and 6b into which the impurity is injected at high density, the contact layers 6a 'and 6b' into which the impurity is injected at low density, and the semiconductor layer 4a of a-Si itself. It is formed on the semiconductor layer 4 disposed on the layer 3. Ions are implanted into these five layers and shaped upon implantation.

In detail, as shown in FIG. 13, the semiconductor layer 4a is formed on the gate insulating layer 3 to a thickness of 20 nm to 50 nm by plasma CVD and then patterned. Then, a channel protective layer 5 made of SiNx is laminated on the semiconductor layer with a thickness of 100 nm to 300 nm similarly to the above. In this step, the sides of the resist can be formed obliquely by lowering the backing temperature of the resist. The side surface of the channel protective layer 5 is formed obliquely at an angle θ by pulling out the side surface of the resist and dry etching to etch the channel protective layer 5. At this time, the etching selectivity of the channel protective layer and the semiconductor layer should be largely adjusted. In the case of wet etching, a taper can be easily obtained by etching using BHF (etch buffer which is a mixture of hydrogen fluoride and ammonium fluoride) after the resist pattern is formed in the photolithography process.

As shown in FIG. 13, the cross section of the channel protective layer 5 has a trapezoidal shape in which the upper side is smaller than the lower side. Inclination angle (theta) is less than 90 degrees, Preferably it is 10 degrees-50 degrees. The oblique side of the channel protective layer 5 makes the lower layer of the channel protective layer thin, so that ions can be easily implanted. The shape of the protective layer 5 is not limited to a trapezoid. Mountain shape is also possible.

Group V elements and mixtures thereof, such as P ⁺ , Pl ⁺ , PH ⁺ , B ⁺ , As, etc., or group III elements or compound impurities thereof, may be formed at the semiconductor layer 4 at an elevated voltage of 1 keV to 100 keV, preferably 5 keV to 50 keV. Is injected into. In this embodiment, P ⁺ is injected. At this time, a part of the semiconductor layer 4 which is not covered with the channel protective layer 5 becomes the contact layers 6a and 6b in which impurities are injected at high density. On the other hand, since the thickness of the lower portion of the inclined side is small, the portion covered with the channel protective layer becomes the contact layers 6a 'and 6b' into which impurities are injected at low density, and the semiconductor layer 4a is originally The channel protective layer 5 is formed on the central portion disposed immediately below.

The source electrode 7 and the drain electrode 8 are formed on the substrate 1 having one side on the channel protective layer 5. These source electrodes 7 and drain electrodes 8 have a thickness of 200 nm to 400 nm, respectively, and are made of Ti, Al, Mo, Cr, or the like.

The thin film transistor is manufactured as described above. The active matrix substrate is formed by manufacturing the pixel electrode 10 electrically connected to the drain electrode 8. The pixel electrode 10 is formed to have a thickness of 50 nm to 100 nm from the tin indium oxide layer (ITO).

As shown in FIG. 12, the channel protective layer 5 has contact layers 6a 'and 6b' into which impurities are injected at low density. Therefore, the distance between the semiconductor layer 4 and the source electrode 7 and the distance between the semiconductor layer 4 and the drain electrode 8 are the presence of the contact layers 6a 'and 6b' in which impurities are injected at low density. The current leakage can be controlled by reducing the current leakage generated by the source electrode 7 and the drain electrode 8 by one to two digits. It is also possible to form an active matrix substrate having the structure described above without increasing the number of processes and photomasks by using the method of the present invention. As a result, the method of the present invention can be applied to an active matrix type display device requiring a large amount of current.

(Example 5)

This embodiment relates to a method of forming a contact layer in a manner different from the method described in the fourth embodiment on a semiconductor layer disposed directly below the channel protective layer.

An active matrix substrate made in this manner is shown in FIGS. 14 and 15. The gate bus line 2a and the source bus line 7a are arranged in a grit form on the insulating substrate 1 made of transparent glass as shown in FIG. The pixel electrode 10 is arranged in a matrix form in the region surrounded by the lines 2a and 7a. The pixel electrode is necessary when used as an active matrix but not necessary when used as a thin film transistor. The gate electrode 2 is formed to protrude from the gate bus line to the pixel electrode 10, and the thin film transistor T is formed on the gate electrode 2.

FIG. 15 shows a cross-sectional structure of the thin film transistor T. As shown in FIG. The gate electrode 2 is formed by stacking a single layer or a plurality of metals made of Ta, Ti, Al, Cr, etc. on the insulating substrate 1 by sputtering, and then patterning the metal layer. The gate bus line 2a is formed at the same time.

A gate insulating layer 3 is formed on the insulating substrate 1 to cover the gate electrode 2. Next, a semiconductor layer 4 made of amorphous silicon is formed. The gate insulating layer 3 is formed by laminating SiNx with a thickness of 200 nm to 500 nm by plasma CVD. The semiconductor layer 4 thereon contains contact layers 6a and 6b on both side surfaces of the semiconductor layer 4 which are central portions in the width direction. These semiconductor layers 4a and the contact layers 6a and 6b are formed by implanting ions into the semiconductor layer 4.

Ion implantation is carried out in the processes shown in FIGS. 16 and 17. As shown in FIG. 16, amorphous silicon is deposited on the gate insulating layer 3 to a thickness of 20 nm to 50 nm by plasma CVD and then patterned to form the semiconductor layer 4. Subsequently, a channel protective layer 5 made of SiNx or the like is formed to a thickness of 100 nm to 300 nm similarly to the above. The channel protective layer 5 is formed at the center of the semiconductor layer 4 to have a width smaller than the thickness of the semiconductor layer 4.

Subsequently, as shown in FIG. 16, the impurity of a group V element such as phosphorus or a compound thereof, or a group III element such as boron or a compound thereof is added to the channel protective layer at a rising voltage of 1 kV to 100 kV, preferably 10 kV to 50 kV. Inject from the upper left direction in (5). Injection from "from the upper left direction" means injection from the side of the source electrode 7 formed later.

Then, as shown in FIG. 17, ions are implanted as described above from the upper right direction. Contact layers 6a and 6b in which ions are injected at low density are formed by ion implantation two or more times from both side surfaces in the width direction of the semiconductor layer 4 not covered with the channel protective layer to the end surface of the channel protective layer. do. The semiconductor layer 4 which remains in its original state is formed on the remainder of the portion, that is, on the central portion immediately below the channel protective layer 5. Ion implantation into the insulating substrate 1 is carried out at an angle of 10 to 180 degrees, preferably 30 degrees to 60 degrees, more preferably 45 degrees.

After the formation of the semiconductor layer 4 and the contact layers 6a and 6b, the source electrode 7 and the drain electrode 8 having one end are formed on the channel protective layer 5. The source electrode and the drain electrode 8 are formed by laminating metals such as Ti, Al, Mo, Cr, etc. to a thickness of 200 nm to 400 nm and then patterning them. The source bus line 7a is also formed at the same time, so that the transistor T is obtained.

The pixel electrode 10 is formed by electrically connecting to the drain electrode 8 on the insulating substrate 1. The pixel electrode is made of a tin indium oxide layer (ITO) having a thickness of 50 nm to 100 nm.

According to the active matrix manufactured as described above, the contact layers 6a and 6b into which impurities are injected under the channel protective layer 5 are formed as shown in FIG. Therefore, the distance between the semiconductor layer 4 and the source electrode 7 and the distance between the semiconductor layer 4 and the drain electrode 8 are caused by the presence of the contact layers 6a and 6b into which impurities are injected at low density. Insulation, thereby improving insulation, and as a result, less than 1 to 2 digits of leakage current is generated between the source electrode 7 and the drain electrode 8 when the active matrix of the above type is used to control the occurrence of leakage. have.

Moreover, by using the method of the present invention, an active matrix substrate having the above structure can be formed without increasing the number of processes and photomasks, thereby improving yield and reliability. As a result, the method of the present invention can be used as an active matrix display device requiring a large current.

Although no taper is formed in the channel protective layer described above, it is apparent that a tapered channel protective layer can be used in the present invention.

(Example 6)

This embodiment describes a method for forming a contact layer even in a portion of the semiconductor layer directly below the end of the channel protective layer by an additional method.

18 and 19 (sectional views taken along the lines (C)-(C)) show such an active matrix. The gate bus line 2a and the source bus line 7a are arranged in a grid on an insulating substrate 1 made of transparent glass as shown in FIG. The pixel electrode 10 is arranged in a matrix in a region surrounded by the bus lines 2a and 7a. The thin film transistor T is formed on the gate electrode 2 formed in the form of a protrusion from the gate bus line toward the pixel electrode 10.

19 shows a cross-sectional structure of a thin film transistor T of an active matrix. The gate electrode 2, the gate insulating layer 3, the semiconductor layer 4, the channel protective layer 5, the source electrode 7 and the drain electrode are shown in FIG. (8) is laminated on the insulating substrate 1 from the insulating substrate side in the order listed. The process of manufacturing the active matrix substrate is described below.

As shown in FIG. 20A, metals such as Ta, Ti, Al, Cr, and the like are deposited on the transparent insulating substrate 1 by a sputtering method to a thickness of 200 nm to 400 nm and then patterned to form the gate electrode 2. Let's do it. The gate bus line 2a is formed at the same time.

Then, after forming the gate insulating layer 3 on the insulating substrate 1 to cover the gate electrode 2, a semiconductor layer 4 made of amorphous silicon is formed thereon. The gate insulating layer 3 is formed by laminating SiNx in a thickness of 200 nm to 400 nm, for example, by plasma CVD. The semiconductor layer 4 thereon is formed as follows. First, an amorphous silicon layer is laminated to a thickness of 150 nm to 350 nm by, for example, plasma CVD.

As shown in FIG. 20B, the central portion of the semiconductor layer 4 is etched to leave a thickness of 50 nm to 100 nm. The channel protective layer 5 made of SiNx is formed in the same way at the center so as to have a thickness of 100 nm to 300 nm. The width of the channel protective layer 5 is arranged smaller than the width of the semiconductor layer 4. The stepped portion formed by the concave surface on the semiconductor layer 4 is planarized by etching as shown in FIG. 20C. As a result, the thin film layer 5a is formed on both sides of the channel protective layer 5.

Then, as shown in FIG. 20D, impurities of a Group V element such as phosphorus or a compound thereof, or a Group III element such as boron or a compound thereof, may be channeled at an elevated voltage of 1 kV to 100 kV, preferably 10 kV to 50 kV. Ion implantation is carried out from the surface of the protective layer 5. The contact layers 6a and 6b into which impurities are injected at low density are formed by injecting both sides in the width direction of the semiconductor layer 4 which is not covered with the channel protective layer 5. On the contrary, since impurities are not injected into the center portion in the width direction of the semiconductor layer 4, the semiconductor layer 4a is kept in its original state.

As described above, after the semiconductor layer 4a and the contact layers 6a, 6b, 6a 'and 6b' are formed, the source electrode 7 and the drain electrode having one end on the channel protective layer 5 are formed. (8) is formed. In order to form the source electrode 7 and the drain electrode 8, metals such as Ti, Al, Mo, Cr, and the like are laminated to a thickness of 200 to 400 nm and then patterned. The source bus line 7a is formed at the same time. The thin film transistor T is formed as described above.

The pixel electrode 10 is then formed by electrically connecting to the drain electrode 8 on the insulating substrate 1 to form an active matrix substrate. The pixel electrode 10 is formed from a tin indium oxide layer (ITO) to a thickness of 50 nm to 100 nm.

According to the active matrix as described above, the contact layers 6a 'and 6b' into which impurities are implanted are formed under the channel protective layer 5. Therefore, the distance between the semiconductor layer 4 and the source electrode 7, and the distance between the semiconductor layer 4 and the drain electrode 8, is determined by the contact layers 6a 'and 6b' where impurities are injected at low density. It will fall by presence, improving the insulation. As a result, leakage (current leakage) generated between the source electrode 7 and the drain electrode 8 can be controlled by using the shutter matrix manufactured in the above process.

(Example 7)

This embodiment relates to a method of forming a contact layer even in a portion of the semiconductor layer directly below the end of the channel protective layer in an additional manner.

21 to 23 show such an active matrix. FIG. 22 is a cross-sectional view taken along the line (D)-(D) of FIG. In this embodiment, the concave portion 3a is formed in the center of the gate insulating layer 3, and the semiconductor layer 4 thereon is formed in a step shape along the channel protective layer 5. The contact layers 6a 'and 6b' are formed at portions disposed below both ends in the width direction of the channel protective layer 5 of the semiconductor layer 4.

Since the thin film transistor of this embodiment has a configuration and a manufacturing process which are almost the same as the above embodiment, only the difference will be described below.

After the gate electrode 2 is formed on the insulating substrate 1 as described above, the gate electrode 2 is formed on both sides of the gate electrode 2 as shown in FIG. By stacking the gate insulating layers 3 ', the concave portion 3a is formed in the center of the width direction. Specifically, for example, SiNx is deposited by plasma CVD, or SiO ₂ is deposited by sputtering to have a thickness of 80 to 100 nm, and then patterned.

Then, as shown in FIG. 123B, the gate insulating layer 3 and the semiconductor layer 4 made of amorphous silicon are formed on the gate electrode 3 'in that order. The concave portion 3a is formed at the center in the width direction of the gate insulating layer 3, and the semiconductor layer 4 is formed in a step shape as shown. The gate insulating layer 3 of this embodiment is formed by laminating SiNx to a thickness of 200 nm to 500 nm, for example, by plasma CVD. The semiconductor layer 4 of this embodiment is formed by laminating amorphous silicon to a thickness of about 20 nm to 50 nm, for example by plasma CVD, and then patterned.

Then, as shown in FIG. 23B, after the channel protective layer 5 is laminated on the semiconductor layer 4 to a thickness of 200 nm to 300 nm, the surface of the channel protective layer 5 is etched in the same manner by etching. It is flattened (Fig. 23C).

Next, ions are implanted from the surface of the channel protective layer 5 in the same manner as shown in FIG. 23D. Contact layers 6a 'and 6b in which impurities are injected at low density in the widthwise portion of the semiconductor layer 4 which do not cover the contact layers 6a and 6b in which impurities are injected at a high density. ') Is formed at portions below both sides of the channel protective layer 5 of the semiconductor wafer 4 in the width direction, and a semiconductor layer 4a to which no impurities are injected is formed in the center of the semiconductor layer, respectively.

Next, the thin film transistor T as shown in FIGS. 21 and 22 is manufactured by forming the source electrode 7 and the drain electrode 8 described in the above-described embodiment. The active matrix substrate is formed by manufacturing the pixel electrode 10 in the same manner.

In the case of using the active matrix of the present embodiment, current leakage occurring between the source electrode 7 and the drain electrode 8 can be reduced by one to two digits less. In addition, it is possible to manufacture an active matrix substrate having the above-described structure without increasing the number of processes and photomasks, thereby improving yield and reliability. As a result, the present method can greatly contribute to manufacturing an active matrix display device that requires a large current.

In the above, an active matrix substrate using an inverted staggered thin film transistor has been described. However, not only this form but also an active matrix substrate using a staggered thin transistor can be used as described below.

(Example 8)

This embodiment relates to a method of forming a contact layer under an end of a gate insulating layer on which a semiconductor layer is disposed.

25 is a plan view of such an active matrix substrate. FIG. 24 is a cross-sectional view taken along the line (E)-(E) of FIG. The semiconductor layer 22, the gate insulating layer 23 and the gate electrode 24 are disposed in this order on the transparent insulating substrate 21 such as glass. The gate insulating layer 23 has a long trapezoidal cross section whose upper surface is shorter than the bottom surface, and the side surface is inclined by the inclination angle θ. The gate electrode 24 thereon is created such that the bottom surface is the same as the top surface of the gate insulating layer 23. The semiconductor layer 22 disposed under the gate insulating layer 23 is shorter in width than the width of the bottom surface. Gate insulating surfaces of the gate insulating layer 23 are formed from two ends in the width direction of the semiconductor layer 22. Contact regions 22a and 22b are formed by ion implanting impurities under both surfaces of 23a and 23b, and electrically connecting gate electrode 24 to gate electrode wiring 27 which signals for scanning.

The source electrode 25a and the drain electrode 25b are separately formed from the semiconductor layer 22 to the substrate 21 in the gate insulating layer 23. The drain electrode 25b is electrically connected to a pixel electrode (not shown) formed by partially stacking. On the other hand, the source electrode 25a is electrically connected to the source electrode wiring 28 in order to send a source signal. The active matrix of this embodiment is constructed by generating the protective layer 26 over the entire surface of the substrate.

Next, the manufacturing method of the active matrix substrate which has such a structure is demonstrated as follows.

As shown in FIG. 24, amorphous silicon is laminated on an insulating substrate 1 such as glass to have a thickness of 20 nm to 150 nm and then patterned to form a semiconductor layer 22. Subsequently, the gate insulating layer 23 made of SiNx or the like is laminated on the semiconductor layer 22 to have a thickness of 50 nm to 500 nm in the same manner. In this case, dry etching or wet etching is used to form the gate insulating layer 23 in which the side surfaces 23a and 23b are inclined. The inclination angle θ of the side is less than 90 °, preferably 10 ° to 70 °, more preferably 30 ° to 50 °. The thickness of the lower portions of the side surfaces 23a and 23b can be made thin by tilting the surface, so that impurities can be injected into the semiconductor layer 22 disposed under both sides 23a and 23b by ion implantation. The inclination angle θ of the side surfaces 23a and 23b may have different values.

Next, a single layer or a plurality of layers made of Ta, Ti, Al, Cr, or the like is laminated on the gate insulating layer 23 by sputtering to have a thickness of 200 nm to 400 nm, and then patterned to form a gate electrode. (24) is formed. When patterning, the gate electrode 24 is formed to have the same shape and the same size as the upper surface of the insulating layer 23 positioned below it.

Subsequently, impurities from the Group V element or the compound thereof, or the Group III element or the compound thereof are ion implanted through the surface into the semiconductor layer 22 at an elevated voltage of 1 kV to 100 kV, preferably 10 kV to 50 kV. In this case, the contact regions 22a and 22b are formed in the portion of the semiconductor layer 22 which is not covered by the gate insulating layer 23 but is covered by the side of the gate insulating layer 23. Impurities are injected in both layers. In order to function as a channel region by maintaining the original state, impurities are not introduced into the center portion of the semiconductor layer 22 covered with the gate insulating layer 23. The thickness of the semiconductor layer 22, the gate insulating layer 23, and the gate electrode 24 may be determined by ion implantation of the contact regions 22a and 22b.

The resist layer is formed on the gate electrode 24 in the form of reverse taper by dichlorobenzene treatment or the like. After that, Ti, Cr, Mo, A1, etc. are deposited on the resist layer so as to have a thickness of 200 nm to 400 nm, and the resist layer is removed, so that the source electrode 25a and The drain electrode 25b is formed.

Next, a pixel electrode (not shown) is formed by partially stacking the drain electrode 25b to form the protective layer 26 over the entire substrate 21 to manufacture the active matrix substrate of the present invention.

Thus, as shown in FIG. 24, there are contact regions 22a and 22b into which impurities are implanted under the gate insulating layer 23 of the active matrix substrate prepared above. Therefore, the portion between the channel region and the source electrode 25a and between the channel electrode and the drain electrode 25b is separated by the presence of the contact regions 22a and 22b, and the source is injected by injecting impurities at low density therebetween. The leakage current occurring between the electrodes 25a is reduced and the drain electrode 25b is made one to two digits smaller. In this way, leakage can be controlled. As a result, the method of the present invention can be used as an active matrix display device requiring a large current. In addition, by using the method of the present invention, the active matrix substrate can be formed without increasing the number of processes and photomasks, thereby creating an active matrix in which leakage is controlled.

Polysilicon as well as amorphous silicon can be used as the semiconductor layer 22.

In addition, SiO ₂ may be used for the gate insulating layer 23 instead of the SiN x of the present embodiment.

(Example 9)

This embodiment is also applied to the stagger type By a method different from that of the eighth embodiment, a contact layer is formed under the end of the gate insulating layer of the semiconductor layer disposed under the gate insulating layer.

27 is a plan view of such an active matrix substrate. FIG. 26 is a cross-sectional view taken along the line (F)-(F). The semiconductor layer 32, the gate insulating layer 33, and the gate electrode 34 are stacked in this order on the transparent insulating substrate to form an active matrix substrate. The width of each layer (line F)-(F) direction of the semiconductor layer 32 is greater than the width of the gate insulating layer 33 and the width of each layer of the gate insulating layer 33 is the width of the gate electrode 34. Greater than width Impurities are implanted into the contact regions 32a and 32b by ion implantation. Contact regions 32a and 32b are formed on both sides of the semiconductor layer 32 in the width direction from the bottom of the end of the gate electrode 34 to the end of the semiconductor layer 32. In order to send a scan signal, the gate electrode 34 is electrically connected to the gate electrode wiring 37.

The source electrode 35a and the drain electrode 35b are formed by branching the gate insulating layer 33 on the prescribed region from the semiconductor layer 32 to the substrate 31. The drain electrode 35b is electrically connected to a pixel electrode (not shown) formed by partially stacking. On the other hand, the source electrode 35a is electrically connected to the source electrode wiring 38 to send a source signal. The protective layer 36 is formed on the entire surface of the substrate 31 to form the active matrix of this embodiment.

The manufacturing method of an active matrix substrate is demonstrated as follows.

First, amorphous silicon is deposited on a transparent insulating substrate 31 such as glass to have a thickness of 20 nm to 150 nm, and then patterned to form a semiconductor layer 32.

Subsequently, SiNx is deposited on the semiconductor layer 32 with a thickness of 50 nm to 500 nm to form the gate insulating layer 33.

Next, the gate electrode 34 is formed by stacking and patterning a single layer or a plurality of metals such as Ta, Ti, Al, Cr and the like at a thickness of 200 nm to 400 nm by sputtering. When patterning, the gate electrode 34 should be formed to have a width smaller than the width of the gate insulating layer 33 beneath it. As a result, impurities can be injected into the semiconductor layer 32 disposed under the gate insulating layer 33 on which the gate electrode 34 is not formed.

Subsequently, impurities of the group V element or the compound thereof, or the group III element or the compound thereof are ion implanted into the semiconductor layer 32 at an elevated voltage of 1 kV to 100 kV. At this time, a contact region is formed by injecting impurities into a part of the semiconductor layer 32 not covered with the gate insulating layer 33 and a part of the semiconductor layer 32 under the gate insulating layer 33 not covered with the gate electrode 34. The centers of the semiconductor layer 32 disposed under the gate insulating layer 33 reach the original state for forming the channel region. The thickness of the semiconductor layer 32, the gate insulating layer 33, and the gate electrode 34 may be determined by ion implantation.

Subsequently, the gate electrode 34 is subjected to dichlorobenzene treatment to form a reverse tapered resist, and laminated with Ti, Cr, Mo, and Al to have a thickness of 200 nm to 400 nm, and then the resist is removed. As a result, a source electrode 35a and a drain electrode 35b branched by the gate insulating layer 33 are formed from the semiconductor layer 32 to the substrate 31 in the prescribed region.

Subsequently, by partially stacking on the drain electrode 35a, a pixel electrode electrically connected to the drain electrode 35b is formed. The protective layer 36 covers the entire surface of the substrate 31 to form an active matrix substrate.

Thus, as shown in FIG. 26, there are contact regions 32a and 32b for injecting impurities of the gate insulating layer 33 into the active matrix substrate manufactured as described above. The region between the channel region and the source electrode 35a, and the region between the channel region and the drain electrode 35b are separated by the presence of the source electrode 35a 斗 drain electrode 35b, whereby the source electrode 35a and drain The leakage of the current generated between the electrodes 35b can be made one to two digits smaller. Therefore, the present method can be used for an active matrix display device that controls the occurrence of leakage and requires a large current. In addition, it is possible to produce thin film transistors that control the occurrence of leakage without increasing the number of processes and photomasks.

Polysilicon as well as amorphous silicon having a thickness of 50 nm to 200 nm may be used for the semiconductor layer 32.

In addition, SiO ₂ may be used for the gate insulating layer 33 instead of SiNx.

If an insulated substrate is transparent, it can pattern as follows.

28, 29, and 30 are cross-sectional views illustrating a method of manufacturing an active matrix substrate. Figure 31 shows how the active matrix is produced. FIG. 31B is a cross-sectional view taken along the line (I)-(I) of FIG. 31A.

As shown in FIG. 28A, Ta is deposited on the glass substrate 1 in a thickness of 200 nm to 400 nm, for example, a thickness of 300 nm by the sputtering method. The gate electrode 2 is formed using a photomask. Subsequently, the gate insulating layer 3 (thickness 200 nm to 500 nm, for example 300 nm) made of SiNx by plasma CVD method, the semiconductor layer 4 (thickness 30 nm) made of a-Si, and the thickness l00 nm to 300 nm such as 200 nm The channel protective layer 5 is laminated on the entire substrate 1 in this order so as to cover the gate electrode 2.

After the resist 11 is coated on the channel protective layer 5, the gate electrode 2 is exposed from the opposite ends of the stacked layers. That is, it exposes from the back surface of the glass substrate 1. Since the glass substrate 1, the gate insulation 3, the semiconductor layer 4 and the channel protective layer 5 are exposed to the substrate-transmitted light, the exposure should be increased only when the exposure amount is increased as compared with the exposure from the top surface of the resist. Can be obtained.

In this embodiment, a positive-resist (irradiated resist dissolved by development) is commonly used. The thickness of the gate electrode 2 is set to a value necessary to block light caused by exposure from the rear surface. In this embodiment, the thickness is 300 nm.

As shown in FIG. 28, the exposed portion is exposed by exposing from the rear surface to dissolve by developing the resist 11 to obtain a prescribed form.

Subsequently, the patterned channel protective layer 5 shown in FIG. 29A is formed by using the resist 11. The resist 11 may be slightly reduced by etching, so that the resist 11 has a reference numeral 12 in FIG. 29A to distinguish it. Hereinafter, this is called (12).

The contact layer by implanting P ⁺ ions without peeling the resist 12 (injection mask) from the upper surface of the channel protective layer 5 patterned by the region implanted with P ⁺ ions in the semiconductor layer 4 The fields 6a and 6b are formed. When implanting ions, the resist 12 remains, because P ⁺ ion implantation is reduced compared to the case where the resist 12 is absent, which causes the source electrode 7 and the drain electrode 8 to be described later. Electrical leakage occurring between For this reason, when P ⁺ ions are injected into the channel protective layer 5, a weak current is generated between the source electrode 7 and the drain electrode 8. However, when the resist l2 remains as described, the P ⁺ ion implantation into the channel protective layer 5 can be reduced as compared with the case without the resist 12.

Subsequently, after the resist 12 is peeled off, a metal layer made of Ti or Mo is formed on the entire surface of the glass substrate 1 by a thickness of 200 nm to 400 nm by the sputtering method as shown in FIG. 30A. For example, Mo layer electrodes 7 and 8 are formed to a thickness of 200 nm.

Further, as shown in FIG. 30B, the source electrode 7, the drain electrode 8 and the contact layers 6a and 6b are formed by patterning the metal layer and the contact layer using a photomask. At the same time, the source bus line 7 'is patterned. Patterning is done by photolithography and the required exposure process is terminated with a single exposure. That is, the source layer 7 and the drain electrode 8, and the contact layers 6a and 6b are obtained by exposing the coated resist using a photomask and then developing and patterning not only the metal layer but also the contact layer at the same time. do. As a result, only one photomask (exposure mask) is used. In addition, it is not necessary to adjust (arrange) the position of the exposure mask in order to arrange the source electrode and the drain electrode on the contact layer, which is necessary when the source electrode and the drain electrode, and the contact layer are patterned. In etching, the source electrode, the drain electrode and the contact layer can be simultaneously etched by wet etching (mixed solution of hydrogen fluoride and nitric acid) and dry etching (carbon tetrachloride group). In this embodiment, dry etching showing the desired accuracy is used. The thickness of the resist is sufficient if it exceeds 1 µm.

As described above, a thin film transistor having a cross-sectional configuration shown in FIG. 30A is produced. Since the transistor purchases less ions into the channel protective layer 5, there is little leakage of current between the source electrode 7 and the drain electrode 8. Further, even when the source bus line is connected to the source electrode 7, since the contact point 6a exists, this transistor is not easily disconnected.

In addition, as shown in FIG. 31A, a transparent layer made of a tin indium oxide layer (ITO) is laminated on the entire surface of the glass substrate 1 on which a thin film transistor having a thickness of 50 nm to l00 nm, for example, 80 nm is formed. The pixel electrode 10 is formed by patterning using a photomask to manufacture an active matrix substrate. FIG. 31A is a plan view of the active matrix substrate, and FIG. 31B is a sectional view taken along the line (I)-(I) of the active matrix substrate. As shown in FIG. 31A, the thin film transistor and the pixel electrode 10 are formed by the gate bus line 2 'connected to the gate electrode 2 and the source electrode 7 connected to the source bus line 7'. ) In the form of a matrix.

In this embodiment, although the a-Si layer is used for the semiconductor layer, multiple crystals such as silicon can also be used. Conventional materials and configurations of the active matrix can also be used.

According to the method, since the channel protective layer and the contact layer do not require a photomask, the number of photomasks and exposure processes can be reduced, thereby improving practicality. In addition, it is not possible to pattern the arrangement difference, so that an active matrix having excellent characteristics can be easily obtained.

In this embodiment, the contact layer is formed on the semiconductor layer by ion implantation, but the contact layer can be formed in the same portion by using another method, that is, by doping ions.

Those skilled in the art can clearly and easily practice various modifications without departing from the scope and principles of the present invention. Accordingly, the scope of the claims appended hereto should not be limited to those described herein, but the claims are intended to cover the invention, including all features which are treated as equivalent by those skilled in the art to which this invention relates. It includes all the features of patentable novelty inherent in it.

Claims (16)

A portion of the gate electrode on the insulating substrate covered with the gate insulating layer, the semiconductor layer on the gate insulating layer, the channel protective layer on the semiconductor layer, and the portion to be placed on the gate electrode with the gate insulating layer, the semiconductor layer, and the channel protective layer interposed therebetween. In order to manufacture an active matrix substrate using a thin film transistor having a drain electrode having a drain electrode and a source electrode having a portion overlying the gate electrode with the gate insulating layer, the semiconductor layer and the channel protective layer interposed therebetween, Forming a resist on the channel protective layer patterning the layer and forming a contact layer by implanting ions into the semiconductor layer by using a resist film as an implantation mask after the pattern formation of the channel protective layer Way. The method of claim 1, wherein the contact layer is formed by patterning the semiconductor layer. 2. The method of claim 1, wherein a resist is formed on the channel protective layer by patterning, ions are implanted into the semiconductor layer by using the resist film as an implantation mask, and the resist is removed to pattern the drain and source electrodes. A gate electrode on the insulating substrate covered with a gate insulating layer, a semiconductor layer on the gate insulating layer, a drain electrode having a portion to be placed on the gate electrode with the gate insulating layer and the semiconductor layer interposed therebetween, and the gate insulating layer and To fabricate an active matrix substrate using a thin film transistor having a source electrode having a portion overlying a gate electrode with a semiconductor layer interposed therebetween, by patterning a resist over the semiconductor layer, using the resist film as an injection mask. Implanting ions into the semiconductor layer to form a contact layer, forming a conductive layer used for the drain electrode and the source electrode without removing the resist, and removing the resist to form the drain electrode and the source electrode separately. Manufacture of active matrix substrate comprising a . A gate electrode on an insulating substrate covered with a gate insulating layer, a semiconductor layer on a gate insulating layer, a channel protective layer on the semiconductor layer, and a portion to be placed on the gate electrode with the gate insulating layer, the semiconductor layer, and the channel protective layer interposed therebetween. In order to manufacture an active matrix substrate using a thin film transistor having a drain electrode having a drain electrode and a source electrode having a portion overlying the gate electrode with the gate insulating layer, the semiconductor layer and the channel protective layer interposed therebetween, Patterning the layer and implanting ions into the semiconductor layer using the patterned channel protective layer as a mask to form a contact layer. 6. A method according to claim 1, 4 or 5, wherein the contact layer is formed by implanting ions under an accelerating voltage so that impurities do not reach the gate insulating layer. 6. The method of claim 1, 4 or 5, wherein the ions are implanted such that the contact layer has the same thickness as the semiconductor layer. Gate electrodes on an insulating substrate, all of which are covered with a gate insulating layer, and are placed on the gate electrode with a semiconductor layer on the gate insulating layer, a channel protective layer on the semiconductor layer, a gate insulating layer and a semiconductor layer, and a channel protective layer interposed therebetween. To fabricate an active matrix substrate using a thin film transistor having a drain electrode having a drain electrode and a source electrode having a portion overlying the gate electrode with the gate insulating layer, the semiconductor layer, and the channel protective layer interposed therebetween, trapezoidal channel protection Implanting ions into the semiconductor layer through the channel protective layer such that a contact layer is formed in the portion of the semiconductor layers immediately below the edges of the inclined sides of the layer. A gate electrode on an insulating substrate covered with a gate insulating layer, a semiconductor layer on the gate insulating layer, a channel protective layer on the semiconductor layer, and a portion to be placed on the gate electrode with the gate insulating layer and the semiconductor layer and the channel protective layer interposed therebetween. In order to manufacture an active matrix using a thin film transistor having a drain electrode having a drain electrode and a source electrode having a portion to be placed on the gate electrode with the gate insulating layer, the semiconductor layer and the channel protective layer between. Forming a channel protective layer and implanting ions along the diagonal direction into the semiconductor layer having the protective layer implanted from above with respect to the substrate to extend from an opposite end of the semiconductor layer to an area located inside the opposite end of the channel protective layer. Forming a contact layer in an area below the channel protective layer; Method for producing an active matrix substrate. A gate electrode on an insulating substrate covered with a gate insulating layer, a semiconductor layer on the gate insulating layer, a channel protective layer on the semiconductor layer, and a portion to be placed on the gate electrode with the gate insulating layer and the semiconductor layer and the channel protective layer interposed therebetween. In order to manufacture an active matrix substrate using a thin film transistor having a drain electrode having a drain electrode and a source electrode having a portion to be placed on the gate electrode with the gate insulating layer, the semiconductor layer and the channel protective layer sandwiched therebetween, The semiconductor layer has a concave surface at the center in the width direction of the gate insulating layer, and the channel protective layer has a width narrower than the semiconductor layer and a transverse portion thinner than its central portion, and the channel protective layer is formed from the opposite end of the semiconductor layer. Ions are transferred through the channel protective layer to form a contact layer in the region extending to the region inside the sides. A method of manufacturing an active matrix substrate comprising implanting into a semiconductor layer. A gate electrode on an insulating substrate covered with a gate insulating layer, a semiconductor layer on the gate insulating layer, a channel protective layer on the semiconductor layer, and a portion to be placed on the gate electrode with the gate insulating layer and the semiconductor layer and the channel protective layer interposed therebetween. In order to manufacture an active matrix substrate using a thin film transistor having a drain electrode having a drain electrode and a source electrode having a portion to be placed on the gate electrode with the gate insulating layer, the semiconductor layer and the channel protective layer sandwiched therebetween, The gate insulating layer has a concave surface at the center in the width direction so that the gate insulating layer covers the gate electrode, the semiconductor layer has a stepped portion along the contour of the gate insulating layer, the channel protective layer is more than the semiconductor layer Opposite sides of the semiconductor layer, having a narrower width and a transverse portion thinner than its central portion From the method of manufacturing an active matrix substrate including the ion through the channel protective layer so that the contact layer formed in a region extending to a region located on the inside of the sides of the channel protection layer the step of injecting into the semiconductor layer. A semiconductor layer having a contact region and a channel region, a gate insulating layer, a gate electrode formed on the substrate in this order, a source electrode and a drain electrode respectively in contact with the contact region, wherein the source electrode and the drain electrode are a semiconductor layer The ends of the gate insulating layer and the gate electrode layer are wider than the gate insulating layer and the gate electrode, the gate insulating layer having inclined sides, with its sides adjacent to the gate electrode facing an upper surface narrower than its bottom toward the substrate. Ions are implanted into the semiconductor layer from the gate electrode such that the contact layer is formed on at least a portion of the inclined sides of the gate insulating layer and a portion of the semiconductor layer overlapping the portion of the semiconductor layer extending beyond the insulating layer. Method for producing an active matrix substrate. A semiconductor layer having a contact region and a channel region, a gate insulating layer, a gate electrode formed on the substrate in this order, a source electrode and a drain electrode respectively in contact with the contact region, wherein the source electrode and the drain electrode are a gate insulating layer And a gate insulating layer wider than the gate electrode and positioned under the cross section of the gate electrode to fabricate an active matrix substrate using a thin film transistor that partially overlaps a cross section of the semiconductor layer wider than the gate electrode. A method of manufacturing an active matrix substrate, characterized by implanting ions from a gate electrode into a semiconductor layer such that a contact layer is formed in a region extending from a portion of the substrate to an opposite side of the semiconductor layer. 6. The method of claim 1 or 5, wherein the resist is patterned by exposing the back side of the gate electrode to light. 6. The method of claim 1 or 5, wherein the resist is patterned by exposing the back side of the gate electrode to light, followed by patterning the channel protective layer using the patterned resist, and transferring ions into the semiconductor layer through the channel protective layer. Implanting to form a contact layer and patterning the contact layer using a second resist, wherein the second resist is used to pattern at least one of a source electrode and a drain electrode. The patterned resist of claim 1 or 5, wherein the resist used to make the channel protective layer is patterned by exposing the back side of the gate electrode to light, followed by patterning the channel protective layer using the patterned resist and remaining. A method of forming a contact layer by implanting ions into a semiconductor layer using a resist.