JPH02222545A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPH02222545A JPH02222545A JP4422989A JP4422989A JPH02222545A JP H02222545 A JPH02222545 A JP H02222545A JP 4422989 A JP4422989 A JP 4422989A JP 4422989 A JP4422989 A JP 4422989A JP H02222545 A JPH02222545 A JP H02222545A
- Authority
- JP
- Japan
- Prior art keywords
- group
- semiconductor layer
- crystal semiconductor
- laser beam
- single crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 239000013078 crystal Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 19
- 230000015572 biosynthetic process Effects 0.000 claims abstract 2
- 239000012535 impurity Substances 0.000 claims description 10
- 239000007789 gas Substances 0.000 abstract description 20
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Natural products P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 abstract description 7
- 239000011521 glass Substances 0.000 abstract description 6
- 229910021478 group 5 element Inorganic materials 0.000 abstract description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 4
- 239000011574 phosphorus Substances 0.000 abstract description 4
- 229910000073 phosphorus hydride Inorganic materials 0.000 abstract description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract description 3
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 abstract description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
を産業上の利用分野」
本発明は非単結晶半導体薄膜を用いた薄膜トランジスタ
（以下にＴＰＴともいう）及びその製造方法に関するも
のであり、特に液晶デイスプレー。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a thin film transistor (hereinafter also referred to as TPT) using a non-single crystal semiconductor thin film and a method for manufacturing the same, and in particular to a liquid crystal display.
イメージセンサ−等に適用可能な高速応答性を持つ薄膜
トランジスタに関する。The present invention relates to a thin film transistor with high-speed response that can be applied to image sensors and the like.
「従来の技術Ｊ
最近、化学的気相法等によって、作製された非単結晶半
導体薄膜を利用した薄膜トランジスタが注目されている
。"Prior Art J" Recently, thin film transistors using non-single-crystal semiconductor thin films produced by chemical vapor deposition have been attracting attention.
この薄膜トランジスタは、絶縁性基板上に前述の如く化
学的気相法等を用いて形成されるので、その作製雰囲気
温度が最高で４５０°Ｃ程度と低温で形成でき、安価な
ソーダガラス、ホウケイ酸ガラス等を基板として用いる
ことができる。Since this thin film transistor is formed on an insulating substrate using a chemical vapor phase method as mentioned above, it can be formed at a low temperature of about 450°C at maximum, and it can be formed using inexpensive soda glass or borosilicate. Glass or the like can be used as the substrate.
この薄膜トランジスタは電界効果型であり、いわゆる？
ｌ０ＳＦＥＴと同様の機能を有しているが、前述の如く
安価な絶縁性基板上に低温で形成でき、さらにその作製
する最大面積は薄膜半導体を形成する装置の寸法にのみ
限定されるもので、容易に大面積基板上にトランジスタ
を作製できるという利点を持っていた。このため多量の
画素を持つマトリクス構造の液晶デイスプレーのスイッ
チング素子や一次元又は二次元のイメージセンサ等のス
イッチング素子として極めて有望である。This thin film transistor is a field effect type, so-called?
It has the same function as the IOSFET, but as mentioned above, it can be formed at low temperature on an inexpensive insulating substrate, and the maximum area that can be manufactured is limited only by the dimensions of the device that forms the thin film semiconductor. It had the advantage that transistors could be easily fabricated on large-area substrates. Therefore, it is extremely promising as a switching element for matrix-structured liquid crystal displays having a large number of pixels, one-dimensional or two-dimensional image sensors, and the like.
また、この薄膜トランジスタを作製するにはすでに確立
された技術であるフォトリソグラフィーが応用可能で、
いわゆる微細加工が可能であり、ＩＣ等と同様に集積化
を図ることも可能であった。In addition, photolithography, which is an already established technology, can be applied to fabricate this thin film transistor.
So-called microfabrication was possible, and it was also possible to integrate it like ICs and the like.
この従来より知られたＴＰＴの代表的な構造を第２図に
概略的に示す。A typical structure of this conventionally known TPT is schematically shown in FIG.
（２１）はガラスよりなる絶縁性基板であり、（２２）
は非単結晶半導体よりなる薄膜半導体、（２３）、 （
２４）はソースドレイン領域で、（２５）、 （２６）
はソースドレイン電極、（２７）はゲート絶縁膜で（２
８）はゲート電極であります、 このように構成された
薄膜トランジスタはゲート電極（２８）に電圧を加える
ことにより、ソースドレイン（２３）、 （２４）間に
流れる電流を調整するものであります。(21) is an insulating substrate made of glass, (22)
is a thin film semiconductor made of a non-single crystal semiconductor, (23), (
24) is the source/drain region, (25), (26)
is the source/drain electrode, (27) is the gate insulating film, and (2
8) is the gate electrode. The thin film transistor configured in this way adjusts the current flowing between the source and drain (23) and (24) by applying voltage to the gate electrode (28).
このような、ＴＰＴを作成する場合にソースドレイン領
域にはＮ型またはＰ型の導電型を示す不純物が高濃度で
、含まれている。この部分を形成する方法としては、こ
れら不純物が混入された低抵抗の非単結晶半導体層をチ
ャネルが形成される高抵抗の非単結晶半導体層上に積層
に形成する方法と、高抵抗の非単結晶半導体層表面上よ
りこれら不純物原子を移動させて高抵抗の非単結晶半導
体層中にソースドレイン領域を形成する方法が知られ広
く行われている。When such a TPT is manufactured, the source/drain region contains a high concentration of impurities exhibiting N-type or P-type conductivity. There are two methods for forming this part: a method in which a low-resistance non-single crystal semiconductor layer mixed with these impurities is stacked on a high-resistance non-single-crystal semiconductor layer in which a channel is formed; A method of forming source/drain regions in a high resistance non-single crystal semiconductor layer by moving these impurity atoms from above the surface of the single crystal semiconductor layer is known and widely used.
しかしながら、前者の方法は不純物が混入された低抵抗
の非単結晶半導体層をチャネルが形成される高抵抗の非
単結晶半導体層上に積層して形成するため両手導体層の
間に界面ができ、この界面がＴＰＴの特性に悪影響を与
えることが多くこの界面の状態を良くすることは難しか
った。However, in the former method, a low-resistance non-single-crystal semiconductor layer containing impurities is stacked on a high-resistance non-single-crystal semiconductor layer in which a channel is formed, so an interface is created between the two-handed conductor layers. This interface often has an adverse effect on the properties of TPT, and it has been difficult to improve the condition of this interface.
一方、後者の方法は熱を基板及び非単結晶半導体層にく
わえることにより不純物を非単結晶半導体層の表面より
その内部へと拡散させるもので、その拡散させる速度を
速くするには加える温度をあげる必要がある。On the other hand, the latter method diffuses impurities from the surface of the non-single-crystal semiconductor layer into the interior by applying heat to the substrate and the non-single-crystal semiconductor layer. I need to give it.
その場合安価なガラス基板を使用することができずコス
ト高になり、加える温度を低くすると不純物が拡散され
る速度が遅（作製に多くの時間を必要としていた。In this case, it is not possible to use an inexpensive glass substrate, resulting in high costs, and lowering the applied temperature slows down the rate at which impurities are diffused (manufacturing requires a lot of time).
ｒ発明の目的」
本発明は前述の如き問題を解決するものであり、従来の
ＴＰＴ比べて良好な特性を示すＴＰＴをより低温で作製
可能としたものであります。Purpose of the Invention The present invention solves the above-mentioned problems, and makes it possible to produce TPT that exhibits better characteristics than conventional TPT at a lower temperature.
ｒ発明の構成」
本発明は減圧状態において、少なくとも■族又は■族元
素を含む気体に対して、電気エネルギーを供給しプラズ
マ化してこれら気体を活性化し、この雰囲気下にて、高
抵抗の非単結晶半導体層の少なくともソース、ドレイン
領域にレーザ光を照射し、このレーザ光が照射された部
分に■族又は■族元素をドープして、ソース、ドレイン
領域を形成するものであります、この場合、混合ガス中
には被膜形成を行なう気体、例えば５ｉｎ４等は含まれ
ておらず、水素又はヘリウム等の不活性気と■族又は■
族元素を含む気体で構成されております。``Structure of the Invention'' The present invention supplies electrical energy to gases containing at least Group Ⅰ or Group Ⅰ elements in a reduced pressure state to turn them into plasma and activate these gases, and in this atmosphere, generates a high-resistance non-metallic material. In this case, the source and drain regions are formed by irradiating at least the source and drain regions of the single crystal semiconductor layer with a laser beam, and doping the portions irradiated with the laser beam with group III or group III elements. , the mixed gas does not contain a gas that forms a film, such as 5in4, and contains an inert gas such as hydrogen or helium and a group
It is composed of gases containing group elements.
すなわち、■族又は■族の元素を含む混合気体に電気エ
ネルギーを与えて、混合気体をプラズマ化すると、これ
ら気体は各々の持つエネルギーに見合った種々の状態を
とり、゛はげしく運動を行っている。このようなプラズ
マ雰囲気下に高抵抗の非単結晶半導体層を持つ基板を配
置すると、これが常に高抵抗の非単結晶半導体層を物理
的にたたいた状態となっている。この時にソース、ドレ
イン領域にレーザ光を照射すると、その領域近傍の■族
又は■族の元素がこのレーザ光によって、より高エネル
ギー状態に活性化される。この■族又はＶ族元素は前述
の如く常に高抵抗の非単結晶半導体層を物理的にたたい
ているので、活性化された状態でも同様のふるまいを行
い、高抵抗の非単結晶半導体層中にドーピングされてゆ
くのである。In other words, when electric energy is applied to a gas mixture containing elements of Group Ⅰ or Group ■, and the mixture is turned into plasma, these gases take on various states commensurate with their respective energies, and move rapidly. . When a substrate having a high-resistance non-single-crystal semiconductor layer is placed in such a plasma atmosphere, the substrate always physically hits the high-resistance non-single-crystal semiconductor layer. At this time, when the source and drain regions are irradiated with laser light, the group (1) or group (2) elements in the vicinity of the regions are activated to a higher energy state by the laser light. As mentioned above, this Group Ⅰ or Group V element always physically hits the high-resistance non-single crystal semiconductor layer, so it behaves in the same way even in the activated state, and the high-resistance non-single crystal semiconductor layer The inside of the body is doped.
またこの■族又は■族元素は長時間にわたって高エネル
ギー状態をとり続けることができない（他の気体分子、
ラジカルとの衝突等によりエネルギーを失うため）ので
選択的なドーピングが行なえるのである。In addition, this group III or group III element cannot maintain a high energy state for a long time (other gas molecules,
Because energy is lost due to collisions with radicals, etc.), selective doping can be performed.
上記のような工程の結果、高抵抗の非単結晶半導体層中
にソース、ドレインを選択的に形成することができ、よ
り短チャネルであり高速応答性のよいＴＰＴを安価な価
格にて提供することが可能となるものであります。As a result of the above process, a source and a drain can be selectively formed in a high-resistance non-single crystal semiconductor layer, and a TPT with a shorter channel and high-speed response can be provided at an inexpensive price. This is what makes it possible.
また、この時基板及び高抵抗の非単結晶半導体層は高抵
抗の非単結晶半導体層作製時の基板温度より低い温度に
保持されているものであり、このことにより、ＴＰＴ作
製工程において、前工程に基板及び被膜を加えた温度よ
り後工程で加える温度を低くすることができ、半導体装
置の依願性を向上させることが可能なものであります。Furthermore, at this time, the substrate and the high-resistance non-single-crystalline semiconductor layer are kept at a lower temperature than the substrate temperature during the fabrication of the high-resistance non-single-crystalline semiconductor layer. The temperature applied in subsequent processes can be lower than the temperature applied to the substrate and film during the process, making it possible to improve the reliability of semiconductor devices.
以下実施例を示し本発明を説明する。The present invention will be explained below with reference to Examples.
「実施例」
第１図（ａ）〜（Ｃ）は本発明の実施例を一つの製造工
程を示している。"Example" FIGS. 1(a) to (C) show one manufacturing process of an example of the present invention.
まず（ａ）の工程において、絶縁性表面を有する基板（
１）例えばソーダガラス基板（１）をプラズマ発生が可
能な装置の反応室内に入れこの基板上に公知のプラズマ
ＣＶＤ法によって、■型の高抵抗性の非単結晶半導体層
（２）を約３００００程度形成する。この時の作製条件
を以下に示す。First, in step (a), a substrate (
1) For example, a soda glass substrate (1) is placed in a reaction chamber of an apparatus capable of generating plasma, and approximately 30,000 layers of a ■-type high-resistance non-single-crystal semiconductor layer (2) is formed on this substrate by a known plasma CVD method. form a degree. The manufacturing conditions at this time are shown below.
基板温度 ２１０ ’Ｃ
反応応力 ０． ０５ ＴｏｒｒＲｆＰｏｗｅｒ
９０ Ｗ
ガス Ｓ ｉ Ｈａ
次に℃）の工程において、反応室内の気体を排気した後
、水素ガスとホスフィンガス（ＰＨ３）の混合ガスを導
入し圧力０．１Ｔｏｒｒで高周波電力を６０Ｗ印加して
プラズマ状態とした。この時のホスフィンは約１５％と
なるように混合した。基板上の高抵抗の非単結晶半導体
層（２）はこの混合ガスの雰囲気下におかれている。こ
の時基板加熱は行わなかった。Substrate temperature 210'C Reaction stress 0. 05 TorrRfPower
90 W Gas S i Ha Next, in the step (°C), after exhausting the gas in the reaction chamber, a mixed gas of hydrogen gas and phosphine gas (PH3) was introduced, and 60 W of high-frequency power was applied at a pressure of 0.1 Torr to generate plasma. state. At this time, the amount of phosphine was mixed to be about 15%. A high resistance non-single crystal semiconductor layer (2) on the substrate is placed in an atmosphere of this mixed gas. At this time, the substrate was not heated.
そして、高抵抗の非単結晶半導体Ｎ（２）のソース３ド
レイン領域に対しエキシマレーザ光（９） （２４８，
７ｎｍ）を照射した。Excimer laser light (9) (248,
7 nm).
この時エキシマレーザ光の照射ビームの形状は光学系に
より集光し、かつその外形をソース（３）。At this time, the shape of the irradiated beam of excimer laser light is focused by an optical system, and its outer shape is defined as a source (3).
ドレイン（４）の領域の外形に一致するようにして照射
した。その時レーザ光の条件は、０．０５Ｊ／ｄのエネ
ルギー密度で、パルス巾１０μｓｅｃで１５００パルス
照射した。Irradiation was carried out to match the outline of the region of the drain (4). At that time, the laser beam was irradiated with 1500 pulses with an energy density of 0.05 J/d and a pulse width of 10 μsec.
これによってリンは、このレーザ光が照射された領域に
のみドーピングされる。As a result, phosphorus is doped only in the region irradiated with this laser beam.
その深さはレーザ光の照射回数及びエネルギーによって
調整可能であるが、エネルギー量が多いと半導体層に損
傷を与えてしまうことがあるので、低エネルギーに保ち
照射回数によってドーピングされる深さを制御する方が
工程上のマージンが増す。 また、ソースとドレインの
間隔は、レーザ光の照射間隔にて調整可能で本実施例の
場合は、その間隔を７μｍとし短チャネルのＴＰＴとし
た。The depth can be adjusted by the number of laser beam irradiations and the energy, but if the amount of energy is too large, it may damage the semiconductor layer, so the doping depth can be controlled by keeping the energy low and changing the number of irradiations. This will increase the margin in the process. Further, the distance between the source and the drain can be adjusted by adjusting the laser beam irradiation interval, and in this example, the distance was set to 7 μm to form a short channel TPT.
次に（Ｃ）の工程として、反応室内の気体を排気し、ガ
スをシランとアンモニアの混合ガスに変えて反応室内に
導入し、ゲート絶縁膜（５）として窒化珪素膜を２００
人形成した。Next, in step (C), the gas in the reaction chamber is exhausted, the gas is changed to a mixed gas of silane and ammonia, and the mixture is introduced into the reaction chamber, and a silicon nitride film is formed as a gate insulating film (5) at
Formed a person.
その作製条件を以下に示す。The manufacturing conditions are shown below.
基板温度 ２００°Ｃ
反応圧力 ０． ０５ ＴｏｒｒＲｆＰｏｗｅｒ
５０ Ｗ
ガス ＮＨｚ ／ Ｓ ｉ Ｈａこの後こ
の基板（１）を反応室から取り出し、所定のパターンに
エツチングして、ゲート絶縁膜（５）とした、さらにＴ
ＰＴの外形のパターンにエツチングを施した後、この上
面全面に公知のスパッタリング法にて、アルミニウムを
形成した後、所定のパターンにエツチングして、ゲート
電極（６）、ソース電極（７）及びドレイン電極（８）
を形成し、図のようなＴＰＴを完成させた。Substrate temperature 200°C Reaction pressure 0. 05 TorrRfPower
50 W gas NHz/S i Ha After this, the substrate (1) was taken out from the reaction chamber and etched into a predetermined pattern to form a gate insulating film (5).
After etching the outer pattern of the PT, aluminum is formed on the entire upper surface by a known sputtering method, and then etched into a predetermined pattern to form the gate electrode (6), source electrode (7), and drain. Electrode (8)
was formed, and the TPT as shown in the figure was completed.
本実施例において、リンをドープする際には、加熱を行
わず、行っても十分にドーピングできるが、少し温度加
熱を行ってドーピングを行うと、速く終了する利点があ
る。この時の加熱温度はＴＰＴの作製工程で基板及び半
導体薄膜に加えられた温度以下にする。In this example, when doping phosphorus, sufficient doping can be achieved even if heating is not performed, but if doping is performed with a little temperature heating, there is an advantage that the doping can be completed quickly. The heating temperature at this time is lower than the temperature applied to the substrate and semiconductor thin film in the TPT manufacturing process.
このように本発明は、ＴＰＴの作製工程で基板及び半導
体薄膜に加えられた温度が最も高い温度とすることがで
き、後工程で高い温度を加える必要がなく、より信頷性
の高いＴＰＴを提供できる。In this way, the present invention allows the temperature applied to the substrate and the semiconductor thin film to be the highest temperature in the TPT manufacturing process, eliminating the need to apply high temperatures in the subsequent process, and creating a more reliable TPT. Can be provided.
本実施例においてレーザ光はエキシマレーザ光を用いた
が、その他のレーザ光でも実現可能である。Although an excimer laser beam is used as the laser beam in this embodiment, other laser beams can also be used.
さらに、本実施例で示したコプレナー型のＴＰＴのみに
限定されることなく、他の形式のＴＰＴにも適用可能で
ある。Furthermore, the present invention is not limited to the coplanar type TPT shown in this embodiment, but can also be applied to other types of TPT.
本発明のプラズマの効果を利用した不純物ドーピング技
術は上記のリンのみではなく、その他の■族又は■族の
不純物元素にしても適用可能である。The impurity doping technique using the plasma effect of the present invention can be applied not only to the above-mentioned phosphorus but also to other impurity elements of group (1) or group (2).
「効果１
以上説明した様に本発明によれば、ＴＰＴのソース、ド
レイン領域をプラズマ状態にされた■族又はＶ族元素雰
囲下にてレーザ光を照射してこれら不純物元素をドーピ
ングして形成してゆくので、より低温でこれら領域を形
成できる。"Effect 1 As explained above, according to the present invention, the source and drain regions of TPT are doped with these impurity elements by irradiating laser light in an atmosphere of group II or group V elements in a plasma state. These regions can be formed at lower temperatures.
また、高抵抗の非単結晶半導体層、ソース、ドレイン領
域及びゲート絶縁膜と連続して形成できるので、各層間
の界面特性が良くなり、かつ作製時間工程の短縮を実現
できる。Furthermore, since the high-resistance non-single-crystal semiconductor layer, the source and drain regions, and the gate insulating film can be formed continuously, the interface characteristics between each layer can be improved and the manufacturing time process can be shortened.
また、レーザ光の照射によってソース、ドレインが形成
できるので、その間隔を短くすることにより容易に短チ
ヤネル構造のＴＰＴを実現でき、高速応答性を持つＴＰ
Ｔを作製することができた。In addition, since the source and drain can be formed by irradiation with laser light, by shortening the interval between them, it is possible to easily realize a TPT with a short channel structure, and a TP with high-speed response.
We were able to create T.
このように本発明は、ＴＰＴの作製工程で基板及び半導
体薄膜に加えられた温度が最も高い温度とすることがで
き、後工程で高い温度を加える必要がなく、より信顧性
の高いＴＰＴを提供できる。In this way, the present invention allows the temperature applied to the substrate and semiconductor thin film to be the highest temperature in the TPT manufacturing process, eliminates the need to apply high temperatures in the post-process, and creates a more reliable TPT. Can be provided.
第１図（ａ）〜（Ｃ）は本発明の作製方法の概略を示す
。
第２図は従来のＴＰＴの構造を示す。
基板
高抵抗の非単結晶半導体層
ソース
ドレイン
ゲート絶縁膜
ゲート電極
ソース電極
ドレイン電極FIGS. 1(a) to (C) schematically show the manufacturing method of the present invention. FIG. 2 shows the structure of a conventional TPT. Substrate High resistance non-single crystal semiconductor layer Source Drain Gate Insulating film Gate electrode Source electrode Drain electrode
Claims (1)
の非単結晶半導体層を基板上に形成する工程と、前記高
抵抗の非単結晶半導体層をIII族又は、Ｖ族元素を含む
混合ガスプラズマ雰囲下に配置し、前記高抵抗の非単結
晶半導体層に対し、レーザ光を照射して、III族又はＶ
族元素をドーピングしてソースまたはドレイン領域を形
成する工程を含むことを特徴とした薄膜トランジスタ作
製方法。 ２、特許請求の範囲第１項において、レーザ光の照射し
てIII族又はＶ族の不純物をドーピングする際は、前記
高抵抗の非単結晶半導体層形成温度以下に基板温度を保
って行うことを特徴とする薄膜トランジスタ作製方法。[Claims] 1. A method for manufacturing a thin film transistor, which includes the steps of forming a high resistance non-single crystal semiconductor layer on a substrate, and forming the high resistance non-single crystal semiconductor layer in a group III or V group. A group III or V
1. A method for manufacturing a thin film transistor, comprising the step of doping a group element to form a source or drain region. 2. In claim 1, when doping with group III or group V impurities by laser beam irradiation, the substrate temperature is maintained below the formation temperature of the high-resistance non-single crystal semiconductor layer. A method for manufacturing a thin film transistor characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4422989A JPH02222545A (en) | 1989-02-23 | 1989-02-23 | Manufacture of thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4422989A JPH02222545A (en) | 1989-02-23 | 1989-02-23 | Manufacture of thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02222545A true JPH02222545A (en) | 1990-09-05 |
Family
ID=12685709
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4422989A Pending JPH02222545A (en) | 1989-02-23 | 1989-02-23 | Manufacture of thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02222545A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05275452A (en) * | 1992-03-25 | 1993-10-22 | Semiconductor Energy Lab Co Ltd | Thin film insulated-gate type semiconductor device and its manufacture |
| JPH05326430A (en) * | 1992-03-26 | 1993-12-10 | Semiconductor Energy Lab Co Ltd | Method and apparatus for laser treatment |
| JPH0799317A (en) * | 1993-08-12 | 1995-04-11 | Semiconductor Energy Lab Co Ltd | Insulated thin-film gate type semiconductor device and manufacture thereof |
| JP2000004026A (en) * | 1999-06-02 | 2000-01-07 | Semiconductor Energy Lab Co Ltd | Manufacture of mis-type semiconductor device |
| US6124155A (en) * | 1991-06-19 | 2000-09-26 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and thin film transistor and method for forming the same |
| US6331717B1 (en) | 1993-08-12 | 2001-12-18 | Semiconductor Energy Laboratory Co. Ltd. | Insulated gate semiconductor device and process for fabricating the same |
| US6358784B1 (en) | 1992-03-26 | 2002-03-19 | Semiconductor Energy Laboratory Co., Ltd. | Process for laser processing and apparatus for use in the same |
| US6417543B1 (en) | 1993-01-18 | 2002-07-09 | Semiconductor Energy Laboratory Co., Ltd. | MIS semiconductor device with sloped gate, source, and drain regions |
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| JPS57202729A (en) * | 1981-06-05 | 1982-12-11 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS62245674A (en) * | 1986-04-18 | 1987-10-26 | Seiko Epson Corp | Manufacture of semiconductor device |
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1989
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| JPS57202726A (en) * | 1981-06-05 | 1982-12-11 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS57202729A (en) * | 1981-06-05 | 1982-12-11 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS62245674A (en) * | 1986-04-18 | 1987-10-26 | Seiko Epson Corp | Manufacture of semiconductor device |
Cited By (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6335213B1 (en) | 1991-06-19 | 2002-01-01 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and thin film transistor and method for forming the same |
| US6847064B2 (en) | 1991-06-19 | 2005-01-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a thin film transistor |
| US6797548B2 (en) | 1991-06-19 | 2004-09-28 | Semiconductor Energy Laboratory Co., Inc. | Electro-optical device and thin film transistor and method for forming the same |
| US6756258B2 (en) | 1991-06-19 | 2004-06-29 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
| US6124155A (en) * | 1991-06-19 | 2000-09-26 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and thin film transistor and method for forming the same |
| US6166399A (en) * | 1991-06-19 | 2000-12-26 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix device including thin film transistors |
| US6887746B2 (en) | 1992-03-25 | 2005-05-03 | Semiconductor Energy Lab | Insulated gate field effect transistor and method for forming the same |
| JPH05275452A (en) * | 1992-03-25 | 1993-10-22 | Semiconductor Energy Lab Co Ltd | Thin film insulated-gate type semiconductor device and its manufacture |
| US6323069B1 (en) | 1992-03-25 | 2001-11-27 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a thin film transistor using light irradiation to form impurity regions |
| US6569724B2 (en) | 1992-03-25 | 2003-05-27 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate field effect transistor and method for forming the same |
| US6358784B1 (en) | 1992-03-26 | 2002-03-19 | Semiconductor Energy Laboratory Co., Ltd. | Process for laser processing and apparatus for use in the same |
| US7781271B2 (en) | 1992-03-26 | 2010-08-24 | Semiconductor Energy Laboratory Co., Ltd. | Process for laser processing and apparatus for use in the same |
| US6655767B2 (en) | 1992-03-26 | 2003-12-02 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display device |
| US7169657B2 (en) | 1992-03-26 | 2007-01-30 | Semiconductor Energy Laboratory Co., Ltd. | Process for laser processing and apparatus for use in the same |
| JPH05326430A (en) * | 1992-03-26 | 1993-12-10 | Semiconductor Energy Lab Co Ltd | Method and apparatus for laser treatment |
| US6417543B1 (en) | 1993-01-18 | 2002-07-09 | Semiconductor Energy Laboratory Co., Ltd. | MIS semiconductor device with sloped gate, source, and drain regions |
| US7351624B2 (en) | 1993-01-18 | 2008-04-01 | Semiconductor Energy Laboratory Co., Ltd. | MIS semiconductor device and method of fabricating the same |
| US6984551B2 (en) | 1993-01-18 | 2006-01-10 | Semiconductor Energy Laboratory Co., Ltd. | MIS semiconductor device and method of fabricating the same |
| US6437366B1 (en) | 1993-08-12 | 2002-08-20 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate semiconductor device and process for fabricating the same |
| JPH0799317A (en) * | 1993-08-12 | 1995-04-11 | Semiconductor Energy Lab Co Ltd | Insulated thin-film gate type semiconductor device and manufacture thereof |
| US6500703B1 (en) | 1993-08-12 | 2002-12-31 | Semicondcutor Energy Laboratory Co., Ltd. | Insulated gate semiconductor device and process for fabricating the same |
| US7381598B2 (en) | 1993-08-12 | 2008-06-03 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate semiconductor device and process for fabricating the same |
| US6331717B1 (en) | 1993-08-12 | 2001-12-18 | Semiconductor Energy Laboratory Co. Ltd. | Insulated gate semiconductor device and process for fabricating the same |
| JP2000004026A (en) * | 1999-06-02 | 2000-01-07 | Semiconductor Energy Lab Co Ltd | Manufacture of mis-type semiconductor device |
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