JPS62245674A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62245674A JPS62245674A JP8947186A JP8947186A JPS62245674A JP S62245674 A JPS62245674 A JP S62245674A JP 8947186 A JP8947186 A JP 8947186A JP 8947186 A JP8947186 A JP 8947186A JP S62245674 A JPS62245674 A JP S62245674A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- channel
- semiconductor layer
- semiconductor device
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 16
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 14
- 239000001257 hydrogen Substances 0.000 claims abstract description 14
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000010409 thin film Substances 0.000 claims abstract description 11
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 239000010408 film Substances 0.000 abstract description 5
- 230000001681 protective effect Effects 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 2
- 238000000137 annealing Methods 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- 229920005591 polysilicon Polymers 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000011534 incubation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に、薄膜シリ
コン半導体層を有する薄膜トランジスタ（以下、ＴＰＴ
と略す）で構成される半導体装置の特性向上に有効であ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, particularly a thin film transistor (hereinafter referred to as TPT) having a thin silicon semiconductor layer.
It is effective in improving the characteristics of semiconductor devices constructed with
本発明けＴＰＴで構成される半導体装置の製造時に、薄
り半導体層の少なくともチャンネル領域に不純物を混入
せしめる工程と水素を混入せしめる工程を設はたことを
特徴とする。The present invention is characterized in that a step of mixing an impurity into at least the channel region of the thin semiconductor layer and a step of mixing hydrogen are provided during manufacturing of the semiconductor device made of the TPT.
〔従来の技術及び発明が解決しようとする問題点〕従来
、ＴＴＦＴのチャンネル領域の該半導体層はオフ電流（
ゲート・ソース間電圧（Ｖ＋）８） ／ｌ（Ｑ 、ソー
ス・ドレイン間電圧（ＶＤ＝）を所定電圧印力ｐ時のソ
ース・ドレイン間電流（Ｉｎｌｌ） ）を最小とするた
め、真性型の半導体層、又は不純物の混入を行わないノ
ンドープの半導体層より形成されていた。[Problems to be solved by the prior art and the invention] Conventionally, the semiconductor layer in the channel region of a TTFT has an off-state current (
In order to minimize the gate-source voltage (V+) 8) /l (Q, source-drain current (Inll) when a given voltage is applied to the source-drain voltage (VD=), It is formed of a semiconductor layer or a non-doped semiconductor layer that is not mixed with impurities.
しかし、単に骸チャンネル領斌に、水素の混入をせしめ
ると第３図（ｃ）に示すように、オン電流ＶＧ８゜ＶＤ
８ ！−所安中電圧した時のよりｌ！ ？＋：増加し、
トランジスタ特性が向上するｈ″−、スレショルド電圧
？ｌ”−水素の混入号とともに動き、オフ電流を大幅に
増大せしめるため、水素を十分混入せしめ、トランジス
タ特性な向上させることができなかった。However, if hydrogen is simply mixed into the channel, as shown in Figure 3(c), the on-current VG8°VD
8! -More than when the voltage is low! ? +: Increase,
The transistor characteristics improve with h''-, threshold voltage ?l''-hydrogen contamination increases significantly the off-state current, and therefore it has not been possible to sufficiently incorporate hydrogen to improve the transistor characteristics.
本発明はかかる大小を除、去１７、前記薄膜半導体層の
チャンネル長域に十分の水素を混入せしめても、スレシ
ョルド電圧が動かず、高いオン−オフ比が得られるＴＰ
Ｔの半導体装置の製造方法を提供することを目的とした
ものである。The present invention eliminates the above-mentioned size.17.Even if a sufficient amount of hydrogen is mixed into the channel length region of the thin film semiconductor layer, the threshold voltage does not change and a high on-off ratio can be obtained.
The purpose of this invention is to provide a method for manufacturing a semiconductor device of T.
本発明はＴＰＴで構成される半導体装置において、薄膜
半導体層の少なくともチャンネル領域に不純物を混入せ
しめる工程と水素を混入せしめる工程を有し、かかる欠
点を除去したものである。The present invention eliminates such drawbacks in a semiconductor device composed of TPT, which includes a step of mixing an impurity into at least a channel region of a thin film semiconductor layer and a step of mixing hydrogen.
第３図に、従来のＴＰＴのトランジスタ特性を示す。た
て軸はソース・ドレイン電流、よこ軸はソース・ゲート
電圧、ソース・ドレイン電圧（ｖｐＩＩ）は５ｖで、チ
ャンネル長５μｍ、チャンネル巾１０μｍのＮチャンネ
ルのＴＰＴ ）ランジスタ特性を示したものである。Ｂ
けチャンネル領域の半導体層がノンドープのトランジス
タ特性ｓＣは該ＴＰＴに水素と混入したもので、オン電
流、スレショルド電圧が急峻に立ち上るカ、トランジス
タ類性がデプレッション型ｆ変り％特性の劣下が著しい
。FIG. 3 shows the transistor characteristics of a conventional TPT. The vertical axis is the source-drain current, the horizontal axis is the source-gate voltage, and the source-drain voltage (vpII) is 5 V, showing the characteristics of an N-channel TPT transistor with a channel length of 5 μm and a channel width of 10 μm. B
The characteristics sC of a transistor in which the semiconductor layer in the channel region is not doped is that the TPT is mixed with hydrogen, and the on-current and threshold voltage rise sharply, and the transistor characteristics are depletion type and the % change characteristics are significantly deteriorated.
ａｅｌｔ、、ｐチャンネルＴＰＴもスレッショルド電圧
がエンハンメントに動くことが押えられ同様の結果が得
られている。Similar results have been obtained for the aelt, p-channel TPT, in which the threshold voltage is prevented from shifting toward enhancement.
以下１本発明について、実施例をもとに詳細な説明を行
う。The present invention will be described in detail below based on examples.
箪１図（ａ＞〜（ハに、本発明による実施例の半導体装
置の製造工Ｓｔ示す。まず、石英ガラス等の絶縁基板１
２上に、熱ＯＶＤ法等によって、多結晶シリコン薄膜半
導体層１１を形成する。このとき凱らかじめ、後工桿（
力の水素注入工程によるスレッショルド電圧の移動を見
込んで、該半導体層１１に、ＮチャンネルＴＦＴならば
ポロン、又はヒ素周期律表の第■族を、ＰチャンネルＴ
］ｌ’Ｔならばリン等の周期律表第１族を混入せしめる
。混入せしめる方法として熱拡散法、イオンブランテー
シｌン法、−１！たけ該半導体層１１を形成時に、同時
にシボラン、アルシン、ホスフィン等を熱ＯＶＤによっ
て分解し混入せしめる方法があり、最適濃度けＮチャン
ネルＴＰＴでボロン、ヒ素ｈｚａ−８〜１０１６原子Ｐ
ＩＡ１Ｒ”、ｐチャンネルＴＰＴでリンめ１．１０−７
〜１０１５原子Ｖ個３である（笛１図（α））。Figures 1 (a) to (c) show a manufacturing process for a semiconductor device according to an embodiment of the present invention. First, an insulating substrate 1 made of quartz glass or the like is shown.
2, a polycrystalline silicon thin film semiconductor layer 11 is formed by a thermal OVD method or the like. At this time, Gai, Kajime, and Gokou (
In anticipation of the shift of the threshold voltage due to the hydrogen implantation process, poron in the case of an N-channel TFT or Group Ⅰ of the arsenic periodic table is added to the semiconductor layer 11, and a P-channel TFT is added to the semiconductor layer 11.
]l'T, Group 1 of the periodic table such as phosphorus is mixed. Methods for mixing include thermal diffusion method, ion blunting method, -1! When forming the semiconductor layer 11, there is a method in which ciborane, arsine, phosphine, etc. are decomposed and mixed at the same time by thermal OVD.
IA1R”, p channel TPT ring 1.10-7
~1015 V atoms 3 (Fig. 1 (α)).
次に、該半導体層１１を熱酸化し、ゲート層１３ゲート
電極１４を形成する（第１図（ｂ））。Next, the semiconductor layer 11 is thermally oxidized to form a gate layer 13 and a gate electrode 14 (FIG. 1(b)).
次に、ゲート電極をマスクにインブ→ンテーシ四ン法（
ハ））によって、Ｐチャンネル、又はＮチャンネルＴＰ
Ｔのソース及びドレイン便域を形成する（第１図（６）
）。Next, using the gate electrode as a mask, we performed an incubation method (
c)) P-channel or N-channel TP
Form the source and drain areas of T (Figure 1 (6)
).
次に、＃ＣｖＤ法等によって、相関絶縁膜１５を形成し
、その後２００℃〜５００℃の温度雰囲気下で、水素プ
ラズマ中で、プラズマ処理を行い、水素を混入せしめる
か（ｂ）、または、水！をインブランチ−シロン法によ
って注入（ｂ）Ｌ 、その伊２００℃〜５００℃で熱処
理を行い、水素を混入せしめる（第１回頭）。その俵、
コンタクトホールな形成、配線１６を行い（第１図（ｅ
） ）−最稜に侶護膜１７を形成する（第１図（ハ）。Next, the correlation insulating film 15 is formed by #CvD method or the like, and then plasma treatment is performed in hydrogen plasma in a temperature atmosphere of 200° C. to 500° C. to mix hydrogen (b), or water! (b) L is injected by the inbranch-Silon method, and then heat treated at 200°C to 500°C to mix hydrogen (first step). That bale,
Form contact holes and wires 16 (see Figure 1(e)
) - A protective film 17 is formed at the top edge (FIG. 1(c)).
第３図に実施例のＴＰＴ ）ランジスタ特性を示す。た
て軸ｈ；ソースのドレイン電流（工Ｏａ）、よこ軸力ソ
ース・ゲート電圧（ＶＧ） 、ソース・ドレイン電圧け
５Ｖ、チャンネル長５μ惜、チャンネル巾１０μｍのＮ
チャンネルＴＰＴのトランジスタ特性（Ａ）′Ｃあり、
第２図の従来のトランジスタに比してオン電流、オン、
オフ比ともに１ケタ以上特性ｂｔ向上する上、スレショ
ルド電圧の移動が皆無である優れ次トランジスタ特性を
示す。この効果けＰチャンネルＴＰＴも同様である。こ
のトランジスタを用いて、０ＭＯ８型のシフト・レジス
タを作製したところ、最大周波数１０ＭＨｇ以上のデー
タ転送が確認できた。このため本発・明１１を′、用１
いれば、１０Ｍ１（２以上の高速、高ｅｌｓ比の固体撮
像装置や、ドライバー内蔵の液晶表示装置に応用で鎗有
用である。FIG. 3 shows the TPT transistor characteristics of the example. Vertical axis h; source drain current (Oa), horizontal force source-gate voltage (VG), source-drain voltage 5V, channel length 5μm, channel width 10μm N
Transistor characteristics of channel TPT (A) with 'C,
Compared to the conventional transistor shown in Figure 2, the on-current,
In addition to improving both the off-ratio and the characteristic bt by more than one order of magnitude, it exhibits excellent next-order transistor characteristics with no shift in threshold voltage. The same applies to this effect P channel TPT. When a 0MO8 type shift register was fabricated using this transistor, data transfer at a maximum frequency of 10 MHg or higher was confirmed. Therefore, the present invention and invention 11 are
If possible, it would be useful in applications such as high-speed, high-ELS-ratio solid-state imaging devices of 10M1 (2 or higher) and liquid crystal display devices with built-in drivers.
第１図（ハ））〜のは本発明の半導体装置の製造方法を
示す図。
第２図は実施例のＴＰＴトランジスタ特性を示す図。
第３図は従来のＴＦ’Ｔ ）ランノスタ特性を示す図。
１１・・・・・・薄膜半導体層
１２・・・・・・絶縁基板
１３・・・・・・ゲート■１
１４・・・・・・ゲート電極
１５・・・・・・相関絶縁嘆
１６・・・・・・配線
１７・・・・・・保護膜
ｂ・・・・・・水素混入
Ａ、 Ｂ、 Ｏ・・・・・・トランジスタ特性以 上FIGS. 1(c) to 1(c) are diagrams showing a method for manufacturing a semiconductor device according to the present invention. FIG. 2 is a diagram showing the TPT transistor characteristics of the example. FIG. 3 is a diagram showing conventional TF'T) runnostar characteristics. 11... Thin film semiconductor layer 12... Insulating substrate 13... Gate ■1 14... Gate electrode 15... Correlation insulation layer 16. ...Wiring 17...Protective film b...Hydrogen contamination A, B, O...Transistor characteristics and above
Claims (1)
絶縁層、ソース及びドレイン電極を形成せしめる半導体
装置の製造方法において、該薄膜半導体層のチャンネル
領域に不純物を混入せしめる工程と水素を混入せしめる
工程を有する事を特徴とする半導体装置の製造方法。(1) In a method for manufacturing a semiconductor device in which a thin film semiconductor layer, a gate insulating layer, and source and drain electrodes are formed on an insulating substrate or an insulating layer, a step of mixing an impurity into a channel region of the thin film semiconductor layer and a step of mixing hydrogen. 1. A method for manufacturing a semiconductor device, comprising a step of increasing
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8947186A JPS62245674A (en) | 1986-04-18 | 1986-04-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8947186A JPS62245674A (en) | 1986-04-18 | 1986-04-18 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62245674A true JPS62245674A (en) | 1987-10-26 |
Family
ID=13971634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8947186A Pending JPS62245674A (en) | 1986-04-18 | 1986-04-18 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62245674A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02222545A (en) * | 1989-02-23 | 1990-09-05 | Semiconductor Energy Lab Co Ltd | Manufacture of thin film transistor |
| JPH02224341A (en) * | 1989-02-27 | 1990-09-06 | Semiconductor Energy Lab Co Ltd | Formation of thin film transistor |
| EP0884773A2 (en) * | 1997-06-09 | 1998-12-16 | Nec Corporation | Method of making an MIS transistor |
| US6232621B1 (en) | 1993-02-15 | 2001-05-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating the same |
-
1986
- 1986-04-18 JP JP8947186A patent/JPS62245674A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02222545A (en) * | 1989-02-23 | 1990-09-05 | Semiconductor Energy Lab Co Ltd | Manufacture of thin film transistor |
| JPH02224341A (en) * | 1989-02-27 | 1990-09-06 | Semiconductor Energy Lab Co Ltd | Formation of thin film transistor |
| US6232621B1 (en) | 1993-02-15 | 2001-05-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating the same |
| US6413842B2 (en) * | 1993-02-15 | 2002-07-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating the same |
| US7952097B2 (en) | 1993-02-15 | 2011-05-31 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating the same |
| EP0884773A2 (en) * | 1997-06-09 | 1998-12-16 | Nec Corporation | Method of making an MIS transistor |
| EP0884773A3 (en) * | 1997-06-09 | 2000-01-12 | Nec Corporation | Method of making an MIS transistor |
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