KR0174998B1 - MOS device and its manufacturing method - Google Patents
MOS device and its manufacturing method Download PDFInfo
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- KR0174998B1 KR0174998B1 KR1019910010229A KR910010229A KR0174998B1 KR 0174998 B1 KR0174998 B1 KR 0174998B1 KR 1019910010229 A KR1019910010229 A KR 1019910010229A KR 910010229 A KR910010229 A KR 910010229A KR 0174998 B1 KR0174998 B1 KR 0174998B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000009792 diffusion process Methods 0.000 claims abstract description 31
- 239000012535 impurity Substances 0.000 claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 239000013078 crystal Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 230000000903 blocking effect Effects 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 13
- 125000006850 spacer group Chemical group 0.000 claims description 5
- 230000008569 process Effects 0.000 abstract description 5
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 230000007547 defect Effects 0.000 abstract description 2
- 230000004913 activation Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- -1 arsenic ions Chemical class 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910015900 BF3 Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
본 발명은 MOS 디바이스 및 그 제조방법에 관한 것으로, 특히 제1전도형의 반도체기판의 표면근방에 상기 제1전도형과 반대형인 제2전도형의 불순물 확산영역으로 형성된 소스 및 드레인영역; 상기 소스영역 및 드레인영역 사이에 한정된 채널영역; 상기 채널영역상에 게이트절연막을 개재하여 형성된 게이트전극을 구비한 MOS 반도체장치에 있어서, MOSFET는 상기 소스 및 드레인영역 아래의 반도체기판에 각각 형성된 확산저지막을 더 구비한 것을 특징으로 한다. 또한, 이와 같은 MOS 디바이스의 제조방법을 제공한다. 따라서, 본 발명은 확산영역 아래에 확산저지막을 형성하여 불순물 확산을 저지함으로써 얕은 확산접합을 용이하게 얻을 수 있으며 후속공정의 온도조건을 자유롭게 할 수 있으며, 고온 열처리가 가능하므로 결정결함을 줄일 수 있고 불순물의 활성화를 완전하게 할 수 있다.The present invention relates to a MOS device and a method of manufacturing the same, in particular, a source and a drain region formed in the vicinity of the surface of the first conductive semiconductor substrate and the impurity diffusion region of the second conductive type opposite to the first conductive type; A channel region defined between the source region and the drain region; In the MOS semiconductor device having a gate electrode formed on the channel region via a gate insulating film, the MOSFET further comprises a diffusion blocking film formed on the semiconductor substrate under the source and drain regions, respectively. Also provided is a method of manufacturing such a MOS device. Therefore, the present invention can easily obtain a shallow diffusion bonding by forming a diffusion blocking film under the diffusion region to prevent the diffusion of impurities, free the temperature conditions of the subsequent process, high temperature heat treatment can be reduced to reduce the crystal defects It is possible to complete the activation of the impurities.
Description
제1도는 종래의 MOSFET 구조를 나타낸 도면.1 is a diagram showing a conventional MOSFET structure.
제2도는 본 발명에 의한 MOSFET 구조를 나타낸 도면.2 is a diagram showing a MOSFET structure according to the present invention.
제3a도∼제3d도는 본 발명에 의한 MOSFET의 제조방법을 나타낸 공정 순서도.3A to 3D are process flowcharts showing a method for manufacturing a MOSFET according to the present invention.
본 발명은 MOS 디바이스 및 그 제조방법에 관한 것으로, 특히 얕은 접합을 가진 MOSFET(Metal Oxide Semiconductor Field Ecffect Tramsistor) 및 그 제조방법에 관한 것이다.TECHNICAL FIELD The present invention relates to a MOS device and a method for manufacturing the same, and more particularly to a MOSFET (Metal Oxide Semiconductor Field Effect Tramsistor) having a shallow junction and a method for manufacturing the same.
제1도를 참조하면 MOSFET는 반도체기판(1)의 표면근방에 형성된 소스 및 드레인영역(2)(3) 사이에 채널영역(4)을 가지며, 이 채널영역(4)상에 박막의 게이트절연막(5)을 개재하여 형성된 게이트전극(6)을 가진다. 이러한 MOSFET는 반도체장치의 고집적화 및 고속화 추세에 따라 게이트길이가 서브미크론 이하로 짧아지고 있고, 게이트길이가 짧아짐에 따라 소스 및 드레인영역도 얕은 접합이 요구되고 있다.Referring to FIG. 1, the MOSFET has a channel region 4 between the source and drain regions 2 and 3 formed near the surface of the semiconductor substrate 1, on which the gate insulating film of the thin film is formed. It has the gate electrode 6 formed through (5). These MOSFETs have shorter gate lengths of less than submicrons due to the trend of higher integration and higher speed of semiconductor devices, and as the gate lengths become shorter, shallower junctions of source and drain regions are required.
왜냐하면, 고집적화에 따라 디바이스의 치수는 감소되었으나 전원전압은 5V로 일정하므로 디바이스 내부의 전계강도가 증대된다. 그러므로 소스 및 드레인영역에서 채널영역측에 미치는 공핍층(7)의 영향으로 유효채널길이(Leff)가 더욱 짧아지게 되므로 스레쉬홀드전압이 저하된다. 따라서, 쇼트채널효과로 스레쉬홀드전압이 변동되는 것을 억제하기 위해서는 소스 및 드레인영역에서 채널영역측으로 퍼지는 공핍층의 영향을 작게하지 않으면 안되므로 소스 및 디바이스의 확산접합의 깊이(Xj)를 엷게 하는 기술이 요구되고 있다. 이와 같은 요구에 부응하여 최근에는 비정이 작고 열확산계수가 작은 비소이온(As+) 및 불화붕소이온(BF2 +)을 불순물로 사용함으로써 0.09μm의 엷은 접합을 얻고 있다.Because of the high integration, the dimensions of the device are reduced, but since the power supply voltage is constant at 5V, the electric field strength inside the device is increased. Therefore, the effective channel length Leff is further shortened by the influence of the depletion layer 7 on the channel region side in the source and drain regions, so that the threshold voltage is lowered. Therefore, in order to suppress the change in the threshold voltage due to the short channel effect, the effect of the depletion layer spreading from the source and drain regions to the channel region side must be reduced, so that the depth of the diffusion junction (Xj) between the source and the device is reduced. This is required. In response to such a demand, a thin bond of 0.09 µm has recently been obtained by using arsenic ions (As + ) and boron fluoride ions (BF 2 + ) as impurities as impurities with a small specificity and a small thermal diffusion coefficient.
그러나, 비정이 작고 열확산계수가 작은 불순물이온을 사용하는 방법은 보다 옅은 접합을 형성하는데는 한계가 있으며, 불순물영역을 형성한 후에 계속 진행되는 후속 열처리공정에 의해 불순물영역이 확장되므로 후속 공정의 엄격한 저온화가 요구된다.However, the method of using impurity ions having a small specificity and a small thermal diffusion coefficient has a limitation in forming a lighter junction, and since the impurity region is extended by a subsequent heat treatment process after the impurity region is formed, Lower temperature is required.
본 발명의 목적은 상기와 같은 종래기술의 문제점을 해결하기 위하여 후속 열처리공정의 온도에 관계없이 옅은 접합을 형성하는 MOS 디바이스 및 그 제조방법을 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a MOS device and a method of manufacturing the same, which form a thin junction regardless of the temperature of a subsequent heat treatment process in order to solve the above problems of the prior art.
상기 목적을 달성하기 위한 본 발명의 MOS 디바이스는 제1전도형의 반도체기판의 표면근방에 상기 제1전도형과 반대형인 제2전도형의 불순물 확산영역으로 형성된 소스 및 드레인영역; 상기 소스영역 및 드레인영역 사이에 한정된 채널영역; 상기 채널영역상에 게이트절연막을 개재하여 형성된 게이트전극을 구비한 MOS 반도체장치에 있어서, 상기 소스 및 드레인영역 아래의 반도체기판에 각각 형성된 확산저지막을 더 구비한 것을 특징으로 한다.The MOS device of the present invention for achieving the above object is a source and drain region formed in the vicinity of the surface of the first conductive semiconductor substrate of the impurity diffusion region of the second conductivity type opposite to the first conductivity type; A channel region defined between the source region and the drain region; A MOS semiconductor device having a gate electrode formed on the channel region with a gate insulating film interposed therebetween, further comprising a diffusion blocking film formed on each of the semiconductor substrates below the source and drain regions.
상기 MOS 디바이스를 제조하는데 가장 적합한 제조방법은 확산접합 아래에 확산저지막을 가지는 MOS 반도체장치의 제조방법에 있어서, 제1전도형의 반도체기판에 필드산화막을 형성하여 액티브영역을 한정하고, 이 액티브영역상에 박막의 실리콘산화막을 형성하는 공정; 상기 실리콘산화막에 개구를 형성하고 이 개구에 노출된 반도체기판을 선택적으로 에피택셜 성장시켜 상기 실리콘산화막 상에 단결정층을 형성하는 공정; 상기 개구에 오버랩되는 단결정층상에 게이트산화막 및 게이트전극을 형성하는 공정; 및 상기 게이트전극에 셀프얼라인되게 상기 단결정층의 표면근방에 상기 제1전도형과의 반대형인 제2전도형의 불순물 확산영역을 형성하는 공정으로 구비한 것을 특징으로 한다.A manufacturing method most suitable for manufacturing the MOS device is a method of manufacturing a MOS semiconductor device having a diffusion blocking film under a diffusion junction, wherein a field oxide film is formed on a first conductive semiconductor substrate to define an active region. Forming a thin silicon oxide film on the substrate; Forming an opening in the silicon oxide film and selectively epitaxially growing a semiconductor substrate exposed to the opening to form a single crystal layer on the silicon oxide film; Forming a gate oxide film and a gate electrode on the single crystal layer overlapping the opening; And forming an impurity diffusion region of a second conductivity type opposite to the first conductivity type near the surface of the single crystal layer so as to be self-aligned with the gate electrode.
이하 첨부한 도면을 참조하여 본 발명을 보다 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2도를 참조하면, 본 발명에 의한 MOS 디바이스, 즉 MOSFET는 소스 및 드레인영역(2)(3) 아래에 예컨대, 박막의 실리콘산화막과 같은 확산저지막(8)을 각각 구비한다. 소스 및 드레인영역(2)(3)은 채널과의 사이에 저농도로 또는 완만한 프로파일을 가진 불순물층을 가지는 LDD(Lightly Doped Drain) 구조를 이룬다. 소스 및 드레인영역(2)(3)의 단결정층(9)은 게이트전극(6) 아래에 확산저지막(8)이 형성되어 있지 않은 노출된 반도체기판(1)으로부터 선택적인 에피택셜 성장(SEG) 방법에 의해 성장된 실리콘 단결정층내에 이온주입 또는 불순물확산 방법으로 형성한다. 따라서 접합길이(Xj)는 SEG(Seletive Epitoxial Grawing)층(9)의 성장두께로 결정된다. 미설명부호 10은 게이트측벽 스페이서이다.Referring to FIG. 2, the MOS device, i.e., the MOSFET according to the present invention, has a diffusion blocking film 8 such as, for example, a thin silicon oxide film under the source and drain regions 2 and 3, respectively. The source and drain regions 2 and 3 form an LDD (Lightly Doped Drain) structure with an impurity layer having a low concentration or a gentle profile between the channels. The single crystal layer 9 of the source and drain regions 2 and 3 is selectively epitaxially grown (SEG) from the exposed semiconductor substrate 1 having no diffusion blocking film 8 formed under the gate electrode 6. It is formed by ion implantation or impurity diffusion in the silicon single crystal layer grown by the method. Therefore, the junction length Xj is determined by the growth thickness of the SEG (Seletive Epitoxial Grawing) layer 9. Reference numeral 10 denotes a gate side wall spacer.
이와 같은 본 발명의 MOSFET의 제조방법을 제3a도부터 제3d도에 도시한 도면을 참조하여 설명한다.Such a method of manufacturing the MOSFET of the present invention will be described with reference to the drawings shown in FIGS. 3A to 3D.
제3a도를 참조하면, 실리콘기판(1)상에 필드산화막을 형성하여 액티브영역을 한정한 후, 액티브영역에 1000∼2000Å 정도의 실리콘산화막(11)을 형성한다. 제3b도를 참조하면, 실리콘산화막(11)에 개구(12)를 형성하고, 이 개구(12)내에 노출된 실리콘기판(1)을 시드(seed)로 하여 선택적으로 실리콘단결정을 에피택셜성장시켜 확산저지막(8)으로 제공되는 선택적인 에피택셜 성장된 단결정층(9)을 상기 실리콘산화막(11)상에 형성한다. 제3c도를 참조하면, 성장된 단결정층(9)상에 개구(12)와 오버랩되게 게이트산화막(5) 및 게이트전극(6)을 형성한다. 이어서, 불순물이 저농도로 도우프된 불순물영역(2a)(3a)을 게이트전극(6)에 셀프얼라인되게 단결정층(9)의 표면근방에 형성한다. 제3d도를 참조하면, 게이트전극(6)의 측벽에 산화막과 같은 절연막으로 된 게이트측벽 스페이서(10)를 형성하고, 이어서 불순물이 고농도로 도우프된 불순물영역(2)(3)은 게이트측벽 스페이서(10)에 셀프얼라인되게 단결정층(9)의 표면근방에 형성한다. 따라서 불순물영역(2)(3)은 하부의 확산저지막(8)에 의해 하방으로 불순물이 확산되는 것이 방지되므로 얕은 접합을 형성하는 것이 용이하다. 또한, 고온 어닐링이 가능하므로 기판에 존재하는 결정결함의 완화가 가능하며 불순물의 완전한 활성화가 가능하다. 그리고 후속공정의 열처리 온도 선택범위를 자유로이 설정할 수 있는 이점이 있다. 여기서 n-채널 MOSFET인 경우에는 불순물영역(2)(3)은 n+형이고, 불순물영역(2a)(3a)는 n-형이다.Referring to FIG. 3A, after forming a field oxide film on the silicon substrate 1 to define an active region, a silicon oxide film 11 of about 1000 to 2000 microseconds is formed in the active region. Referring to FIG. 3B, an opening 12 is formed in the silicon oxide film 11, and a silicon single crystal is selectively epitaxially grown using the silicon substrate 1 exposed in the opening 12 as a seed. An optional epitaxially grown single crystal layer 9 provided as a diffusion blocking film 8 is formed on the silicon oxide film 11. Referring to FIG. 3C, the gate oxide film 5 and the gate electrode 6 are formed on the grown single crystal layer 9 so as to overlap the opening 12. Subsequently, impurity regions 2a and 3a doped with impurities at low concentration are formed near the surface of the single crystal layer 9 so as to self-align with the gate electrode 6. Referring to FIG. 3D, a gate side wall spacer 10 made of an insulating film such as an oxide film is formed on the sidewall of the gate electrode 6, and then the impurity regions 2 and 3 doped with a high concentration of impurities are gate side walls. It is formed near the surface of the single crystal layer 9 so as to be self-aligned with the spacer 10. Therefore, the impurity regions 2 and 3 are prevented from diffusing impurities downward by the lower diffusion blocking film 8, so that it is easy to form a shallow junction. In addition, the high temperature annealing is possible, so that crystal defects existing in the substrate can be alleviated and impurities can be fully activated. And there is an advantage that can be freely set the heat treatment temperature selection range of the subsequent process. In the case of an n-channel MOSFET, the impurity regions 2 and 3 are n + type, and the impurity regions 2a and 3a are n − type.
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