GB2150348A - Insulated-gate field-effect transistors and their manufacture - Google Patents
Insulated-gate field-effect transistors and their manufacture Download PDFInfo
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- GB2150348A GB2150348A GB08331836A GB8331836A GB2150348A GB 2150348 A GB2150348 A GB 2150348A GB 08331836 A GB08331836 A GB 08331836A GB 8331836 A GB8331836 A GB 8331836A GB 2150348 A GB2150348 A GB 2150348A
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- 230000005669 field effect Effects 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000002019 doping agent Substances 0.000 claims abstract description 64
- 238000000034 method Methods 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 10
- 230000000873 masking effect Effects 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 230000000717 retained effect Effects 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000002513 implantation Methods 0.000 description 6
- -1 boron ions Chemical class 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 101150068246 V-MOS gene Proteins 0.000 description 4
- 239000007943 implant Substances 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005094 computer simulation Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
An insulated-gate field-effect transistor, for example of the vertical D-MOS type, is manufactured to have a low gate threshold voltage and a short channel (33) but a high source-drain punch-through voltage, as a result of providing an additional dopant concentration (20) in the part of the opposite conductivity type channel region (2) adjacent the source region (1). This additional dopant concentration (20) partially compensates the higher dopant concentration in this part of the channel region which would otherwise result in a higher threshold voltage. <IMAGE>
Description
SPECIFICATION
Insulated-gate field-effect transistors and their manufacture
This invention relates to methods of manufacturing an insulated-gate field-effect transistor, for example of the power D-MOST and V-MOST types, and further relates to such insulated-gate field-effect transistors having low threshold voltages.
Methods of manufacturing an insulated-gate field-effect transistor are known, including the steps of (a) providing a semiconductor body having a body portion of one conductivity type which is associated with a drain of the transistor, (b) introducing dopant of opposite conductivity type into at least one area of the body portion to form a first region of the opposite conductivity type, (c) introducing dopant of the one conductivity type into at least part of the at least one area to provide a source region of the one conductivity type which in the manufactured device is separated from the body portion of the one conductivity type by the first region of the opposite conductivity type, the dopant concentration of said opposite conductivity type of said first region being higher adjacent the source region than adjacent the body portion, and (d) providing a conductive layer on an insulating layer at least at a surface-adjoining part of the first region extending between the source region and the body portion to form an insulated gate of the transistor.
Different specific types of transistor structure manufactured by such a known method are described in, for example, I.E.E.E. Transactions on
Electron Devices: Vol. ED-25, No. 11 (November 1978), pages 1325 to 1327, and Vol. ED-27, No. 2, (February 1980), pages 340 to 343; and Electronics: 22 November 1979, pages 85 to 86 and 28 August 1980, pages 145 to 147; and United States Patent (US-A) 4364073. In most cases the dopant of the one conductivity type is introduced into the body through at least part of a window in a masking pattern on the body, through which window the dopant of said opposite conductivity type is also introduced. The length of the transistor channel is determined by the extent to which the first region dopant is introduced further into the body than the source region at, for example, the window edge.At least part of the masking pattern may be retained in the manufactured device, for example at least on the surface-adjoining part of the first region, as for example an insulating layer or/and at least part of the gate of the transistor.
The article in I.E.E.E. Transactions ED-25 describes a high voltage double-diffused lateral D
MOS transistor in which the source and first regions are diffused into the body portion (an epitaxial layer) and in which a drain region is also present and contacted at the same major surface of the body as the source and first regions. This particular D-MOS transistor is also suitable for incorporation in a monolithic integrated circuit. The article in I.E.E.E. 'Transaction ED-27 describes a high power, double-diffused vertical D-MOS transistor in which the source and first regions are diffused into the body portion (an epitaxial layer) and in which a drain region is provided by the substrate and contacted at the opposite major surface of the body from the source and first regions.The 1979 article in Electronics describes power V-MOS
Transistors which have a vertical source-drain configuration and a groove extending through the double-diffused source and first regions, the insulated gate being present on the walls of the groove. The 1980 article in Electronics describes a high power vertical transistor of the D-MOS type in which the source and first regions are formed by a double implantation instead of double diffusion.
Non-power types of such insulated-gate field-effect transistors are also fabricated in integrated circuits, especially in a lateral D-MOS configuration. In this case, the bulk of the semiconductor body may form a common body portion of a plurality of such transistors. US-A 4364073 describes another form of high power, double-diffused vertical D-MOS transistor in which an epitaxial layer which provides the body portion associated with the drain is present on a substrate of the opposite conductivity type to provide an anode region for the transistor.
Low gate threshold voltages (for example about 2 volts) are often required for insulated-gate fieldeffect transistors, for example for power D-MOS or
V-MOS transistors driven by transistor-transistor logic (TTL) circuits. It is known to reduce the threshold voltage by choosing a lower doping concentration of said opposite conductivity type for the first region. However, as described in for example the I.E.E.E. Transactions ED-25 article, the reducing of threshold voltage in this known manner reduces the drain-to-source punch-through voltage for a given channel length. In order to maintain an acceptable punch-through voltage with low threshold voltages, a lower doping concentration of the one conductivity type can be used for the body portion as suggested in the I.E.E.E. Transactions ED-25 article.Such a reduction in the doping concentration of the body portion leads to a higher on-resistance for the transistor, and this is often not desirable. Therefore in order to maintain a high punch-through voltage it is often necessary to adopt a longer channel length and a higher threshold voltage than would otherwise be desirable.
The I.E.E.E. Transactions ED-25 article describes an optimised power D-MOST structure in which, with an epitaxial-layer body portion having a dopant concentration of 1 x 1015 cm-3 to minimise on-resistance, the minimum threshold voltage which can be obtained is 4 volts for a channel length of 3 micrometres with a source-drain punch- through voltage of at least 200v. As illustrated in
Figure 2 of said I.E.E.E. Transactions ED-25 article, for a threshold voltage of 2 volts, the punchthrough voltage would be less than 50 volts with a channel length of 3 micrometres and less than 30 volts for a channel length of 2 micrometres.
The present invention provides a method of manufacturing an insulated-gate field-effect transistor as well as a transistor itself which can have a low threshold voltage, an acceptably low on-resistance, and a short channel, but with a high immunity to short-channel effects such as punch-through at high drain bias voltages. Furthermore, the manufacture of the transistor can be performed without requiring additional mask alignment steps compared with previously used methods of manufacturing an insulated-gate field-effect transistor.
According to a first aspect of the present invention there is provided a method of manufacturing an insulated-gate field-effect transistor including the steps of: (a) providing a semiconductor body having a body portion of one conductivity type which is associated with a drain of the transistor, (b) introducing dopant of opposite conductivity type into at least one area of the body portion to form a first region of the opposite conductivity type, (c) introducing dopant of the one conductivity type into at least part of the at least one area to provide a source region of the one conductivity type which in the manufactured device is separated from the body portion of the one conductivity by the first region of the opposite conductivity type, the dopant concentration of said opposite conductivity type of said first region being higher adjacent the source region than adjacent the body portion, and (d) providing a conductive layer on an insulating layer at least at a surface-adjoining part of the first region extending between the source region and the body portion to form an insulated gate of the transistor, characterised in that, in addition to the dopant introduction to form the source region, a dopant introduction step is effected to provide an additional dopant concentration of the one conductivity type in the part of the body which in the manufactured device is a part of the first region adjacent the source region and below the in sulated s;;3id~additional dopant concentration being of the same order of magnitude as said' higher dopant concentration of the first region and thereby serving to reduce the threshold voltage of the transistor.
According to a second aspect of the invention there is provided an insulated-gate field-effect transistor comprising a semiconductor body having a body portion of one conductivity type which is associated with a drain of the transistor, a source region of the one conductivity which is separated from the body portion of the one conductivity by a first region of the opposite conductivity type, the dopant concentration of said opposite conductivity type of said first region being higher adjacent the source region than adjacent the body portion, and a conductive layer on an insulating layer at least at a surface-adjoining part of the first region extending between the source region and the body portion to form an insulated gate of the transistor, characterised in that, in addition to the dopant concentration provided in the body to form the source region, an additional dopant concentration of the one conductivity type is present in the part of the first region adjacent the source region and below the insulated gate, said additional dopant concentration being of the same order of magnitude as said higher dopant concentration of the first region and thereby serving to reduce the threshold volts age of the transistor.
Surprisingly it has been found that by providing such an additional dopant concentration of the one conductivity type in this part of the first region to compensate partially the higher dopant concentration adjacent the source region, a low threshold voltage can be obtained while maintaining a high punch-through voltage.
These and other features in accordance with the invention will now be described with reference to the accompanying drawings to illustrate, by way of example, a few embodiments of the invention. In these drawings:
Figure l is a schematic sectional view of part of a high voltage D-MOST structure in accordance with the invention;
Figure 2 is a graph of nett doping concentration (N) with lateral distance (X) across part of the source region, channel region and drain drift region of one example of the Figure 1 structure;
Figure 3 is a cross-sectional view of part of a power D-MOS transistor during manufacture by a method in accordance with the invention;
Figure 4 is a cross-sectional view of the part of
Figure 3 in its final form, and
Figure 5 is a cross-sectional view of part of a power V-MOS transistor manufactured in accordance with the present invention.
It should be noted that all the Figures (except
Figure 2) are diagrammatic and not drawn to scale.
In particular the relative dimensions and proportions of some parts of the cross-sectional views have been shown greatly exaggerated or reduced for the sake of convenience and clarity in the drawings. The same reference numerals as used in one embodiment are generally used to refer to corresponding or similar parts in the other embodiments.
Figure 1 lustrates ananWrns,u lated-gate field-effect transistor of the D-MOST type comprising a monocrystalline silicon semiconductor body 10 having an n-type body portion 3 which is a low doped (n-) drift region associated with the drain of the transistor. A higher doped (n+) source region 1 of n type conductivity is separated from the drain drift region 3 by a p type region 2. Regions 1 and 2 are formed by introducing donor and acceptor dopant respectively into an area of the body portion 3 by, for example, implantation and/or diffusion performed in known manner. The acceptor dopant concentration of the p type region 2 decreases with distance into the body portion 3 and so is higher adjacent the source region 1 than adjacent the drain drift region 3.
A conductive layer 12 is provided on an insulating layer 22 at least at a surface-adjoining part 33 of the p type region 2 extending between the source region 1 and the drain drift region 3 to form an insulated gate of the transistor. This gate layer 12 may comprise, for example, highly-doped polycrystalline silicon, aluminium, other metals, or metal silicides, and the insulating layer 22 may comprise, for example, thermally grown silicon dioxide or other suitable dielectric materials. In op eration an n type conductive channel is capacitively induced in the part 33 in known manner by signals on the insulated gate 12.
The source region is contacted by a source electrode 11 at a window in the insulating layer 22, and in the example illustrated in Figure 1 this source electrode 11 is also connected to the p type region 2 by a more highly doped (p+) contact region 32 of p type conductivity which is also present at the source contact window. The schematic of Figure 1 is applicable to both vertical and lateral
D-MOST configurations. In a vertical configuration the drain drift region 3 may be an epitaxial layer on a higher-doped n-type substrate 4 which provides the drain region and which is contacted at the opposite major surface by a drain electrode 14, see for example Figure 4. In a lateral configuration the drain region 4 and drain electrode 14 are provided at the same surface of the body 10 as the regions 1 and 2 and the source electrode 11.For a vertical power device a large number of transistor cell areas each similar to Figure 1 may be present as in, for example, Figure 4, and these cell areas may be arranged in any suitable power device geometry such as, for example, polygonal array or interdigitated geometries.
In accordance with the present invention an additional dopant concentration 20 of the same conductivity type (n type) as the drain drift region 3 is provided in the channel part of the body 10 below the insulated gate 12 where the p type region 2 has a high dopant concentration adjacent the source region 1. This additional dopant concentration 20 is provided by effecting a donor dopant introduction step (for example by ion implantation and/or diffusion) in addition to the donor introduction to form the source region 1. The donor concentration 20 is of the same order of magnitude as the high acceptor concentration of the region 2 adjacent the source region 1 while retaining the p type conductivity of the region 2 in that part of the body.In this manner the threshold voltage of the transistor is reduced while still maintaining a source-drain punch-through voltage similar to that which would be obtained with said high acceptor concentration in the absence of the further donor concentration 20.
An example of the provision of such an additional donor concentration 20 will now be described with reference to Figure 2 which shows a computer plot of nett doping concentration (N is dopant atoms/cm3) with lateral distance (X in micrometres) across part of the source region 1, p- type region 2 and drain drift region 3. The lateral distance X extends through the channel area 33 below the insulated gate 12 and so is parallel to the upper major surface of the body 10 in Figure 1.
The plot is based on a computer model of the distribution of dopant implanted at a window in a masking layer at the upper major surface and diffused laterally beyond the window edge by subsequent heating. The origin of the X-axis is taken in line with the window edge of the masking layer and so is aligned with the edge of the gate layer 12 in the Figure 1 example.
The lines plotted in Figure 2 represent a monocrystalline silicon body portion 3 having a uniform donor concentration (n-) of 1 x 1015 cm-3, an implant dose of 5 x1012 boron ions cm-2 which is diffused to a depth of 3.5 micrometres to provide an acceptor concentration p' for the region 2, and an implant dose of 5 x 1015 phosphorus ions cm-2 which is diffused to a depth of 1.1 micrometi-es to provide a donor concentration n+ for the source region 1. As can be seen from Figure 2, the acceptor concentration p' is much higher (in this example, about 5 x 10'6cm3) adjacent the source region 1 than adjacent the drain drift region 3.In the absence of the additional donor concentration 20 this high acceptor concentration p' in the channel part adjacent the source region 1 results in a moderately high threshold voltage; for example with the doping concentration profile p' of Figure 2 and a doped polycrystalline silicon gate 12 on a 0.1 micrometre thick layer 22 of thermally grown silicon dioxide, a gate threshold voltage of about 4 volts may be obtained in the absence of the additional donor concentration 20.
However in accordance with the present invention an additional donor concentration 20 of the same order of magnitude as the high acceptor concentration p' is provided in the Figure 2 structure by an implant dose of 5 x 1013 cm 2 phosphorus ions diffused approximately two-thirds the distance of the boron dopant to compensate partially this high acceptor concentration p' adjacent the source region 1. As a result, the nett acceptor doping concentration of the region 2 over about half the channel length adjacent the source region 1 is reduced as illustrated by the solid line p in Figure 2. However, as can be seen from Figure 2, the p-n junction formed with the source region is not significantly shifted.In the example of Figure 2, this nett acceptor concentration p now has a peak of about 2 x 1016 cm-3 a short distance in the transistor channel from the source region 1. In this manner the threshold voltage is reduced from about 4 volts to about 2 volts.
The provision of the additional donor concentration 20 does not affect significantly the sourcedrain punch-through of the device, provided the diffusion of the donor concentration 20 does not extend so far as to modify significantly the diffusion tail of the region 2 in the vicinity of its junction with the region 3. Thus, in the example of
Figure 2 even though the channel length is only about 2 micrometres a source-drain punch-through voltage of at least 200 volts can be achieved even with a reduced threshold voltage of 2 volts.
Figures 3 and 4 illustrate one example of the manufacture of such an insulated-gate field-effect transistor by a method in accordance with the invention. The region structure shown in Figure 3 may be manufactured using known technologies.
Thus, the deep p+ contact regions may be formed by boron diffusion in an n-epitaxial layer 3 on an n+ substrate 4, after which an insulating layer 22' of thermally grown silicon dioxide may be formed on the epitaxial layer surface 31. A part of the layer 22' subsequently provides the final gate dielectric 22. The gate layer 12 may then be provided as part of an implantation mask for forming the p type region 2, the additional donor concentration 20 and the source region 1. The gate layer 12 may have a grid geometry, and the implantation mask may comprise islands 12' formed at the same time as the grid 12 and serving to mask part of the contact regions 32 against the implants.
Figure 3 illustrates a stage in the manmask 12, 12' as were used for the p type region 2. These implanted phosphorus ions may be diffused in the semiconductor body by subsequent heating in order to achieve the desired doping profile in the part of the channel adjacent the source region 1.
The combination of implantation and diffusion permits good control of the doping profile. The source region 1 may then be formed by a higher dose of phosphorus ions implanted through the same mask windows but diffused to a lesser extent than the donor concentration 20. Subsequently the mask islands 12' are removed, and contact windows are opened after, for example, coating the retained gate layer 12 with insulating material.
Electrode metallization is then provided for the source contact 11, gate connection (not shown) and drain contact 14. The final transistor structure is shown in Figure 4.
Many modifications are possible within the scope of the invention. Thus, for example, the masking pattern for the source and p-type regions 1 and 2 and dopant concentration 20 may be defined in the insulating layer 22' as well as or even instead of being in a gate layer 12, 12'. The island area 12' of the masking pattern may be omitted, at least when providing the acceptor concentration for the region 2. The dopant concentration in the regions 1 and 2 may be introduced into the body by thermal diffusion instead of using ion implantation, although ion implantation is preferred as it provides tighter control of the dopant concentrations especially for the area of the region 2 adjacent the region 1.
In the method of Figures 3 and 4, at least part of the insulated gate structure 12, 22 is formed before the dopant introduction steps for the regions 1 and 2 and dopant 20. However the insulated gate structure of a transistor in accordance with the invention may be formed subsequently. By way of example Figure 5 illustrates a transistor of the V
MOS type in which, after forming the regions 1 and 2 and dopant concentration 20, a groove 40 is etched into the body portion 3 through part of the regions 1 and 2, and the insulated gate 12, 22 is then formed on a part of the region 2 at side-wall of the groove 40.In this case the effective dopant concentration 20 in the channel of the transistor extends along the side-wall of the groove 40 and has a profile formed by vertical diffusion in the body, instead of the laterally-diffused profile at the upper major surface 31 which is effective in the
Figure 4 transistor.
In such a V-MOS transistor in accordance with the invention implantation and diffusion steps for providing the dopant concentration 20 and the regions 1 and 2 need not be masked at the upper major surface 31, except possibly around the periphery of the active device. However Figure 5 illustrates a modification which is in accordance with the invention disclosed in published European Patent Application 0081269 (our reference PHB 32842) in which a Schottky junction is formed between the source electrode 11 and a part 32' of the drain-drift region 3 surrounded by the regions 1 and 2. This transistor can have a high switching speed even when driving inductive loads. In this case a masking pattern comprising island areas similar to islands 12' may be used to mask the parts 32' when providing grid-shaped regions 1 and 2 and dopant concentration 20.
Although n channel MOSFETs have been illustrated, opposite conductivity type dopants may be used for the various regions to form p channel devices. Furthermore, the present invention may be employed in a wide variety of types of insulatedgate field-effect transistor, for example, such as the other known types of transistor already described.
Thus, an additional doping concentration 20 in accordance with the present invention may be incorporated in vertical D-MOS transistors having a substrate 4 of opposite conductivity type forming an anode region on which the epitaxial drain-drift layer 3 is formed, as well as in, for example, lateral
D-MOS transistors. The invention may also be used with insulated-gate field-effect transistors formed in other semiconductor materials, for example gallium arsenide.
Claims (9)
1. A method of manufacturing an insulated-gate field-effect transistor including the steps of: (a) providing a semiconductor body having a body portion of one conductivity type which is associated with a drain of the transistor, (b) introducing dopant of opposite conductivity type into at least one area of the body portion to form a first region of the opposite conductivity type, (c) introducing dopant of the one conductivity type into at least part of the at least one area to provide a source region of the one conductivity type which in the manufactured device is separated from the body portion of the one conductivity by the first region of the opposite conductivity type, the dopant concentration of said opposite conductivity type of said first region being higher adjacent the source region than adjacent the body portion, and (d) providing a conductive layer on an insulating layer at least at a surface-adjoining part of the first region extending between the source region and the body portion to form an insulated gate of the transistor, characterised in that, in the addition to the dopant introduction to form the source region, a dopant introduction step is effected to provide an additional dopant concentration of the one conductivity type in the part of the body which in the manufactured device is a part of the first region adjacent the source region and below the insulated gate, said additional dopant concentration being of the same order of magnitude as the higher dopant concentration of the first region adjacent the source region and thereby serving to reduce the threshold voltage of the transistor.
2. A method as claimed in Claim 1, further characterised in that the dopant introductions of said one conductivity type to provide the source region and additional dopant concentration are effected through at least part of a window in a masking pattern on the semiconductor body, through which window the dopant introduction of said opposite conductivity type is also effected.
3. A method as claimed in Claim 2, further characterised in that at least part of the masking pattern is retained in the manufactured device at least on the surface-adjoining part of the first region to provide at least part of the insulated gate.
4. A method as claimed in Claim 1 or Claim 2, further characterised in that, after providing the first region, the source region and said additional dopant concentration, a groove is etched into the body portion through part of the first region and source region, and in that the insulated gate is formed on a part of the first region at a side-wall of the groove.
5. A method as claimed in any one of the preceding claims, further characterised in that at least the dopant concentration of said opposite conductivity type and said additional dopant concentration of said one conductivity type are introduced into the body by dopant ion implantations diffused in the body by subsequent heating.
6. An insulated-gate field-effect transistor manufactured by a method claimed in any one of the preceding claims.
7. An insulated-gate field-effect transistor comprising a semiconductor body having a body portion of one conductivity type which is associated with a drain of the transistor, a source region of the one conductivity which is separated from the body portion of the one conductivity by a first region of the opposite conductivity type, the dopant concentration of said opposite conductivity type of said first region being higher adjacent the source region than adjacent the body portion, and a conductive layer on an insulating layer at least at a surface-adjoining part of the first region extending between the source region and the body portion to form an insulated gate of the transistor, characterised in that, in addition to the dopant concentration provided in the body to form the source region, an additional dopant concentration of the one conductivity type is present in the part of the first region adjacent the source region and below the insulated gate, said additional dopant concentration being of the same order of magnitude as said higher dopant concentration of the first region and thereby serving to reduce the threshold voltage of the transistor,
8. A method of manufacturing an insulated-gate field-effect transistor substantially as described with reference to Figures 1 and 2 or Figures 3 and 4 or Figure 5 of the accompanying drawings.
9. An insulated-gate field-effect transistor substantially as described with reference to Figures 1, 4 or 5 of the accompanying drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08331836A GB2150348A (en) | 1983-11-29 | 1983-11-29 | Insulated-gate field-effect transistors and their manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08331836A GB2150348A (en) | 1983-11-29 | 1983-11-29 | Insulated-gate field-effect transistors and their manufacture |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8331836D0 GB8331836D0 (en) | 1984-01-04 |
| GB2150348A true GB2150348A (en) | 1985-06-26 |
Family
ID=10552528
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08331836A Withdrawn GB2150348A (en) | 1983-11-29 | 1983-11-29 | Insulated-gate field-effect transistors and their manufacture |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2150348A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2214351A (en) * | 1988-01-18 | 1989-08-31 | Matsushita Electric Works Ltd | Dmosfet device |
| US5420046A (en) * | 1990-02-23 | 1995-05-30 | Matsushita Electric Works, Ltd. | Method for manufacturing optically triggered lateral thyristor |
| FR2742583A1 (en) * | 1995-12-18 | 1997-06-20 | Sgs Thomson Microelectronics | FIELD EFFECT TRANSISTOR WITH INSULATED GRID AND DIFFUSED CHANNEL |
| EP1005091A1 (en) * | 1998-11-17 | 2000-05-31 | STMicroelectronics S.r.l. | A method of manufacturing a vertical-channel MOSFET |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1173150A (en) * | 1966-12-13 | 1969-12-03 | Associated Semiconductor Mft | Improvements in Insulated Gate Field Effect Transistors |
| GB2027992A (en) * | 1978-08-08 | 1980-02-27 | Siemens Ag | Improvements in or relating to MOS field effect transistors for high voltage use |
-
1983
- 1983-11-29 GB GB08331836A patent/GB2150348A/en not_active Withdrawn
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1173150A (en) * | 1966-12-13 | 1969-12-03 | Associated Semiconductor Mft | Improvements in Insulated Gate Field Effect Transistors |
| GB2027992A (en) * | 1978-08-08 | 1980-02-27 | Siemens Ag | Improvements in or relating to MOS field effect transistors for high voltage use |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2214351A (en) * | 1988-01-18 | 1989-08-31 | Matsushita Electric Works Ltd | Dmosfet device |
| GB2214351B (en) * | 1988-01-18 | 1991-02-20 | Matsushita Electric Works Ltd | Method for manufacturing double-diffused metal oxide semiconductor field effect transistor device and the device thereby manufactured |
| US5420046A (en) * | 1990-02-23 | 1995-05-30 | Matsushita Electric Works, Ltd. | Method for manufacturing optically triggered lateral thyristor |
| FR2742583A1 (en) * | 1995-12-18 | 1997-06-20 | Sgs Thomson Microelectronics | FIELD EFFECT TRANSISTOR WITH INSULATED GRID AND DIFFUSED CHANNEL |
| EP0780908A1 (en) * | 1995-12-18 | 1997-06-25 | STMicroelectronics S.A. | A diffused channel insulated gate field effect transistor |
| US5801078A (en) * | 1995-12-18 | 1998-09-01 | Sgs-Thomson Microelectronics S.A. | Method for manufacturing diffused channel insulated gate effect transistor |
| EP1005091A1 (en) * | 1998-11-17 | 2000-05-31 | STMicroelectronics S.r.l. | A method of manufacturing a vertical-channel MOSFET |
| US6362025B1 (en) | 1998-11-17 | 2002-03-26 | Stmicroelectronics S.R.L | Method of manufacturing a vertical-channel MOSFET |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8331836D0 (en) | 1984-01-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |