JP3444478B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to MIS (Metal-Insu
The present invention relates to a lator-semiconductor (metal-insulator-semiconductor) type semiconductor device, in particular, a MIS transistor. In particular, the present invention relates to a thin film MIS type semiconductor device and a thin film transistor (TFT) formed on an insulating substrate, and has a so-called inverted stagger type structure in which a channel forming region is located above a gate electrode. The present invention relates to a MIS type semiconductor device. INDUSTRIAL APPLICABILITY The present invention is used in a semiconductor integrated circuit formed on an insulating substrate, for example, an active matrix type circuit used in a liquid crystal display device, a drive circuit of an image sensor, or the like.

[0002]

2. Description of the Related Art In recent years, an apparatus having a thin film MIS type semiconductor device formed on an insulating substrate is sometimes used. For example, it is an active matrix type liquid crystal display device or the like. Currently, the commercially available active matrix type circuit is T
There are a type using FT and a type using a diode such as MIM. In particular, the former has been vigorously manufactured in recent years because it can provide high-quality images.

An active matrix circuit using a TFT is a TF using a polycrystalline semiconductor such as polycrystalline silicon.
A TFT (amorphous silicon TFT) using T and an amorphous semiconductor such as amorphous silicon is known. The latter is difficult to manufacture for a large screen due to problems in the manufacturing process, and the latter, which can be manufactured at a process temperature of 350 ° C. or lower, is mainly used for large screens.

FIG. 2 shows a conventional amorphous silicon TF.
The manufacturing process of T (reverse stagger type) is shown. As the substrate 201, heat-resistant non-alkali glass such as Corning 7059 is used. Since the maximum temperature of the process of the amorphous silicon TFT is about 350 ° C., a material that can withstand this temperature is required. In particular, when it is used as a liquid crystal display panel, heat resistance and a high glass transition temperature that are not distorted by heat treatment are required. In the case of Corning 7059, this glass transition temperature is less than 600 ° C., which satisfies the condition.

In order to stabilize the operation of the TFT, it is not desirable that mobile ions such as sodium are contained in the substrate. Corning 7059 has no problem because the alkali concentration is sufficiently low. However, if the substrate contains a large amount of sodium or the like, silicon nitride and oxide are used to prevent mobile ions in the substrate from entering the TFT. It is necessary to form a passivation film of aluminum or the like.

First, a gate electrode 202 is formed by forming a film with a conductive material such as aluminum or tantalum and patterning with a mask. In particular, in order to prevent a short circuit between the gate electrode / wiring and the upper wiring, an oxide film 203 may be formed on the surface of the gate electrode. The anodic oxidation method is mainly used as a method for forming the oxide film. This is formed by oxidizing the surface of the gate electrode 202 by applying a positive voltage to the gate electrode 202 in an electrolytic solution to energize it.

After that, a gate insulating film 204 is formed. Although silicon nitride is generally used as the gate insulating film, silicon oxide may be used, or a silicide in which nitrogen and oxygen are mixed at an arbitrary ratio may be used. Further, it may be a single-layer film or a multi-layer film. When the silicon nitride film is used as the gate insulating film, the process temperature is about 350 ° C. when the plasma CVD method is used, which is the maximum temperature of this step. This state is shown in FIG.

Further, an amorphous silicon film is formed. When the plasma CVD method is used, the substrate temperature is required to be 250 to 300 ° C. The thickness of this film is preferably as thin as possible, and is usually 10 to 100 nm, preferably 10 to 30 nm. Then, the amorphous silicon region 205 is formed by patterning with a mask. This amorphous silicon region will later become a TFT channel formation region. The state thus far is shown in FIG.

Further, a silicon nitride film is formed on the entire surface and is patterned with a mask to form an etching stopper 206. This etching stopper is provided so as not to erroneously etch the amorphous silicon region 205 in the channel formation region in a later step. Because the amorphous silicon region 2 as described above
This is because 05 is as thin as 10 to 100 nm.
Further, since the amorphous silicon region below the etching stopper functions as a channel forming region, the etching stopper is designed to overlap the gate electrode as much as possible. However, since a slight misalignment occurs in normal mask alignment, patterning is performed so as to sufficiently overlap the gate electrode (that is, smaller than the gate electrode).

After that, an N-type or P-type conductivity type silicon film is formed. Normal amorphous silicon T
The FT is of N-channel type. Since this silicon film has too low conductivity in amorphous silicon,
A silicon film in a microcrystalline state is used. The N-type microcrystalline silicon film can be formed by a plasma CVD method at a temperature of 350 ° C. or lower. However, since the resistance is still not sufficiently low, it was necessary to set the thickness to 200 nm or more. Further, the P-type microcrystalline silicon film cannot be used because it has a remarkably large resistance, and therefore the P-channel TFT
It has been difficult to manufacture the with amorphous silicon.

The silicon film thus formed is patterned with a mask to form an N-type microcrystalline silicon region 20.
7 is formed. The state thus far is shown in FIG.
In the state of FIG. 2C, since the (N-type) microcrystalline silicon film is bonded on the etching stopper, TF
T does not work. Therefore, it is necessary to divide this. Then, this is divided by using a mask, and the groove 20
8 is formed. If there is no etching stopper, the underlying amorphous silicon region 205 may be accidentally etched. . This is because the thickness of the microcrystalline silicon region 207 is several times to ten times or more than that of the amorphous silicon region below it, or more.

After that, the wiring 209 is formed by a known method.
The pixel electrode 210 is formed using a mask. This state is shown in FIG. In the above method, since the number of masks is as large as seven, there is a concern that the yield will decrease. Therefore, a method of reducing the number of masks has been proposed as shown below. First, the gate electrode portion is patterned on the substrate using the first mask. After that, a gate insulating film is formed, and further, an amorphous silicon film and a silicon nitride film (which later become an etching stopper) are continuously formed. Then, expose from the back side,
Only the silicon nitride film is etched in a self-aligning manner using the gate electrode portion as a mask to form an etching stopper.
Then, a microcrystalline silicon film is formed thereover, and a second mask is used to form a TFT region including a groove above the channel (corresponding to 208 in FIG. 2). After that, wirings and electrodes are formed using the third and fourth masks. Finally, a product equivalent to that shown in FIG. 2D is obtained.
By making full use of the self-aligning process, the number of masks can be reduced by three.

[0013]

As can be seen from the figure, the TFT formed in this way has extremely severe irregularities. This is mainly due to the gate electrode portion (including the oxide 203 of the gate electrode), the etching stopper and the microcrystalline silicon region. The thickness of the gate electrode portion is 300 nm, the thickness of the etching stopper is 200 nm, The thickness of the microcrystalline silicon region 206 is 30
If the thickness is 0 nm, asperities of 800 nm will occur on the substrate.

For example, when used as an active matrix circuit of a liquid crystal display panel, the cell thickness is 5 to 5.
It has a thickness of 6 μm and is controlled with an accuracy of 0.1 μm or less. Under such a condition, if there is an unevenness of 1 μm, a remarkable defect will be given to the uniformity of the cell thickness.

However, none of these factors, which are mentioned as the cause of the unevenness of the TFT, can be easily reduced. For example, if the microcrystalline silicon film is made thin, the resistance of the source and drain increases and the characteristics deteriorate. Further, if the etching stopper is thin, the amorphous silicon region below may be erroneously etched while the microcrystalline silicon region is being etched, which lowers the yield.

The present invention has been made in view of such conventional problems, and one of the objects of the present invention is to simplify the process. For example, the yield is improved by reducing the number of masks as compared with the conventional method. Alternatively, it is intended to improve throughput and reduce cost by reducing film formation steps.

Another object of the invention is to make the TFTs flatter. This not only solves the problem of using it for a liquid crystal display panel, but also planarization is an important technical issue in other applications, and it is difficult to apply it to conventional TFTs. It can be applied.

It is also an object of the present invention to improve TFT characteristics. In the TFT shown in FIG. 2, the sheet resistance of the source / drain is high, which adversely affects various characteristics of the TFT.
Moreover, since the source / drain and the channel formation region are formed by different films, the state of the junction between them is extremely poor. Moreover, it is impossible to continuously form the source / drain after forming the channel formation region. Ideally, in order to improve the characteristics, it is necessary to form the source / drain and the channel forming region by the same film in the same plane and improve the junction between these regions like the MOS transistor of the semiconductor integrated circuit. .

[0019]

In order to solve the above-mentioned problems, the present invention proposes a completely new TFT manufacturing method which does not use an etching stopper and a TFT manufactured by the method. That is, the resistance of the microcrystalline silicon region (source / drain) is sufficiently reduced and the thickness thereof is reduced. Furthermore, according to the present invention, a two-step process such as the formation of an amorphous silicon region (film) that becomes a channel formation region and the formation of a microcrystalline silicon region (film) that becomes a source / drain region as in the prior art is performed. Instead, one silicon film is formed, and one portion is formed as a source / drain region and the other portion is formed as a channel formation region.

In order to improve the throughput, reducing the number of film forming steps is the most important issue. Not only does the film formation process take time to form a film, but it also takes about the same time to clean the inside of the chamber.In modern semiconductor processes that require an extremely clean environment, the cleaning process is not performed between chambers. The reality is that the film is done. Therefore, forming a thin film rather than forming a thick film, and forming a single-layer film rather than forming a multi-layer film are necessary for increasing throughput. In that sense, it is desirable to reduce the film forming process.

A TFT based on one technical idea of the present invention
Has the following configuration. First, the inverted stagger type T
It is FT. A gate insulating film is formed so as to cover the gate electrode, and a semiconductor film is further formed. The portion above the gate electrode is substantially intrinsic so as to function as a channel formation region. The other portion is N-type or P-type and functions as a source / drain. Also,
The portion functioning as the channel formation region can be in an amorphous state, a semi-amorphous state, a microcrystalline state, a polycrystalline state, or an intermediate state thereof. Amorphous is desirable for suppressing the off current. On the other hand, the region functioning as the source / drain is crystalline silicon having a sufficiently small resistance. In addition, in the present invention, this region is irradiated with visible light or near-infrared light, that is, strong light having a wavelength of 4 to 0.5 μm for a short time, so that the semiconductor is provided with order and crystallinity. Is characterized by.

With such a structure, the semiconductor film can be formed in one step.
Only layers are required, and mass productivity is improved. Furthermore, since the thick microcrystalline silicon unlike the conventional case is not formed, the unevenness of the TFT can be reduced. Of course, according to the present invention, the channel forming region and the impurity regions such as the source / drain are not necessary.
It is needless to say that not only the formation of the semiconductor film of layers is required, but also a multilayer structure may be used in order to further improve the characteristics of the element in consideration of cost and characteristics. However, also in that case, it is necessary that the source / drain and the channel formation region are substantially in the same plane (inside the layer).

Further, another T based on the technical idea of the present invention.
The FT is characterized by not having an etching stopper on the channel formation region. The presence of the etching stopper is an important factor for the unevenness of the TFT.

The fabrication of the TFT of the present invention is carried out by the method shown in FIG. 1, but it goes without saying that necessary modifications can be made to this process chart. As shown in the figure, heat-resistant non-alkali glass (for example Corning 705
9) The gate electrode 102 is patterned on the substrate 101 by a mask. If necessary, as shown in FIG. 1, an oxide film 103 may be formed on the surface of the gate electrode to enhance the insulating property. Further, a gate insulating film 104 is formed. Thus, FIG. 1A is obtained.

Next, amorphous, semi-amorphous,
A thin film of microcrystal, polycrystal, or a silicon thin film in an intermediate state thereof is formed and patterned by a mask to form the semiconductor region 105. In practice, an amorphous silicon film is often formed in consideration of the film forming temperature and the off-current (leakage current), but a low temperature crystallization technique such as laser annealing may be used to form polycrystalline or semi-amorphous silicon. Good. However, when polycrystalline silicon or semi-amorphous silicon is used, the electric field mobility increases, but the off-current also increases, which is not suitable for an active matrix circuit of a liquid crystal display panel.

Next, a film that serves as a mask material for visible / near infrared light, for example, a silicon nitride film containing a large amount of silicon (preferably having a thickness of 50 nm or more) is formed, and this is patterned with a mask. At this time, the photoresist may be left on the silicon nitride film. That is, FIG.
In (C), 106 is a silicon nitride film and 107 is a photoresist. The thickness of the photoresist is 100 nm or more, preferably 500 nm or more, in consideration of the subsequent ion implantation step.

In this state, first, impurities are selectively implanted into the semiconductor region 105 by a method such as ion implantation, ion doping, or doping of plasmatized ions. Thus, the impurity region 108 is formed. However, this impurity implantation causes a very large defect in the semiconductor film, and the semiconductor film no longer functions as a semiconductor. Therefore, crystallization (lamp annealing, rapid thermal annealing (RTA)) is performed by irradiating visible or near infrared light from above for a short time.
By this step, the order of the semiconductor is restored, and a state with better order than the state before the introduction of impurities is obtained. In this lamp annealing process, by appropriately controlling the irradiation time of the light used, the temperature of the object to be irradiated, and the atmosphere, silicon in various states from a polycrystalline state that is extremely close to a single crystal state to a semi-amorphous state is formed. You can The crystallinity of the silicon thus obtained by the lamp annealing step can be confirmed by examining the scattering peaks peculiar to crystalline silicon by Raman scattering spectroscopy.

More specifically, 10 to 10 light from near infrared light to visible light, preferably light having a wavelength of 4 μm to 0.5 μm (for example, infrared light having a peak at a wavelength of 1.3 μm) is used.
The crystallinity is promoted by heating the silicon film by irradiating it for a relatively short time of about 00 seconds.
The wavelength of the light used is preferably absorbed by the silicon film and not substantially absorbed by the glass substrate.

Intrinsic or substantially intrinsic amorphous silicon is well absorbed by visible light, especially light having a short wavelength of less than 0.5 μm, and light having a longer wavelength has a lower absorptivity. On the other hand, light having a wavelength of 0.5 to 4 μm is effectively absorbed by the amorphous silicon film doped with impurities, but hardly absorbed by the glass substrate. As a result, 0.5 ~
If the light of 4 μm is used, it is possible to effectively heat only the impurity-doped region of the TFT. Further, in the lamp annealing, it goes without saying that the light may be emitted from only one of the upper side and the substrate side or may be emitted from both sides.

Further, in such heat treatment, the silicon film is often peeled off due to a difference in coefficient of thermal expansion between the silicon film and the substrate, a difference in temperature between the surface of the silicon film and the substrate / silicon film interface, and the like. is there. In particular, this is remarkable when the area of the film is large so as to cover the entire surface of the substrate. However, in the present invention, since the film is divided into a sufficiently small area, peeling of the film can be prevented. Further, since the entire surface of the substrate is not heated through the silicon film, thermal contraction of the substrate can be suppressed to the minimum. Further, in order to suppress the thermal influence on the substrate and the like as much as possible, it is preferable to shorten the lamp annealing time as much as possible.

The gate electrode should be made of a material that can withstand this lamp annealing process, and a metal having a high melting point such as tantalum or titanium is preferable. Further, aluminum is easily deformed at a high temperature, but when it is covered with an anodized film having a sufficient thickness, it can withstand a short annealing time.

According to the knowledge of the present inventor, in the lamp annealing step, if the sample is heated to about 250 to 500 ° C., the activation of impurities progresses to the inside of the sample, and the impurity concentration can be made sufficiently high. did it. In order to keep the channel formation region of amorphous silicon, it is not desirable to place the sample in a too high temperature state, and since the glass substrate is also restricted, it is desirable to limit the heating to about 250 to 350 ° C.

After performing the doping as described above, the silicon nitride film 106 and the photoresist 107 are removed. The silicon nitride film 106 may be left as it is. Then, the wiring 110 and the ITO are formed by a known method.
The pixel electrode 111 of is formed by a mask and. Although a total of five masks are required by the above steps, the number of masks can be reduced to four by making full use of the self-alignment method using the back surface exposure technique of the gate electrode as in the conventional case. That is, one is required to form the gate electrode, one is required to form the semiconductor region, and two are required to form the pixel electrode and the wiring. The patterning of the silicon nitride mask 106 may be performed by backside exposure using the gate electrode as a mask.

As is apparent from FIG. 1D, the TFT according to the present invention has smaller irregularities than the conventional TFT. This is because the main cause of the unevenness is only the unevenness of the gate electrode portion. Since the thickness of the semiconductor region 105 is extremely thin and is 10 to 100 nm like the conventional TFT, it does not significantly contribute to the unevenness.

As described above, the semiconductor region, that is, the source /
The drain may be thin because the impurity concentration in the region is sufficiently high and its crystallinity is good, and the feature of the present invention is brought about by adopting the lamp annealing process. Further, in the present invention, the etching stopper does not exist as in the conventional case, and the mask material used in the present invention is not required to remain after the completion of the TFT, so that the unevenness of the TFT is significantly reduced.

Further, unlike the conventional TFT, the channel forming region and the source / drain are not made of different films, but are made of the same film, so that the junction between these regions is good. Thus, the TFT characteristics (electric field mobility, subthreshold characteristic value, leak current) are improved.

[0037]

DETAILED DESCRIPTION OF THE INVENTION

[0038]

EXAMPLES Example 1 This example was formed according to the manufacturing process shown in FIG. The manufacturing process sectional view corresponds to FIG. 1. However, the steps up to forming the metal wiring / electrode 110 in FIG. 1 do not include the step of forming the ITO pixel electrode 111. The gate electrode was tantalum, and in step 5, an anodic oxide film having a thickness of about 200 nm was formed on the surface of the gate electrode to improve the insulating property. An ion doping method was used as the impurity doping means. The number of masks used in this step is four. The total process consists of 26 processes.

3 to 6, "sputter" is a sputtering film forming method, "PCVD" is a plasma CVD method,
"RIE" means reactive ion etching. Also, after these techniques, the following is written:
The film thickness, the gas used, etc.

The sectional view of the conventional manufacturing process corresponding to this embodiment is shown in FIG. 2 and the process drawing thereof is shown in FIG. 5. Here, the number of masks used is 6, and the total number of processes is 29. Consists of steps. As described above, in this embodiment, the manufacturing process can be shortened as compared with the conventional method.

The present embodiment will be described in detail below with reference to process drawings. Corning 7059 glass (101 in FIG. 1) was used as the substrate. This is washed (step 1), and a tantalum film having a thickness of 200 n is formed thereon by a sputtering method.
m (step 2). Then, this is patterned with a mask (step 3), and mixed acid (phosphoric acid containing 5% nitric acid)
Etching was performed (step 4). After that, the tantalum gate electrode (102 in FIG. 1) is energized to perform anodic oxidation,
The voltage was increased to 120 V at maximum and an anodic oxide film (103 in FIG. 1) was formed to a thickness of 200 nm (step 5). The method of anodic oxidation is described in Japanese Patent Application No. 3-237100 or 3-238713 and will not be described in detail here.

After that, the resist was removed (step 6), and a 200 nm-thick silicon nitride film (104 in FIG. 1) as a gate insulating film was formed by plasma CVD (step 7). The substrate temperature at this time was 300 ° C. And
After cleaning the substrate (step 8), an amorphous silicon film having a thickness of 30 nm was formed by the plasma CVD method (step 9). The substrate temperature at this time was 300 ° C.

Then, the semiconductor region is patterned with a mask (step 10), and the amorphous silicon film is etched by the reactive ion etching method using CF ₄ as a reaction gas (step 11) to form the semiconductor region (FIG. 1). 105) was formed. The remaining resist was removed (step 12) and the substrate was washed (step 13).

After that, a 200-nm-thick silicon nitride film was formed by the plasma CVD method (step 14). The substrate temperature at this time was 300 ° C. Then, the silicon nitride mask was patterned with the mask (step 15), and the silicon nitride film was etched with buffer hydrofluoric acid (step 16) to form a silicon nitride mask (106 in FIG. 1). A resist (107 in FIG. 1) having a thickness of about 500 nm remained on the silicon nitride mask.

Then, by the ion doping method, 3
Phosphorus ions with a dose of × 10 ¹⁵ cm ^-2 were implanted with an acceleration energy of 10 keV (step 17) to form an impurity region (108 in FIG. 1). Then, the substrate was washed (step 18) and the remaining resist was removed (step 1).
9).

After that, lamp annealing was performed with a halogen tungsten lamp (step 20), and the silicon nitride mask (106 in FIG. 1) was removed by etching with buffer hydrofluoric acid (step 21). Lamp annealing (Process 2
In 0), the intensity of visible / near infrared light is 800 to 1300 when the temperature on the monitor single crystal silicon wafer is 800 to 1300.
C., typically between 900 and 1200.degree. Specifically, the temperature of the thermocouple embedded in the silicon wafer was monitored and fed back to the infrared light source. In this embodiment, the temperature rising / falling temperature is as shown in FIG.
It carried out like (A) or (B). The temperature rise is constant, the speed is 50 to 200 ° C / sec, and the temperature fall is 20 by natural cooling.
Was ~ 100 ° C.

FIG. 7A shows a general temperature cycle, which is composed of three processes of a temperature raising time a, a holding time b, and a temperature lowering time c. However, in this case, since the sample is rapidly heated and cooled from room temperature to a temperature as high as 1000 ° C., and further from a high temperature state to room temperature, it has a great influence on the silicon film and the substrate, and the silicon film may be peeled off. high.

In order to solve this problem, FIG.
As described above, a preheat time d and a postheat time f are provided before reaching the holding time, and 200 to before the holding time is reached.
It is desirable to keep at a temperature of 500 ° C. that does not significantly affect the substrate and film. Also, this lamp annealing was performed in an H ₂ atmosphere. 0.1 to 1 in H ₂ atmosphere
0% HCl, other hydrogen halide, fluorine and chlorine,
A compound of bromine may be mixed. Then, the substrate was washed (step 22).

Next, an aluminum film is formed to a thickness of 400 nm by the sputtering method (step 23), and the aluminum wiring is patterned by a mask (step 2).
4) Then, the aluminum film is further etched with mixed acid (step 25), and the aluminum wiring (11 in FIG. 1) is etched.
0) was formed. The remaining resist was removed (step 2
6). Finally, annealing was performed at 350 ° C. for 30 minutes in a hydrogen atmosphere of 1 atm. Particularly, in the present invention, the dangling bonds generated in the step of lamp annealing with visible light / near infrared light are subjected to 250 to 4 in the hydrogen atmosphere in the subsequent step.
It is important to neutralize by heating at 00 ° C. Through the above steps, the N-channel TFT was completed.

Example 2 This example was formed according to the manufacturing process shown in FIG. A cross-sectional view of the manufacturing process corresponds to FIG. 1 except that a backside exposure technique is used. However, as shown in FIG. 4, like the first embodiment, the steps up to the step of forming the metal wiring / electrode 110 of FIG. 1 are performed. The gate electrode was tantalum, and in step 5, an anodic oxide film having a thickness of about 200 nm was formed on the surface of the gate electrode to improve the insulating property. A backside exposure technique was used to form the silicon nitride mask. An ion doping method was used as the impurity doping means. The number of masks used in this step is reduced by one by the backside exposure technique to three. The total process consists of 26 processes.

A conventional manufacturing process corresponding to this embodiment is shown in FIG.
, The number of masks used is 3 here.
It is a sheet, and the whole process consists of 23 processes. In this embodiment (FIG. 4), the total number of steps is increased, but the number of film forming steps that limits the throughput is 5, which is 6 of the conventional method (FIG. 6).
Fewer than the process, the productivity is actually improved.

The present embodiment will be described in detail below with reference to process drawings. Corning 7059 glass (101 in FIG. 1) was used as the substrate. This is washed (step 1), and a tantalum film having a thickness of 400 n is formed thereon by a sputtering method.
m (step 2). Then, this is patterned with a mask (step 3), and mixed acid (phosphoric acid containing 5% nitric acid)
Etching was performed (step 4). After that, the tantalum gate electrode (102 in FIG. 1) is energized to perform anodic oxidation,
The voltage was increased to 120 V at maximum and an anodic oxide film (103 in FIG. 1) was formed to a thickness of 200 nm (step 5).

After that, the resist was removed (step 6), and a silicon nitride film (104 in FIG. 1) as a gate insulating film was formed to a thickness of 200 nm by the plasma CVD method (step 7). The substrate temperature at this time was 300 ° C. And
After cleaning the substrate (step 8), an amorphous silicon film having a thickness of 30 nm was formed by the plasma CVD method (step 9). The substrate temperature at this time was 300 ° C.

Then, the semiconductor region is patterned with a mask (step 10), and the amorphous silicon film is etched by the reactive ion etching method using CF ₄ as a reaction gas (step 11) to form the semiconductor region (FIG. 1). 105) was formed. The remaining resist was removed (step 12) and the substrate was washed (step 13).

After that, a 200-nm-thick silicon nitride film was formed by the plasma CVD method (step 14). The substrate temperature at this time was 300 ° C. Then, the resist is applied and exposed from the back surface of the substrate, the silicon nitride mask is patterned in a self-aligned manner using the gate electrode as a mask (step 15), and the silicon nitride film is etched with buffer hydrofluoric acid (step 16). ), And a silicon nitride mask (106 in FIG. 1) was formed. A resist (107 in FIG. 1) having a thickness of about 500 nm remained on the silicon nitride mask.

Then, by the ion doping method, 2
Phosphorus ions with a dose of × 10 ¹⁵ cm ^-2 were implanted with an acceleration energy of 10 keV (step 17) to form an impurity region (108 in FIG. 1). Then, the substrate was washed (step 18) and the remaining resist was removed (step 1).
9).

After that, lamp annealing was performed with a halogen tungsten lamp (step 20), and the silicon nitride mask (106 in FIG. 1) was removed by etching with buffer hydrofluoric acid (step 21). The conditions for lamp annealing were the same as in Example 1. Then, the substrate was washed (Step 2
2).

Then, an aluminum film is formed to a thickness of 400 nm by the sputtering method (step 23), and the aluminum wiring is patterned by a mask (step 2).
4) Then, the aluminum film is further etched with mixed acid (step 25), and the aluminum wiring (11 in FIG. 1) is etched.
0) was formed. The remaining resist was removed (step 2
6). Finally, annealing was performed at 350 ° C. for 30 minutes in a hydrogen atmosphere of 1 atm. An N-channel TFT was manufactured through the above steps.

[0059]

As is apparent from the above description, the effect of the present invention is characterized by the simplification of the process. As well,
The sheet resistance of the source and drain regions is small, so that it is possible to provide a TFT of good quality (for example, excellent in high speed and small in threshold voltage). As described above, the present invention is industrially useful.

[Brief description of drawings]

FIG. 1 shows a cross-sectional view of a method for manufacturing a TFT according to the present invention.

FIG. 2 shows a cross-sectional view of a conventional TFT manufacturing method.

3A to 3C show a manufacturing process diagram of the TFT of Example 1. FIG.

4A to 4C show a manufacturing process diagram of a TFT of Example 2. FIG.

5A to 5C are views showing a process of manufacturing a TFT by a conventional method.

FIG. 6 is a diagram showing a process of manufacturing a TFT by a conventional method.

FIG. 7 shows an example of temperature setting according to the first embodiment.

[Explanation of symbols]

101 substrate 102 gate electrode 103 Surface oxide of gate electrode 104 Gate insulation film 105 Semiconductor region 106 silicon nitride mask 107 photoresist mask 108 impurity region 109 channel formation region 110 metal wiring 111 Pixel electrode (ITO)

   ─────────────────────────────────────────────────── ─── Continued front page       (56) Reference JP-A-4-269837 (JP, A)                 JP-A-56-100412 (JP, A)                 Japanese Patent Laid-Open No. 59-221221 (JP, A)                 JP 61-198625 (JP, A)                 JP-A-60-245173 (JP, A)                 JP-A-62-205664 (JP, A)                 JP 58-168278 (JP, A)

Claims (7)

(57) [Claims] 1. A method of manufacturing an insulating gate type semiconductor device, comprising: forming a gate electrode on a substrate; forming a gate insulating film on the gate electrode; A polycrystalline semiconductor film is formed , a mask is formed on the semiconductor film , an impurity is injected into a region of the semiconductor film which is not covered with the mask to form a source region and a drain region, and the mask is left. As it is, the temperature of the semiconductor film is raised to the first temperature by the lamp annealing, and the semiconductor film is maintained at the first temperature, and then the semiconductor film is further heated from the first temperature to the first temperature by the lamp annealing. Crystallizing the source region and the drain region by raising the temperature to a second temperature higher than the temperature and maintaining the semiconductor film at the second temperature. Method of manufacturing insulated gate type semiconductor device according to claim. 2. A method of manufacturing an insulating gate type semiconductor device, wherein a gate electrode is formed on a substrate, a gate insulating film is formed on the gate electrode, and an amorphous film of 10 to 100 nm is formed on the gate insulating film.
Alternatively, a polycrystalline semiconductor film is formed, a mask is formed over the semiconductor film, impurities are injected into a selected region of the semiconductor film which is not covered with the mask, and lamp annealing is performed with the mask left. Temperature of the semiconductor film is raised to a first temperature by maintaining the semiconductor film at the first temperature by means of lamp annealing and then the semiconductor film is heated from the first temperature to a temperature higher than the first temperature. 2. A method for manufacturing an insulating gate type semiconductor device, comprising: crystallizing the selected region of the semiconductor film by raising the temperature to 2 and maintaining the semiconductor film at the second temperature. 3. A method of manufacturing an insulating gate type semiconductor device, comprising forming a gate electrode on a substrate, forming a gate insulating film on the gate electrode, and forming an amorphous film of 10 to 100 nm on the gate insulating film.
Alternatively, a polycrystalline semiconductor film is formed, a mask made of a photoresist and a silicon compound film is formed on the semiconductor film, and an impurity is injected into a selected region of the semiconductor film using the mask. After that, the photoresist is removed, the semiconductor film is raised to a first temperature by lamp annealing while the silicon compound film is left, and the semiconductor film is maintained at the first temperature. To raise the semiconductor film from the first temperature to a second temperature higher than the first temperature and maintain the semiconductor film at the second temperature, thereby selecting the selected region of the semiconductor film. was crystallized, the lamp after annealing, producing side of the selected forming an electrode in contact with the region wherein the insulated gate semiconductor device of the semiconductor film . 4. A method of manufacturing an insulating gate type semiconductor device, comprising forming a gate electrode on a substrate, forming a gate insulating film on the gate electrode, and forming an amorphous film of 10 to 100 nm on the gate insulating film.
Or a polycrystalline semiconductor film is formed, a mask is formed over the semiconductor film by the exposure from the rear surface of the substrate, impurities are implanted into selected regions above not covered by the mask of the semiconductor film, wherein The semiconductor film is heated to a first temperature by lamp annealing while the mask is left, and the semiconductor film is maintained at the first temperature, and then the semiconductor film is heated from the first temperature by lamp annealing. An insulating gate characterized by crystallizing the selected region of the semiconductor film by raising the temperature to a second temperature higher than the first temperature and maintaining the semiconductor film at the second temperature. Method for manufacturing a semiconductor device of the semiconductor type. 5. The lamp anneal has a wavelength of 0.5 to 4
method of manufacturing insulated gate type semiconductor device according to any one of claims 1 a <br/> stone 4, characterized in that it is carried out with light having a [mu] m. Wherein said impurities, the production of insulated gate semiconductor device according to any one of claims 1 <br/> to 5, characterized in that it is injected into the semiconductor film by an ion doping method Method. 7. A method of manufacturing insulated gate type semiconductor device according to any one of claims 1 to 6 wherein the first temperature is characterized in that it is a 200 to 500 ° C..