KR0145225B1 - 블럭 단위로 스트레스 가능한 회로 - Google Patents

블럭 단위로 스트레스 가능한 회로

Info

Publication number
KR0145225B1
KR0145225B1 KR1019950010167A KR19950010167A KR0145225B1 KR 0145225 B1 KR0145225 B1 KR 0145225B1 KR 1019950010167 A KR1019950010167 A KR 1019950010167A KR 19950010167 A KR19950010167 A KR 19950010167A KR 0145225 B1 KR0145225 B1 KR 0145225B1
Authority
KR
South Korea
Prior art keywords
voltage
block
stress
signal
stress voltage
Prior art date
Application number
KR1019950010167A
Other languages
English (en)
Korean (ko)
Other versions
KR960039014A (ko
Inventor
고용남
최영준
Original Assignee
김광호
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자주식회사 filed Critical 김광호
Priority to KR1019950010167A priority Critical patent/KR0145225B1/ko
Priority to US08/634,643 priority patent/US5654925A/en
Priority to DE19615660A priority patent/DE19615660A1/de
Priority to JP8107272A priority patent/JP2755936B2/ja
Publication of KR960039014A publication Critical patent/KR960039014A/ko
Application granted granted Critical
Publication of KR0145225B1 publication Critical patent/KR0145225B1/ko

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

Landscapes

  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
KR1019950010167A 1995-04-27 1995-04-27 블럭 단위로 스트레스 가능한 회로 KR0145225B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019950010167A KR0145225B1 (ko) 1995-04-27 1995-04-27 블럭 단위로 스트레스 가능한 회로
US08/634,643 US5654925A (en) 1995-04-27 1996-04-18 Circuit for applying a stress voltage in sequence to selected memory blocks in a semiconductor device
DE19615660A DE19615660A1 (de) 1995-04-27 1996-04-19 Schaltung zur Aufbringung einer Belastungsspannung in eine Blockeinheit für die Verwendung in einer Halbleiterspeichervorrichtung
JP8107272A JP2755936B2 (ja) 1995-04-27 1996-04-26 ブロック単位でストレス印加可能なストレス電圧印加回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950010167A KR0145225B1 (ko) 1995-04-27 1995-04-27 블럭 단위로 스트레스 가능한 회로

Publications (2)

Publication Number Publication Date
KR960039014A KR960039014A (ko) 1996-11-21
KR0145225B1 true KR0145225B1 (ko) 1998-08-17

Family

ID=19413137

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950010167A KR0145225B1 (ko) 1995-04-27 1995-04-27 블럭 단위로 스트레스 가능한 회로

Country Status (4)

Country Link
US (1) US5654925A (ja)
JP (1) JP2755936B2 (ja)
KR (1) KR0145225B1 (ja)
DE (1) DE19615660A1 (ja)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6005409A (en) * 1996-06-04 1999-12-21 Advanced Micro Devices, Inc. Detection of process-induced damage on transistors in real time
KR19980034731A (ko) * 1996-11-08 1998-08-05 김영환 반도체 메모리 소자의 스트레스 테스트 장치 및 그 방법
JPH10269800A (ja) 1997-03-27 1998-10-09 Mitsubishi Electric Corp 半導体記憶装置
JP2964982B2 (ja) * 1997-04-01 1999-10-18 日本電気株式会社 不揮発性半導体記憶装置
JPH1166874A (ja) * 1997-08-08 1999-03-09 Mitsubishi Electric Corp 不揮発性半導体記憶装置
KR100268434B1 (ko) * 1997-12-29 2000-10-16 윤종용 반도체 메모리 장치 및 그것의 번-인 테스트방법
KR100269322B1 (ko) * 1998-01-16 2000-10-16 윤종용 스트레스용전압을이용하여메모리를테스팅하는기능을갖는집적회로및그의메모리테스트방법
US6606267B2 (en) * 1998-06-23 2003-08-12 Sandisk Corporation High data rate write process for non-volatile flash memories
US6122760A (en) * 1998-08-25 2000-09-19 International Business Machines Corporation Burn in technique for chips containing different types of IC circuitry
US6081455A (en) * 1999-01-14 2000-06-27 Advanced Micro Devices, Inc. EEPROM decoder block having a p-well coupled to a charge pump for charging the p-well and method of programming with the EEPROM decoder block
JP3859912B2 (ja) 1999-09-08 2006-12-20 株式会社東芝 不揮発性半導体記憶装置
US6622230B1 (en) * 2000-11-28 2003-09-16 Advanced Micro Devices, Inc. Multi-set block erase
US6392941B1 (en) * 2000-12-29 2002-05-21 Cypress Semiconductor Corp. Wordline and pseudo read stress test for SRAM
US6574158B1 (en) * 2001-09-27 2003-06-03 Cypress Semiconductor Corp. Method and system for measuring threshold of EPROM cells
KR100515055B1 (ko) * 2002-12-12 2005-09-14 삼성전자주식회사 모든 칼럼 선택 트랜지스터들을 선택할 수 있는 칼럼 프리디코더를 갖는 플레쉬 메모리 장치와 그 스트레스 테스트방법
JP4203372B2 (ja) * 2003-08-26 2008-12-24 富士雄 舛岡 不揮発性半導体記憶装置及びそれを備えてなる液晶表示装置
JP4805733B2 (ja) * 2006-06-21 2011-11-02 株式会社東芝 半導体記憶装置及びそのテスト方法
KR100816162B1 (ko) * 2007-01-23 2008-03-21 주식회사 하이닉스반도체 낸드 플래시 메모리 장치 및 셀 특성 개선 방법
KR100904962B1 (ko) * 2007-05-31 2009-06-26 삼성전자주식회사 스트레스 검출 회로, 이를 포함하는 반도체 칩 및 스트레스검출 방법
US7679978B1 (en) * 2007-07-11 2010-03-16 Sun Microsystems, Inc. Scheme for screening weak memory cell
RU2748727C2 (ru) * 2017-01-31 2021-05-31 Хьюлетт-Паккард Дивелопмент Компани, Л.П. Доступ к блокам памяти в банке памяти
KR20220050665A (ko) * 2020-10-16 2022-04-25 삼성전자주식회사 패스 트랜지스터 회로를 포함하는 메모리 장치

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5075890A (en) * 1989-05-02 1991-12-24 Kabushiki Kaisha Toshiba Electrically erasable programmable read-only memory with nand cell
KR960002006B1 (ko) * 1991-03-12 1996-02-09 가부시끼가이샤 도시바 2개의 기준 레벨을 사용하는 기록 검증 제어기를 갖는 전기적으로 소거 가능하고 프로그램 가능한 불휘발성 메모리 장치
KR960001859B1 (ko) * 1993-04-16 1996-02-06 삼성전자주식회사 반도체 메모리장치의 디코딩회로 및 그 방법
JP2725570B2 (ja) * 1993-11-02 1998-03-11 日本電気株式会社 半導体メモリ装置

Also Published As

Publication number Publication date
JP2755936B2 (ja) 1998-05-25
JPH08306200A (ja) 1996-11-22
US5654925A (en) 1997-08-05
DE19615660A1 (de) 1996-11-14
KR960039014A (ko) 1996-11-21

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