KR0120606B1 - 반도체 기억소자의 자동모드 선택 회로 - Google Patents

반도체 기억소자의 자동모드 선택 회로

Info

Publication number
KR0120606B1
KR0120606B1 KR1019940040567A KR19940040567A KR0120606B1 KR 0120606 B1 KR0120606 B1 KR 0120606B1 KR 1019940040567 A KR1019940040567 A KR 1019940040567A KR 19940040567 A KR19940040567 A KR 19940040567A KR 0120606 B1 KR0120606 B1 KR 0120606B1
Authority
KR
South Korea
Prior art keywords
node
vref
reference voltage
potential
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019940040567A
Other languages
English (en)
Korean (ko)
Other versions
KR960027303A (ko
Inventor
김정필
Original Assignee
김주용
현대전자산업주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업주식회사 filed Critical 김주용
Priority to KR1019940040567A priority Critical patent/KR0120606B1/ko
Priority to JP7355049A priority patent/JP2771962B2/ja
Priority to TW084114206A priority patent/TW291626B/zh
Priority to GB9526695A priority patent/GB2296592B/en
Priority to CN96102021A priority patent/CN1121691C/zh
Publication of KR960027303A publication Critical patent/KR960027303A/ko
Priority to US08/893,542 priority patent/US5818783A/en
Application granted granted Critical
Publication of KR0120606B1 publication Critical patent/KR0120606B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)
KR1019940040567A 1994-12-31 1994-12-31 반도체 기억소자의 자동모드 선택 회로 Expired - Fee Related KR0120606B1 (ko)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019940040567A KR0120606B1 (ko) 1994-12-31 1994-12-31 반도체 기억소자의 자동모드 선택 회로
JP7355049A JP2771962B2 (ja) 1994-12-31 1995-12-28 半導体記憶素子の自動モード選択回路
TW084114206A TW291626B (enExample) 1994-12-31 1995-12-29
GB9526695A GB2296592B (en) 1994-12-31 1995-12-29 Automatic mode selection circuit for a semiconductor memory device
CN96102021A CN1121691C (zh) 1994-12-31 1996-01-02 用于半导体存储器件的自动模式选择电路
US08/893,542 US5818783A (en) 1994-12-31 1997-07-11 Automatic mode selection circuit for semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940040567A KR0120606B1 (ko) 1994-12-31 1994-12-31 반도체 기억소자의 자동모드 선택 회로

Publications (2)

Publication Number Publication Date
KR960027303A KR960027303A (ko) 1996-07-22
KR0120606B1 true KR0120606B1 (ko) 1997-10-30

Family

ID=19406204

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940040567A Expired - Fee Related KR0120606B1 (ko) 1994-12-31 1994-12-31 반도체 기억소자의 자동모드 선택 회로

Country Status (6)

Country Link
US (1) US5818783A (enExample)
JP (1) JP2771962B2 (enExample)
KR (1) KR0120606B1 (enExample)
CN (1) CN1121691C (enExample)
GB (1) GB2296592B (enExample)
TW (1) TW291626B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100429919B1 (ko) * 2000-06-05 2004-05-04 닛뽕덴끼 가부시끼가이샤 반도체 장치 및 그 테스트 방법

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100203140B1 (ko) * 1996-06-29 1999-06-15 김영환 입력 누설 전류가 없는 자동 모드 선택 장치
KR100278648B1 (ko) * 1997-04-30 2001-01-15 윤종용 반도체장치및방법
JP3022410B2 (ja) * 1997-06-17 2000-03-21 日本電気株式会社 インタフェース回路およびその判定レベル設定方法
TW381385B (en) * 1997-08-20 2000-02-01 Advantest Corp Signal transmission circuit, CMOS semiconductor device and circuit board
JP3087839B2 (ja) * 1997-08-28 2000-09-11 日本電気株式会社 半導体装置、そのテスト方法
JPH1188146A (ja) * 1997-09-04 1999-03-30 Fujitsu Ltd レベルインターフェース回路
KR100321177B1 (ko) * 1999-12-29 2002-03-18 박종섭 메모리모듈의 인쇄회로기판
US6744271B2 (en) * 2002-04-30 2004-06-01 Infineon Technologies Ag Internal generation of reference voltage
KR100596977B1 (ko) * 2004-08-20 2006-07-05 삼성전자주식회사 외부 기준 전압과 내부 기준 전압을 동시에 이용하는 기준전압 발생 회로 및 이를 이용한 기준 전압 발생 방법
US7154794B2 (en) * 2004-10-08 2006-12-26 Lexmark International, Inc. Memory regulator system with test mode
DE102004058612A1 (de) * 2004-12-04 2006-06-08 Infineon Technologies Ag Spannungsversorgungsschaltung, insbesondere für eine DRAM-Speicherschaltung sowie ein Verfahren zum Steuern einer Versorgungsquelle
CN100357856C (zh) * 2005-03-25 2007-12-26 威盛电子股份有限公司 主机板及其电源控制装置
US7343147B2 (en) * 2005-04-04 2008-03-11 Freescale Semiconductor, Inc. Method and apparatus for powering and loading software into a battery-less electronic device
KR100850272B1 (ko) * 2007-01-25 2008-08-04 삼성전자주식회사 반도체 메모리 장치의 전압 발생회로 및 사용 전압공급방법
CN101617371B (zh) 2007-02-16 2014-03-26 莫塞德技术公司 具有多个外部电源的非易失性半导体存储器
US8374049B2 (en) * 2010-04-08 2013-02-12 Agiga Tech Inc. DIMM memory module reference voltage switching circuit
CN103163802B (zh) * 2011-12-15 2015-05-13 快捷半导体(苏州)有限公司 输出控制电路、方法、及其应用设备
CN106199297A (zh) * 2016-09-10 2016-12-07 苏州创必成电子科技有限公司 输入数据有效性检测电路
CN106226685A (zh) * 2016-09-10 2016-12-14 苏州创必成电子科技有限公司 带有开关控制的多输入数据状态并行检测电路
US10033388B1 (en) * 2017-03-21 2018-07-24 Xilinx, Inc. Circuit for and method of enabling the selection of a circuit
TWI700795B (zh) * 2019-03-26 2020-08-01 瑞昱半導體股份有限公司 積體電路晶片及用於其之組態調整方法
CN111766935B (zh) * 2019-04-02 2022-06-21 瑞昱半导体股份有限公司 集成电路芯片及用于集成电路芯片的组态调整方法
KR102749603B1 (ko) * 2020-08-10 2025-01-02 에스케이하이닉스 주식회사 파워게이팅 동작을 수행하는 장치

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4130899A (en) * 1977-11-25 1978-12-19 Ncr Corporation System for operating volatile memory in normal and standby modes
US5297097A (en) * 1988-06-17 1994-03-22 Hitachi Ltd. Large scale integrated circuit for low voltage operation
DE69120483T2 (de) * 1990-08-17 1996-11-14 Sgs Thomson Microelectronics Halbleiter-Speicher mit unterdrücktem Testmodus-Eingang während des Strom-Einschaltens
KR930008886B1 (ko) * 1991-08-19 1993-09-16 삼성전자 주식회사 전기적으로 프로그램 할 수 있는 내부전원 발생회로
US5329168A (en) * 1991-12-27 1994-07-12 Nec Corporation Semiconductor integrated circuit device equipped with substrate biasing system selectively powered from internal and external power sources
JP2768172B2 (ja) * 1992-09-30 1998-06-25 日本電気株式会社 半導体メモリ装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100429919B1 (ko) * 2000-06-05 2004-05-04 닛뽕덴끼 가부시끼가이샤 반도체 장치 및 그 테스트 방법

Also Published As

Publication number Publication date
JPH0963277A (ja) 1997-03-07
CN1140884A (zh) 1997-01-22
GB2296592A (en) 1996-07-03
TW291626B (enExample) 1996-11-21
CN1121691C (zh) 2003-09-17
KR960027303A (ko) 1996-07-22
US5818783A (en) 1998-10-06
GB2296592B (en) 1998-09-23
GB9526695D0 (en) 1996-02-28
JP2771962B2 (ja) 1998-07-02

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