JPWO2021094844A1 - - Google Patents

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Publication number
JPWO2021094844A1
JPWO2021094844A1 JP2021555897A JP2021555897A JPWO2021094844A1 JP WO2021094844 A1 JPWO2021094844 A1 JP WO2021094844A1 JP 2021555897 A JP2021555897 A JP 2021555897A JP 2021555897 A JP2021555897 A JP 2021555897A JP WO2021094844 A1 JPWO2021094844 A1 JP WO2021094844A1
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JP
Japan
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JP2021555897A
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Japanese (ja)
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JPWO2021094844A5 (https=
JP7525506B2 (ja
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Priority to JP2024114714A priority Critical patent/JP7711280B2/ja
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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G11C11/4045—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell using a plurality of serially connected access transistors, each having a storage capacitor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Human Computer Interaction (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Memory System (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
JP2021555897A 2019-11-11 2020-08-26 情報処理装置、および情報処理装置の動作方法 Active JP7525506B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2024114714A JP7711280B2 (ja) 2019-11-11 2024-07-18 情報処理装置の動作方法

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2019203814 2019-11-11
JP2019203814 2019-11-11
JP2019209362 2019-11-20
JP2019209362 2019-11-20
PCT/IB2020/057947 WO2021094844A1 (ja) 2019-11-11 2020-08-26 情報処理装置、および情報処理装置の動作方法

Related Child Applications (1)

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JP2024114714A Division JP7711280B2 (ja) 2019-11-11 2024-07-18 情報処理装置の動作方法

Publications (3)

Publication Number Publication Date
JPWO2021094844A1 true JPWO2021094844A1 (https=) 2021-05-20
JPWO2021094844A5 JPWO2021094844A5 (https=) 2023-08-17
JP7525506B2 JP7525506B2 (ja) 2024-07-30

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JP2024114714A Active JP7711280B2 (ja) 2019-11-11 2024-07-18 情報処理装置の動作方法

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Country Status (5)

Country Link
US (1) US11776596B2 (https=)
JP (2) JP7525506B2 (https=)
KR (1) KR20220106991A (https=)
CN (1) CN114631145A (https=)
WO (1) WO2021094844A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20230074757A (ko) 2020-10-02 2023-05-31 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007242163A (ja) * 2006-03-09 2007-09-20 Toshiba Corp 半導体集積回路装置のデータ記録方式
JP2017168809A (ja) * 2015-10-22 2017-09-21 株式会社半導体エネルギー研究所 半導体装置、又は該半導体装置を有する記憶装置

Family Cites Families (73)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59168983A (ja) * 1983-03-17 1984-09-22 Seiko Epson Corp 半導体記憶装置
JP2869339B2 (ja) * 1993-08-09 1999-03-10 松下電器産業株式会社 ラインメモリ
JPH09101503A (ja) 1995-10-04 1997-04-15 Semiconductor Energy Lab Co Ltd 表示装置
TW522354B (en) 1998-08-31 2003-03-01 Semiconductor Energy Lab Display device and method of driving the same
US6876339B2 (en) 1999-12-27 2005-04-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and driving method thereof
JP2001273773A (ja) 2000-03-27 2001-10-05 Sanyo Electric Co Ltd 半導体メモリ装置
KR100387529B1 (ko) 2001-06-11 2003-06-18 삼성전자주식회사 랜덤 억세스 가능한 메모리 셀 어레이를 갖는 불휘발성반도체 메모리 장치
JP5138869B2 (ja) 2002-11-28 2013-02-06 ルネサスエレクトロニクス株式会社 メモリモジュール及びメモリシステム
JP4156985B2 (ja) * 2003-06-30 2008-09-24 株式会社東芝 半導体記憶装置
JP2005309304A (ja) 2004-04-26 2005-11-04 Seiko Epson Corp データ線駆動回路、電気光学装置および電子機器
US7586784B2 (en) * 2006-06-09 2009-09-08 Micron Technology, Inc. Apparatus and methods for programming multilevel-cell NAND memory devices
US8095104B2 (en) 2006-06-30 2012-01-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic device having the same
KR101381359B1 (ko) 2006-08-31 2014-04-04 가부시키가이샤 한도오따이 에네루기 켄큐쇼 클록 생성 회로 및 이 클록 생성 회로를 구비한 반도체장치
TWI481195B (zh) 2006-10-31 2015-04-11 半導體能源研究所股份有限公司 振盪器電路及包含該振盪器電路的半導體裝置
KR101428787B1 (ko) 2007-02-08 2014-08-08 가부시키가이샤 한도오따이 에네루기 켄큐쇼 클록 신호 생성 회로 및 반도체 장치
JP2010149654A (ja) 2008-12-25 2010-07-08 Sanyo Electric Co Ltd 車両用表示装置
US8649554B2 (en) 2009-05-01 2014-02-11 Microsoft Corporation Method to control perspective for a camera-controlled computer
KR101870119B1 (ko) 2009-12-25 2018-06-25 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
JP2011187794A (ja) 2010-03-10 2011-09-22 Toshiba Corp 半導体記憶装置及びその製造方法
JP5039168B2 (ja) * 2010-03-24 2012-10-03 株式会社東芝 半導体記憶装置
JP5709197B2 (ja) 2010-05-21 2015-04-30 国立大学法人 東京大学 集積回路装置
KR101258327B1 (ko) 2010-10-13 2013-04-25 주식회사 팬택 플렉서블 디스플레이부를 구비한 장치 및 그 디스플레이 방법
JP2012146861A (ja) 2011-01-13 2012-08-02 Toshiba Corp 半導体記憶装置
KR20130011138A (ko) 2011-07-20 2013-01-30 삼성전자주식회사 모노 랭크와 멀티 랭크로 호환 가능한 메모리 장치
WO2013080985A1 (ja) 2011-11-30 2013-06-06 シャープ株式会社 制御ユニット、該制御ユニットを含む表示装置、及び、制御方法
JP5842602B2 (ja) 2011-12-26 2016-01-13 株式会社Ｊｏｌｅｄ 曲面ディスプレイ
KR102033618B1 (ko) 2012-12-18 2019-10-17 엘지디스플레이 주식회사 표시장치와 이의 구동방법
JP2014127220A (ja) * 2012-12-27 2014-07-07 Toshiba Corp 半導体記憶装置
JP6405100B2 (ja) 2013-03-08 2018-10-17 株式会社半導体エネルギー研究所 半導体装置
KR102071573B1 (ko) 2013-06-13 2020-03-02 삼성전자주식회사 외부 클락 신호를 이용하여 오실레이터의 주파수를 조절할 수 있는 디스플레이 드라이버 ic, 이를 포함하는 장치, 및 이들의 동작 방법
JP2015004727A (ja) 2013-06-19 2015-01-08 シャープ株式会社 表示装置および表示方法
JP2015056642A (ja) 2013-09-13 2015-03-23 株式会社東芝 半導体記憶装置
US9973692B2 (en) 2013-10-03 2018-05-15 Flir Systems, Inc. Situational awareness by compressed display of panoramic views
JP2015075516A (ja) 2013-10-07 2015-04-20 ソニー株式会社 画像処理装置、画像処理方法、および表示装置
US20150155039A1 (en) 2013-12-02 2015-06-04 Silicon Storage Technology, Inc. Three-Dimensional Flash NOR Memory System With Configurable Pins
DE112015001133T5 (de) 2014-03-07 2016-12-01 Semiconductor Energy Laboratory Co., Ltd. Betriebsverfahren für eine Halbleitervorrichtung
JP6525421B2 (ja) * 2014-03-13 2019-06-05 株式会社半導体エネルギー研究所 半導体装置
KR102172980B1 (ko) 2014-04-07 2020-11-02 삼성전자주식회사 타일드 디스플레이 시스템 및 그 화상 처리 방법
KR102321501B1 (ko) * 2014-05-14 2021-11-05 삼성전자주식회사 불휘발성 메모리 장치 및 그것을 포함하는 스토리지 장치의 동작 방법
KR102247087B1 (ko) * 2014-07-08 2021-05-03 삼성전자주식회사 스토리지 장치 및 스토리지 장치의 동작 방법
KR102238592B1 (ko) * 2014-08-08 2021-04-09 삼성전자주식회사 비휘발성 메모리 장치의 디폴트 독출 전압 설정 방법 및 비휘발성 메모리 장치의 데이터 독출 방법
US9544994B2 (en) 2014-08-30 2017-01-10 Lg Display Co., Ltd. Flexible display device with side crack protection structure and manufacturing method for the same
US9543370B2 (en) 2014-09-24 2017-01-10 Apple Inc. Silicon and semiconducting oxide thin-film transistor displays
JP6615565B2 (ja) 2014-10-24 2019-12-04 株式会社半導体エネルギー研究所 半導体装置
US9634097B2 (en) 2014-11-25 2017-04-25 Sandisk Technologies Llc 3D NAND with oxide semiconductor channel
US9847135B2 (en) * 2015-01-30 2017-12-19 Toshiba Memory Corporation Memory device and method of reading data
US9761732B2 (en) 2015-02-25 2017-09-12 Snaptrack Inc. Tunnel thin film transistor with hetero-junction structure
JP6290124B2 (ja) * 2015-03-12 2018-03-07 東芝メモリ株式会社 半導体記憶装置
KR102282196B1 (ko) * 2015-04-28 2021-07-27 삼성전자 주식회사 비휘발성 메모리 장치, 메모리 시스템 및 그것의 동작 방법
JP2016225613A (ja) 2015-05-26 2016-12-28 株式会社半導体エネルギー研究所 半導体装置及び半導体装置の駆動方法
JP6343256B2 (ja) 2015-05-29 2018-06-13 東芝メモリ株式会社 半導体装置及びその製造方法
KR102553553B1 (ko) 2015-06-12 2023-07-10 가부시키가이샤 한도오따이 에네루기 켄큐쇼 촬상 장치, 및 그 동작 방법 및 전자 기기
KR20170008999A (ko) * 2015-07-15 2017-01-25 에스케이하이닉스 주식회사 메모리 시스템 및 메모리의 동작 방법
JP6400536B2 (ja) 2015-08-04 2018-10-03 東芝メモリ株式会社 半導体記憶装置
US10410599B2 (en) 2015-08-13 2019-09-10 Samsung Electronics Co., Ltd. Source driver integrated circuit for ompensating for display fan-out and display system including the same
JP6545587B2 (ja) 2015-09-15 2019-07-17 東芝メモリ株式会社 半導体装置
KR20180081732A (ko) 2015-11-13 2018-07-17 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치, 전자 부품, 및 전자 기기
JP2017111847A (ja) * 2015-12-17 2017-06-22 株式会社東芝 半導体記憶装置
KR102465169B1 (ko) * 2015-12-21 2022-11-11 에스케이하이닉스 주식회사 전자 장치
US10475370B2 (en) 2016-02-17 2019-11-12 Google Llc Foveally-rendered display
JP6433933B2 (ja) * 2016-03-14 2018-12-05 東芝メモリ株式会社 半導体記憶装置及びメモリシステム
KR102547795B1 (ko) * 2016-05-04 2023-06-27 에스케이하이닉스 주식회사 데이터 처리 시스템 및 데이터 처리 시스템의 동작 방법
JP6940974B2 (ja) 2016-05-10 2021-09-29 株式会社半導体エネルギー研究所 移動体
JP2017207747A (ja) 2016-05-17 2017-11-24 株式会社半導体エネルギー研究所 表示システムおよび移動体
US10930205B2 (en) 2016-05-19 2021-02-23 Semiconductor Energy Laboratory Co., Ltd. Display system and moving object
US9859298B1 (en) * 2016-06-23 2018-01-02 Sandisk Technologies Llc Amorphous silicon layer in memory device which reduces neighboring word line interference
KR102696801B1 (ko) 2016-07-27 2024-08-20 삼성전자주식회사 수직형 메모리 소자 및 이의 제조방법
JP6693907B2 (ja) 2017-06-08 2020-05-13 株式会社半導体エネルギー研究所 半導体装置、記憶装置、及び電子機器
US10593693B2 (en) 2017-06-16 2020-03-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
JP7195068B2 (ja) 2017-06-26 2022-12-23 株式会社半導体エネルギー研究所 半導体装置、電子機器
US11682667B2 (en) 2017-06-27 2023-06-20 Semiconductor Energy Laboratory Co., Ltd. Memory cell including cell transistor including control gate and charge accumulation layer
CN108733325B (zh) * 2018-05-25 2020-12-18 山东大学 一种基于非挥发性存储器的数据自毁方法及系统
TW202602212A (zh) 2019-10-31 2026-01-01 日商半導體能源研究所股份有限公司 半導體裝置及電子裝置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007242163A (ja) * 2006-03-09 2007-09-20 Toshiba Corp 半導体集積回路装置のデータ記録方式
JP2017168809A (ja) * 2015-10-22 2017-09-21 株式会社半導体エネルギー研究所 半導体装置、又は該半導体装置を有する記憶装置

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