JPWO2017043068A1 - 固体撮像素子 - Google Patents
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Abstract
Description
まず、図1及び図2を参照しながら、実施の形態1に係る固体撮像素子の構造を説明する。なお、本明細書において、「平面視」とは、図1に示す第1主面S1及び第2主面S2の法線方向から見ることを指す。
次に、図6を参照しながら、実施の形態2に係る固体撮像素子の構造を説明する。図6は、実施の形態2にかかる固体撮像素子において、トランジスタTR1がNチャネルの場合の断面図である。図7は、図6の第1主面S1を第2主面S2の方へ見たときの平面図である。図7においては、位置関係の理解の向上のため、トランジスタのゲート電極40も併せて図示している。
図8は、実施の形態3に係る固体撮像素子の断面図である。図9は、図8の第1主面S1を第2主面S2の方へ見たときの平面図である。図9においては、位置関係の理解の向上のため、トランジスタのゲート電極40も併せて図示している。図10は、図8のAA’線での断面を第2主面S2の方へ見たときの平面図である。図11は、図8のBB’線での断面を第2主面S2の方へ見たときの平面図である。図12は、図8のCC’線上において、P+型半導体領域10に固定電位Vpdを印加したときのポテンシャル勾配を示した図である。図8〜図12において、実施の形態1と同様の要素については同一の符号を付している。また、以下では、実施の形態1との相違点を主に説明する。
以上、本開示の実施の形態及び変形例に係る固体撮像素子について説明したが、本開示は、上記実施の形態及び変形例に限定されるものではない。
3、3’ 画素終端部
10 P+型半導体領域
11 基板
12、13、13’、18 N型半導体領域
14、19、31 P型半導体領域
15、15’、16 N型ウェル
17 配線層
20 コンタクトプラグ
21 配線
22、30 P型ウェル
32 画素間分離領域
32a 画素終端部分離領域
33 P+型半導体領域(表面不活性領域)
40 ゲート電極
41 拡散領域
100 固体撮像素子
101 外部電源
102 画素アレイ
103 垂直走査回路
104 水平走査回路
105 読み出し回路
106 転送トランジスタ
107 リセットトランジスタ
108 浮遊拡散領域
109 増幅トランジスタ
110 選択トランジスタ
111 バッファアンプ
PD 光電変換部
AM アバランシェ増倍領域
S1 第1主面
S2 第2主面
TR1 トランジスタ
TR2 増幅トランジスタ
TR3 転送トランジスタ
Claims (10)
- 第1画素及び前記第1画素に隣接する第2画素を含む画素アレイを備える固体撮像素子であって、
前記画素アレイは、
第1主面及び前記第1主面の反対側であって光が入射する第2主面を有する第1導電型の基板と、
前記第1主面上に配置された配線層とを備え、
前記基板は、
前記第1画素及び前記第2画素のそれぞれについて形成され、前記基板の内部に配置され、前記第1主面から前記第2主面の方向に伸び、且つ、前記第1導電型と異なる第2導電型の第1の半導体領域と、
前記第1画素及び前記第2画素のそれぞれについて形成され、前記基板の内部であって前記第2主面と前記第1の半導体領域との間に配置され、前記第1の半導体領域と接続され、且つ、前記第2導電型の第2の半導体領域と、
前記基板の内部であって前記第2主面と前記第1画素及び前記第2画素の前記第2の半導体領域との間に配置され、前記第1導電型の第3の半導体領域と、
前記基板の内部であって、かつ、前記第1画素の前記第1の半導体領域と前記第2画素の前記第1の半導体領域との間であって、前記第1主面に配置された第1のウェル領域と、
前記第1のウェル領域内に配置された画素回路と、
前記基板の内部であって前記第1画素の前記第2の半導体領域と前記第2画素の前記第2の半導体領域との間に配置された画素間分離領域とを備え、
前記第2の半導体領域と前記第3の半導体領域とは、アバランシェ増倍領域を形成する
固体撮像素子。 - 前記第1のウェル領域は、前記第1導電型であり、前記画素間分離領域によって、前記第3の半導体領域と電気的に分離されている
請求項1に記載の固体撮像素子。 - 前記第1のウェル領域と、前記第2の半導体領域との間に配置され、前記第2の半導体領域と電気的に分離された、前記第2導電型の第2のウェル領域をさらに備える
請求項2に記載の固体撮像素子。 - 前記画素間分離領域における電子に対するポテンシャル障壁は、前記第1の半導体領域と前記第2のウェル領域との間の前記第1導電型の領域における電子に対するポテンシャル障壁よりも高い
請求項3に記載の固体撮像素子。 - 前記第1の半導体領域と前記第1主面との間に配置された前記第2導電型の表面不活性領域をさらに備え、
前記画素回路は、前記第1の半導体領域をソース領域とするMOS型トランジスタを有する
請求項2〜4のいずれか1項に記載の固体撮像素子。 - 前記画素間分離領域は、前記第1導電型、又は、前記第2の半導体領域の不純物濃度よりも低濃度の前記第2導電型である
請求項1〜5のいずれか1項に記載の固体撮像素子。 - 前記第1の半導体領域は、前記第1主面側での前記第1主面に平行な面での断面における面積よりも、前記第2主面側での前記第1主面に平行な面での断面における面積が大きい
請求項1〜6のいずれか1項に記載の固体撮像素子。 - 前記第3の半導体領域と前記第2主面との間の領域における不純物濃度は、前記第3の半導体領域の不純物濃度よりも低い
請求項1〜7のいずれか1項に記載の固体撮像素子。 - 前記基板の内部であって、前記画素アレイを囲み、前記第1主面に接する前記第2導電型の第4の半導体領域をさらに備え、
前記第4の半導体領域と前記基板における前記第4の半導体領域と接する領域とによって形成されるPN接合における不純物濃度の勾配は、前記第2の半導体領域と前記第3の半導体領域とによって形成されるPN接合における不純物濃度の勾配よりも小さい
請求項1〜8のいずれか1項に記載の固体撮像素子。 - 前記第4の半導体領域に電気的に接続される第5の半導体領域と、
前記画素アレイの最外周の画素における前記第2の半導体領域と前記第5の半導体領域とを電気的に分離するための画素終端部分離領域とをさらに備え、
前記画素終端部分離領域は空乏化している
請求項9に記載の固体撮像素子。
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US201562216238P | 2015-09-09 | 2015-09-09 | |
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US201662275998P | 2016-01-07 | 2016-01-07 | |
US62/275,998 | 2016-01-07 | ||
PCT/JP2016/004058 WO2017043068A1 (ja) | 2015-09-09 | 2016-09-06 | 固体撮像素子 |
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JP6846648B2 (ja) * | 2017-03-21 | 2021-03-24 | パナソニックIpマネジメント株式会社 | 固体撮像素子及びその製造方法 |
JP7178605B2 (ja) * | 2017-03-22 | 2022-11-28 | パナソニックIpマネジメント株式会社 | 固体撮像装置 |
JPWO2019180898A1 (ja) * | 2018-03-23 | 2021-03-25 | パナソニックIpマネジメント株式会社 | 固体撮像素子 |
JP7174932B2 (ja) * | 2018-03-23 | 2022-11-18 | パナソニックIpマネジメント株式会社 | 固体撮像素子 |
JP6967755B2 (ja) * | 2018-03-30 | 2021-11-17 | パナソニックIpマネジメント株式会社 | 光検出器 |
US10193009B1 (en) | 2018-04-05 | 2019-01-29 | Stmicroelectronics (Crolles 2) Sas | Single photon avalanche gate sensor device |
JP7008653B2 (ja) * | 2019-02-07 | 2022-01-25 | 株式会社東芝 | 分子検出装置 |
JP7327949B2 (ja) * | 2019-02-27 | 2023-08-16 | キヤノン株式会社 | 光電変換装置、光電変換システム、及び移動体 |
JP7129664B2 (ja) * | 2019-03-28 | 2022-09-02 | パナソニックIpマネジメント株式会社 | 光検出器 |
CN110544667A (zh) * | 2019-08-28 | 2019-12-06 | 上海集成电路研发中心有限公司 | 一种深耗尽的图像传感器像素单元结构及制作方法 |
CN114631188A (zh) * | 2019-10-29 | 2022-06-14 | 松下知识产权经营株式会社 | 光电传感器及使用该光电传感器的距离测量系统 |
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