JPWO2015029159A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JPWO2015029159A1 JPWO2015029159A1 JP2015533844A JP2015533844A JPWO2015029159A1 JP WO2015029159 A1 JPWO2015029159 A1 JP WO2015029159A1 JP 2015533844 A JP2015533844 A JP 2015533844A JP 2015533844 A JP2015533844 A JP 2015533844A JP WO2015029159 A1 JPWO2015029159 A1 JP WO2015029159A1
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- Prior art keywords
- electrode pad
- semiconductor device
- temperature sensing
- sensing diode
- semiconductor substrate
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 74
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 12
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 230000001681 protective effect Effects 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000036413 temperature sense Effects 0.000 description 1
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- General Physics & Mathematics (AREA)
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Abstract
Description
まず、本発明の前提となる技術(前提技術)について説明する。
図1は、本発明の実施の形態1による半導体装置1の構成の一例を示す平面図である。また、図2は、図1のA−A断面の一例を示す断面図である。
図4は、本発明の実施の形態2による半導体装置1の構成の一例を示す断面図であり、図1のA−A断面の一例を示している。
Claims (6)
- 半導体基板に形成されたスイッチング素子と、
前記半導体基板に形成された温度センスダイオードと、
前記半導体基板上に配設された前記スイッチング素子の主電流電極パッドと、
前記半導体基板上に配設され、前記温度センスダイオードの一方電極と前記主電流電極パッドとを電気的に接続する導電膜と、
を備える、半導体装置。 - 前記半導体基板上に配設された前記温度センスダイオードの一方電極パッドをさらに備え、
前記導電膜は、前記一方電極パッドと前記主電流電極パッドとを電気的に接続することを特徴とする、請求項1に記載の半導体装置。 - 前記導電膜は、前記温度センスダイオードの一方電極パッドを介することなく、前記温度センスダイオードの一方電極と前記主電流電極パッドとを電気的に接続することを特徴とする、請求項1に記載の半導体装置。
- 前記半導体基板上に配設された前記半導体スイッチング素子の制御電極配線をさらに備え、
前記導電膜は、前記制御電極配線と同一工程で形成されることを特徴とする、請求項3に記載の半導体装置。 - 前記半導体基板上の周縁部に配設された前記温度センスダイオードの他方電極パッドをさらに備え、
前記温度センスダイオードは、前記半導体基板上の中央部に形成されることを特徴とする、請求項4に記載の半導体装置。 - 前記主電流電極パッド上にはんだと接合可能な金属膜をさらに備え、
前記導電膜は、前記金属膜と同一工程で形成されることを特徴とする、請求項1に記載の半導体装置。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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PCT/JP2013/072960 WO2015029159A1 (ja) | 2013-08-28 | 2013-08-28 | 半導体装置 |
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JPWO2015029159A1 true JPWO2015029159A1 (ja) | 2017-03-02 |
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Application Number | Title | Priority Date | Filing Date |
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JP2015533844A Pending JPWO2015029159A1 (ja) | 2013-08-28 | 2013-08-28 | 半導体装置 |
Country Status (5)
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US (1) | US9716052B2 (ja) |
JP (1) | JPWO2015029159A1 (ja) |
CN (1) | CN105518865A (ja) |
DE (1) | DE112013007376T5 (ja) |
WO (1) | WO2015029159A1 (ja) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE112013007361B4 (de) | 2013-08-23 | 2019-07-04 | Mitsubishi Electric Corporation | Halbleitervorrichtung |
JP6526981B2 (ja) * | 2015-02-13 | 2019-06-05 | ローム株式会社 | 半導体装置および半導体モジュール |
US10637460B2 (en) | 2016-06-14 | 2020-04-28 | Macom Technology Solutions Holdings, Inc. | Circuits and operating methods thereof for monitoring and protecting a device |
US20180109228A1 (en) | 2016-10-14 | 2018-04-19 | MACOM Technology Solution Holdings, Inc. | Phase shifters for gallium nitride amplifiers and related methods |
JP7013668B2 (ja) * | 2017-04-06 | 2022-02-01 | 富士電機株式会社 | 半導体装置 |
US20190028065A1 (en) | 2017-07-24 | 2019-01-24 | Macom Technology Solutions Holdings, Inc. | Fet operational temperature determination by gate structure resistance thermometry |
US20190028066A1 (en) | 2017-07-24 | 2019-01-24 | Macom Technology Solutions Holdings, Inc. | Fet operational temperature determination by field plate resistance thermometry |
US20190078941A1 (en) * | 2017-09-14 | 2019-03-14 | Macom Technology Solutions Holdings, Inc. | Operational temperature determination in bipolar transistors by resistance thermometry |
JP6819540B2 (ja) * | 2017-10-23 | 2021-01-27 | 三菱電機株式会社 | 半導体装置 |
CN109786367B (zh) * | 2019-01-31 | 2024-04-05 | 惠州市忠邦电子有限公司 | 一种具有内部集成温度保护装置的Mosfet半导体器件 |
JP7103256B2 (ja) * | 2019-02-13 | 2022-07-20 | 株式会社デンソー | 半導体装置 |
JP7001785B2 (ja) * | 2020-10-02 | 2022-01-20 | ローム株式会社 | 半導体装置および半導体モジュール |
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CN105518865A (zh) | 2016-04-20 |
DE112013007376T5 (de) | 2016-05-19 |
WO2015029159A1 (ja) | 2015-03-05 |
US9716052B2 (en) | 2017-07-25 |
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