WO2015029159A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2015029159A1
WO2015029159A1 PCT/JP2013/072960 JP2013072960W WO2015029159A1 WO 2015029159 A1 WO2015029159 A1 WO 2015029159A1 JP 2013072960 W JP2013072960 W JP 2013072960W WO 2015029159 A1 WO2015029159 A1 WO 2015029159A1
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WIPO (PCT)
Prior art keywords
electrode pad
semiconductor device
temperature sensing
sensing diode
cathode
Prior art date
Application number
PCT/JP2013/072960
Other languages
English (en)
French (fr)
Inventor
毅 大佐賀
三紀夫 石原
日山　一明
達也 川瀬
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to DE112013007376.5T priority Critical patent/DE112013007376T5/de
Priority to CN201380079189.1A priority patent/CN105518865A/zh
Priority to PCT/JP2013/072960 priority patent/WO2015029159A1/ja
Priority to JP2015533844A priority patent/JPWO2015029159A1/ja
Priority to US14/894,456 priority patent/US9716052B2/en
Publication of WO2015029159A1 publication Critical patent/WO2015029159A1/ja

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    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Definitions

  • the present invention relates to a semiconductor device including a switching element and a temperature sensing diode for measuring the operating temperature on one chip.
  • Power modules equipped with power chips such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductors Field Field Effect Transistors) are used as switching devices that perform switching operations to turn on and off current at high speed Yes.
  • IGBTs Insulated Gate Bipolar Transistors
  • MOSFETs Metal Oxide Semiconductors Field Field Effect Transistors
  • the temperature of the power chip can be detected by converting the value of the forward voltage VF of the temperature sensing diode into a temperature.
  • the process of converting the forward voltage VF of the temperature sensing diode into temperature has been performed by a control circuit provided separately from the power chip in the power module and connected to the power chip.
  • a control circuit provided separately from the power chip in the power module and connected to the power chip.
  • the cathode electrode pad of the temperature sensing diode and the main electrode pad of the switching element are provided separately in the power chip, and when both electrode pads are short-circuited, the relay provided from each electrode pad outside the power chip There was a problem that it was necessary to wire the terminals, and the assemblability was poor.
  • the present invention has been made to solve these problems, and an object of the present invention is to provide a semiconductor device capable of improving assemblability and downsizing.
  • a semiconductor device includes a switching element formed on a semiconductor substrate, a temperature sensing diode formed on the semiconductor substrate, and a main current of the switching element disposed on the semiconductor substrate.
  • An electrode pad and a conductive film disposed on the semiconductor substrate and electrically connecting one electrode of the temperature sensing diode and the main current electrode pad are provided.
  • the switching element formed on the semiconductor substrate, the temperature sensing diode formed on the semiconductor substrate, the main current electrode pad of the switching element disposed on the semiconductor substrate, and the semiconductor substrate are disposed on the semiconductor substrate. Since the conductive film for electrically connecting the one electrode of the temperature sensing diode and the main current electrode pad is provided, the assembling property can be improved and the size can be reduced.
  • the switching element formed on the substrate (semiconductor substrate) of the semiconductor device is assumed to be an IGBT.
  • FIG. 7 is a plan view showing an example of the configuration of the semiconductor device 1 (power chip) according to the base technology.
  • the semiconductor device 1 is provided with an emitter electrode pad 6 (main current electrode pad), a gate electrode pad 7 and a trench 8 on a substrate to form an IGBT (switching element).
  • the temperature sensing diode 2 is formed on the substrate.
  • the cathode electrode 2a of the temperature sensing diode 2 is connected to the cathode electrode pad 3 through the cathode wiring 4a. Further, the anode electrode 2b of the temperature sensing diode 2 is connected to the anode electrode pad 5 through the anode wiring 4b.
  • the relay terminal 9a is an element in the terminal unit 9 provided in the power module including the semiconductor device 1 and a control circuit (not shown).
  • the relay terminal connection wiring 10 may be, for example, an aluminum wire or another metal wire.
  • FIG. 8 is a cross-sectional view showing an example of the AA cross section of FIG. In FIG. 8, only main components necessary for the description are shown in a simplified manner for the sake of simplicity.
  • the cathode electrode pad 3 and the emitter electrode pad 6 are formed via the insulating film 14.
  • a trench 8 for forming a gate electrode of each cell of the IGBT is formed under the emitter electrode pad 6 of the Si substrate 13. Note that the pitch of the trenches 8 does not match between FIG. 7 and FIG.
  • the doped polysilicon 15 and the gate metal wiring 16 are formed by being laminated, and are provided separately between the cathode electrode pad 3 and the emitter electrode pad 6.
  • the doped polysilicon 15 and the gate metal wiring 16 constitute a gate wiring portion 17, and the gate wiring portion 17 is connected to the gate electrode pad 7.
  • the protective film 18 is formed so as to cover the insulating film 14, the gate metal wiring 16, some cathode electrode pads 3, and some emitter electrode pads 6.
  • the temperature sensing diode 2 is also formed on the Si substrate 13.
  • the cathode electrode pad 3 and the emitter electrode pad 6 are insulated (not electrically connected).
  • the cathode electrode pad 3 and the emitter electrode pad 6 are short-circuited and used, in which case the relay terminal connection wiring 10 is drawn out from the cathode electrode pad 3 and the emitter electrode pad 6 and is connected to each of the relay terminals 9a. It is necessary to short-circuit the cathode electrode pad 3 and the emitter electrode pad 6 by connecting the relay terminal connection wiring 10 drawn from the electrode pad. Therefore, there is a problem that the assembling property of the semiconductor device 1 is deteriorated.
  • the present invention has been made to solve the above problems, and will be described in detail below.
  • FIG. 1 is a plan view showing an example of the configuration of the semiconductor device 1 according to the first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view showing an example of the AA cross section of FIG.
  • the semiconductor device 1 according to the first embodiment is provided with conductive cathode-emitter connection wiring 19 (conductive film) for electrically connecting the cathode electrode pad 3 and the emitter electrode pad 6. It is characterized by that. Since other configurations are the same as those of the semiconductor device 1 according to the base technology shown in FIG. 7, the description thereof is omitted here.
  • the cathode / emitter connection wiring 19 is provided so as to connect (short-circuit) the cathode electrode pad 3 and the emitter electrode pad 6 so as to cover the protective film 18. That is, the cathode-emitter connection wiring 19 is disposed on the Si substrate 13, and the cathode electrode pad 3 (one electrode pad) connected to the cathode electrode 2 a (one electrode) of the temperature sensing diode 2 and the emitter electrode pad. 6 (main current electrode pad) is electrically connected.
  • the cathode / emitter connection wiring 19 may be formed of, for example, an aluminum film, or may be formed of another conductive metal film.
  • the cathode / emitter connection wiring 19 By providing the cathode / emitter connection wiring 19, the cathode electrode pad 3 and the emitter electrode pad 6 have the same potential. Therefore, as shown in FIG. 1, the relay terminal connection wiring 10 for connecting the cathode electrode pad 3 and the relay terminal 9a becomes unnecessary.
  • FIG. 3 is a cross-sectional view showing an example of the BB cross section of FIG.
  • the gate electrode pad 7 is directly connected to the gate metal wiring 16.
  • the doped polysilicon 15 is filled in the trench 8, and the doped polysilicon 15 is connected to the gate metal wiring 16 (that is, constitutes a trench gate).
  • the cathode electrode pad 3 and the emitter electrode pad 6 can be short-circuited inside the semiconductor device 1. Therefore, the relay terminal connection wiring 10 for connecting the cathode electrode pad 3 and the relay terminal 9a is not necessary, and the assembling property and the size of the semiconductor device 1 can be improved.
  • a metal film (Front (Metal: FM) that can be joined to the solder is formed on the emitter electrode pad 6.
  • the metal film may be formed as the cathode-emitter connection wiring 19.
  • the metal film (FM) and the cathode / emitter connection wiring 19 can be formed at the same time (in the same process), so that the cathode / emitter connection wiring 19 is not added without adding a new process. Can be formed.
  • FIG. 4 is a sectional view showing an example of the configuration of the semiconductor device 1 according to the second embodiment of the present invention, and shows an example of the AA section of FIG.
  • the semiconductor device 1 according to the second embodiment is formed by connecting the cathode electrode pad 3 and the emitter electrode pad 6 in the same layer, and the cathode electrode pad 3 and the emitter electrode pad 6.
  • the gate metal wiring 16 control electrode wiring
  • the doped polysilicon 15 is continuously formed in the divided portion of the gate metal wiring 16.
  • the conductive film that electrically connects the cathode electrode pad 3 and the emitter electrode pad 6 can be formed in the same process as the gate metal wiring 16.
  • Other configurations are the same as those of the first embodiment (see FIGS. 1 to 3), and thus description thereof is omitted here.
  • the conductive film that electrically connects the cathode electrode pad 3 and the emitter electrode pad 6 is formed in the same process.
  • the cathode electrode pad 3 and the emitter electrode pad 6 can be short-circuited without adding a new manufacturing process.
  • the cathode-emitter connecting portion 20 may be configured as shown in FIG. 4 so that the cathode wiring 4a is directly connected to the cathode electrode pad 3 and the emitter electrode pad 6. . That is, the conductive film that electrically connects the cathode electrode pad 3 and the emitter electrode pad 6 does not pass through the cathode electrode pad 3 of the temperature sensing diode 2 as shown in FIG. And the emitter electrode pad 6 are electrically connected.
  • the cathode-emitter connection portion 20 indicates a portion where the cathode wiring 4 a and the emitter electrode pad 6 are connected. With such a configuration, the cathode electrode pad 3 can be omitted, and the effective area in the semiconductor device 1 can be expanded.
  • the anode electrode pad 5 (the other electrode pad) of the temperature sensing diode 2 is disposed on the peripheral edge on the semiconductor substrate, and the temperature sensing diode 2 is arranged.
  • the same effect as described above can be obtained by forming the film at the center of the semiconductor substrate.
  • the position of the anode electrode pad 5 may be arbitrarily changed. Thereby, the freedom degree of design improves.
  • SYMBOLS 1 Semiconductor device, 2 temperature sense diode, 2a cathode electrode, 2b anode electrode, 3 cathode electrode pad, 4a cathode wiring, 4b anode wiring, 5 anode electrode pad, 6 emitter electrode pad, 7 gate electrode pad, 8 trench, 9 terminal Part, 9a relay terminal, 10 relay terminal connection wiring, 11 N ⁇ layer, 12 P layer, 13 Si substrate, 14 insulating film, 15 doped polysilicon, 16 gate metal wiring, 17 gate wiring part, 18 protective film, 19 Cathode-emitter connection wiring, 20 Cathode-emitter connection.

Abstract

　本発明は、組み立て性の向上および小型化が可能な半導体装置を提供することを目的とする。本発明による半導体装置１は、Ｓｉ基板１３に形成されたＩＧＢＴと、Ｓｉ基板１３に形成された温度センスダイオード２と、Ｓｉ基板１３上に配設されたＩＧＢＴのエミッタ電極パッド６と、Ｓｉ基板１３上に配設され、温度センスダイオード２のカソード電極パッド３とエミッタ電極パッド６とを電気的に接続するカソード・エミッタ接続用配線１９とを備える。

Description

半導体装置
　本発明は、１チップ上にスイッチング素子とその動作温度を測定する温度センスダイオードとを備えた半導体装置に関する。
　ＩＧＢＴ（Insulated Gate Bipolar Transistor）やＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）等のパワーチップ（半導体装置）を搭載したパワーモジュールは、電流を高速で通電／遮断するスイッチング動作を行うスイッチング装置として用いられている。
　スイッチング動作を続けると、スイッチング装置に流れる電流とスイッチング装置に印加される電圧との積分による電力損失がパワーチップにて発熱として発生する。パワーチップの温度が動作保証範囲を超えてしまうと、パワーチップに不具合が生じる可能性がある。
　従来、パワーチップの温度が動作保証範囲を超えないようにするために、パワーチップの表面温度をモニタする温度センスダイオードを備えたパワーチップが用いられている（例えば、特許文献１～３参照）。
特開２００７－２８７９１９号公報 特開平８－２１３４４１号公報 特開平１０－１１６９８７号公報
　ダイオードの順電圧ＶＦは、温度の上昇に応じて低下するため、温度センスダイオードの順電圧ＶＦの値を温度に換算することによってパワーチップの温度検出を行うことができる。
　従来、温度センスダイオードの順電圧ＶＦを温度に換算する処理は、パワーモジュール内にパワーチップとは別に設けられ当該パワーチップに接続された制御回路が行っていた。パワーチップと制御回路とを接続する際は、パワーチップ内の温度センスダイオードのカソード電極（端子）と、パワーチップ内のスイッチング素子の主電極（例えば、スイッチング素子がＩＧＢＴの場合はエミッタ電極）とを、制御回路内や中継端子で接続していた。すなわち、温度センスダイオードのカソード電極パッドとスイッチング素子の主電極パッドとがパワーチップ内で分離して設けられており、両電極パッドを短絡させる場合は各電極パッドからパワーチップ外に設けられた中継端子に配線を施す必要があり、組み立て性が悪いという問題があった。
　本発明は、これらの問題を解決するためになされたものであり、組み立て性の向上および小型化が可能な半導体装置を提供することを目的とする。
　上記の課題を解決するために、本発明による半導体装置は、半導体基板に形成されたスイッチング素子と、半導体基板に形成された温度センスダイオードと、半導体基板上に配設されたスイッチング素子の主電流電極パッドと、半導体基板上に配設され、温度センスダイオードの一方電極と主電流電極パッドとを電気的に接続する導電膜とを備える。
　本発明によると、半導体基板に形成されたスイッチング素子と、半導体基板に形成された温度センスダイオードと、半導体基板上に配設されたスイッチング素子の主電流電極パッドと、半導体基板上に配設され、温度センスダイオードの一方電極と主電流電極パッドとを電気的に接続する導電膜とを備えるため、組み立て性の向上および小型化が可能となる。
　この発明の目的、特徴、態様、および利点は、以下の詳細な説明と添付図面とによって、より明白となる。
本発明の実施の形態１による半導体装置の構成の一例を示す平面図である。 本発明の実施の形態１による半導体装置の構成の一例を示す断面図である。 本発明の実施の形態１による半導体装置の構成の一例を示す断面図である。 本発明の実施の形態２による半導体装置の構成の一例を示す断面図である。 本発明の実施の形態２による半導体装置の構成の他の一例を示す平面図である。 本発明の実施の形態２による半導体装置の構成の他の一例を示す平面図である。 前提技術による半導体装置の構成の一例を示す平面図である。 前提技術による半導体装置の構成の一例を示す断面図である。
　本発明の実施の形態について、図面に基づいて以下に説明する。
　なお、本実施の形態において、半導体装置の基板（半導体基板）上に形成されるスイッチング素子はＩＧＢＴであるものとして説明する。
　＜前提技術＞
　まず、本発明の前提となる技術（前提技術）について説明する。
　図７は、前提技術による半導体装置１（パワーチップ）の構成の一例を示す平面図である。
　半導体装置１は、基板上にエミッタ電極パッド６（主電流電極パッド）、ゲート電極パッド７、およびトレンチ８を設けてＩＧＢＴ（スイッチング素子）を形成している。また、半導体装置１は、基板上に温度センスダイオード２を形成している。
　温度センスダイオード２のカソード電極２ａは、カソード配線４ａを介してカソード電極パッド３に接続されている。また、温度センスダイオード２のアノード電極２ｂは、アノード配線４ｂを介してアノード電極パッド５に接続されている。
　カソード電極パッド３、アノード電極パッド５、およびゲート電極パッド７の各々は、中継端子接続用配線１０を介して中継端子９ａに接続されている。中継端子９ａは、半導体装置１と図示しない制御回路とを含むパワーモジュールに備えられた端子部９の中の一要素である。なお、中継端子接続用配線１０は、例えばアルミニウムワイヤであってもよく、他の金属ワイヤであってもよい。
　なお、図示していないが、制御回路から引き出された配線も必要に応じて中継端子９ａに接続されているものとする。
　図８は、図７のＡ－Ａ断面の一例を示す断面図である。なお、図８においては、説明を簡単にするために、説明に必要な主な構成要素のみを簡略化して図示している。
　Ｎ－層１１およびＰ層１２からなるＳｉ基板１３（半導体基板）上には、絶縁膜１４を介してカソード電極パッド３およびエミッタ電極パッド６が形成されている。
　Ｓｉ基板１３のエミッタ電極パッド６下には、ＩＧＢＴの各セルのゲート電極を形成するためのトレンチ８が形成されている。なお、トレンチ８のピッチは、図７と図８とでは一致していない。
　ドープドポリシリコン１５およびゲートメタル配線１６は、積層して形成されており、カソード電極パッド３とエミッタ電極パッド６との間に離間して設けられている。また、ドープドポリシリコン１５およびゲートメタル配線１６はゲート配線部１７を構成し、ゲート配線部１７はゲート電極パッド７に接続されている。
　保護膜１８は、絶縁膜１４、ゲートメタル配線１６、一部のカソード電極パッド３、および一部のエミッタ電極パッド６を覆うように形成されている。
　なお、図８の断面図には表われていないが、温度センスダイオード２もＳｉ基板１３上に形成されている。
　上記のように、前提技術による半導体装置１では、カソード電極パッド３とエミッタ電極パッド６とが絶縁されている（電気的に接続されていない）。しかしながら、カソード電極パッド３とエミッタ電極パッド６とを短絡して使用する場合があり、その場合はカソード電極パッド３およびエミッタ電極パッド６から中継端子接続用配線１０を引き出し、中継端子９ａにて各電極パッドから引き出された中継端子接続用配線１０を接続することによってカソード電極パッド３とエミッタ電極パッド６とを短絡させる必要がある。従って、半導体装置１の組み立て性が悪くなるという問題があった。
　本発明は、上記の問題を解決するためになされたものであり、以下に詳細に説明する。
　＜実施の形態１＞
　図１は、本発明の実施の形態１による半導体装置１の構成の一例を示す平面図である。また、図２は、図１のＡ－Ａ断面の一例を示す断面図である。
　図２に示すように、本実施の形態１による半導体装置１は、カソード電極パッド３とエミッタ電極パッド６とを電気的に接続する導電性のカソード・エミッタ接続用配線１９（導電膜）を設けることを特徴としている。その他の構成は、図７に示す前提技術による半導体装置１と同様であるため、ここでは説明を省略する。
　カソード・エミッタ接続用配線１９は、保護膜１８を覆うように、カソード電極パッド３とエミッタ電極パッド６とを接続（短絡）するように設けられている。すなわち、カソード・エミッタ接続用配線１９は、Ｓｉ基板１３上に配設され、温度センスダイオード２のカソード電極２ａ（一方電極）に接続されたカソード電極パッド３（一方電極パッド）と、エミッタ電極パッド６（主電流電極パッド）とを電気的に接続する。
　なお、カソード・エミッタ接続用配線１９は、例えばアルミニウム膜で形成されてもよく、他の導電性の金属膜で形成されてもよい。
　カソード・エミッタ接続用配線１９を設けることによって、カソード電極パッド３とエミッタ電極パッド６とが同電位となる。従って、図１に示すように、カソード電極パッド３と中継端子９ａとを接続する中継端子接続用配線１０が不要になる。
　図３は、図１のＢ－Ｂ断面の一例を示す断面図である。
　図３に示すように、ゲート電極パッド７は、ゲートメタル配線１６と直接接続されている。
　また、トレンチ８にはドープドポリシリコン１５が充填されており、ドープドポリシリコン１５はゲートメタル配線１６に接続されている（すなわち、トレンチゲートを構成している）。
　以上のことから、本実施の形態１によれば、半導体装置１の内部でカソード電極パッド３とエミッタ電極パッド６とを短絡することができる。従って、カソード電極パッド３と中継端子９ａとを接続する中継端子接続用配線１０が不要になるため、半導体装置１の組み立て性の向上および小型化が可能となる。
　また、Ｓｉ基板１３が両面はんだ付け対応（Ｓｉ基板１３の表面および裏面に対してはんだ付け可能）である場合において、エミッタ電極パッド６上にはんだと接合可能な金属膜（Front Metal：FM）を形成する際に、当該金属膜をカソード・エミッタ接続用配線１９として形成してもよい。このようにすることによって、金属膜（ＦＭ）とカソード・エミッタ接続用配線１９とを同時に（同一工程で）形成することができるため、新たな工程を追加することなくカソード・エミッタ接続用配線１９を形成することができる。
　＜実施の形態２＞
　図４は、本発明の実施の形態２による半導体装置１の構成の一例を示す断面図であり、図１のＡ－Ａ断面の一例を示している。
　図４に示すように、本実施の形態２による半導体装置１は、カソード電極パッド３とエミッタ電極パッド６とが同一の層で接続して形成されており、カソード電極パッド３とエミッタ電極パッド６と交差する部分におけるゲート配線部１７では、ゲートメタル配線１６（制御電極配線）が分断して形成されていることを特徴としている。すなわち、ゲートメタル配線１６の分断部分では、ドープドポリシリコン１５が連続して形成されている。このような構成とすることによって、カソード電極パッド３とエミッタ電極パッド６とを電気的に接続する導電膜は、ゲートメタル配線１６と同一工程で形成することができる。その他の構成は、実施の形態１（図１～３を参照）と同様であるため、ここでは説明を省略する。
　以上のことから、本実施の形態２によれば、実施の形態１による効果に加えて、カソード電極パッド３とエミッタ電極パッド６とを電気的に接続する導電膜を同一工程で形成するため、新たな製造工程を追加することなくカソード電極パッド３とエミッタ電極パッド６とを短絡させることができる。
　また、図５において、カソード・エミッタ接続部２０を図４に示すような構成とすることによって、カソード配線４ａとカソード電極パッド３およびエミッタ電極パッド６とを直接的に接続するようにしてもよい。すなわち、カソード電極パッド３とエミッタ電極パッド６とを電気的に接続する導電膜は、図１に示すような温度センスダイオード２のカソード電極パッド３を介することなく、温度センスダイオード２のカソード電極２ａとエミッタ電極パッド６とを電気的に接続する。ここで、カソード・エミッタ接続部２０は、カソード配線４ａとエミッタ電極パッド６とが接続されている部分を示す。このような構成とすることによって、カソード電極パッド３を省略することができ、半導体装置１における有効面積を拡大することができる。
　また、図５のような構成とするときは、図６に示すように、温度センスダイオード２のアノード電極パッド５（他方電極パッド）を半導体基板上の周縁部に配設し、温度センスダイオード２を半導体基板上の中央部に形成するようにしても上記と同様の効果が得られる。なお、アノード電極パッド５の位置は任意に変更してもよい。これにより、設計の自由度が向上する。
　なお、本発明は、その発明の範囲内において、実施の形態を適宜、変形、省略することが可能である。
　この発明は詳細に説明されたが、上記した説明は、すべての態様において、例示であって、この発明がそれに限定されるものではない。例示されていない無数の変形例が、この発明の範囲から外れることなく想定され得るものと解される。
　１　半導体装置、２　温度センスダイオード、２ａ　カソード電極、２ｂ　アノード電極、３　カソード電極パッド、４ａ　カソード配線、４ｂ　アノード配線、５　アノード電極パッド、６　エミッタ電極パッド、７　ゲート電極パッド、８　トレンチ、９　端子部、９ａ　中継端子、１０　中継端子接続用配線、１１　Ｎ－層、１２　Ｐ層、１３　Ｓｉ基板、１４　絶縁膜、１５　ドープドポリシリコン、１６　ゲートメタル配線、１７　ゲート配線部、１８　保護膜、１９　カソード・エミッタ接続用配線、２０　カソード・エミッタ接続部。

Claims (6)

  1. 　半導体基板に形成されたスイッチング素子と、
    　前記半導体基板に形成された温度センスダイオードと、
    　前記半導体基板上に配設された前記スイッチング素子の主電流電極パッドと、
    　前記半導体基板上に配設され、前記温度センスダイオードの一方電極と前記主電流電極パッドとを電気的に接続する導電膜と、
    を備える、半導体装置。
  2. 　前記半導体基板上に配設された前記温度センスダイオードの一方電極パッドをさらに備え、
    　前記導電膜は、前記一方電極パッドと前記主電流電極パッドとを電気的に接続することを特徴とする、請求項１に記載の半導体装置。
  3. 　前記導電膜は、前記温度センスダイオードの一方電極パッドを介することなく、前記温度センスダイオードの一方電極と前記主電流電極パッドとを電気的に接続することを特徴とする、請求項１に記載の半導体装置。
  4. 　前記半導体基板上に配設された前記半導体スイッチング素子の制御電極配線をさらに備え、
    　前記導電膜は、前記制御電極配線と同一工程で形成されることを特徴とする、請求項３に記載の半導体装置。
  5. 　前記半導体基板上の周縁部に配設された前記温度センスダイオードの他方電極パッドをさらに備え、
    　前記温度センスダイオードは、前記半導体基板上の中央部に形成されることを特徴とする、請求項４に記載の半導体装置。
  6. 　前記主電流電極パッド上にはんだと接合可能な金属膜をさらに備え、
    　前記導電膜は、前記金属膜と同一工程で形成されることを特徴とする、請求項１に記載の半導体装置。
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9530766B2 (en) 2013-08-23 2016-12-27 Mitsubishi Electric Corporation Semiconductor device
US20190078941A1 (en) * 2017-09-14 2019-03-14 Macom Technology Solutions Holdings, Inc. Operational temperature determination in bipolar transistors by resistance thermometry
US10637460B2 (en) 2016-06-14 2020-04-28 Macom Technology Solutions Holdings, Inc. Circuits and operating methods thereof for monitoring and protecting a device
WO2020166251A1 (ja) * 2019-02-13 2020-08-20 株式会社デンソー 半導体装置
US10790787B2 (en) 2017-07-24 2020-09-29 Macom Technology Solutions Holdings, Inc. FET operational temperature determination by gate structure resistance thermometry
US10855230B2 (en) 2017-07-24 2020-12-01 Macom Technology Solutions Holdings, Inc. FET operational temperature determination by field plate resistance thermometry
JP2021002683A (ja) * 2020-10-02 2021-01-07 ローム株式会社 半導体装置および半導体モジュール
US11038473B2 (en) 2016-10-14 2021-06-15 Macom Technology Solutions Holdings, Inc. Phase shifters for gallium nitride amplifiers and related methods
US11257812B2 (en) 2015-02-13 2022-02-22 Rohm Co., Ltd. Semiconductor device and semiconductor module

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7013668B2 (ja) * 2017-04-06 2022-02-01 富士電機株式会社 半導体装置
JP6819540B2 (ja) * 2017-10-23 2021-01-27 三菱電機株式会社 半導体装置
CN109786367B (zh) * 2019-01-31 2024-04-05 惠州市忠邦电子有限公司 一种具有内部集成温度保护装置的Mosfet半导体器件

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007059882A (ja) * 2005-07-28 2007-03-08 Matsushita Electric Ind Co Ltd 半導体装置
JP2007287919A (ja) * 2006-04-17 2007-11-01 Toyota Industries Corp 温度検出機能付き半導体装置

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL8402023A (nl) * 1984-06-27 1986-01-16 Philips Nv Halfgeleiderinrichting met een niet-vluchtige geheugentransistor.
JP3008900B2 (ja) 1985-11-29 2000-02-14 株式会社デンソー 半導体装置
JPH07153920A (ja) * 1993-11-30 1995-06-16 Nec Corp 半導体装置
JP3062029B2 (ja) * 1995-01-31 2000-07-10 日本電気株式会社 ダイオードの順電圧を利用した温度検知方法
JP4846106B2 (ja) * 2001-02-16 2011-12-28 三菱電機株式会社 電界効果型半導体装置及びその製造方法
JP4270788B2 (ja) 2002-01-15 2009-06-03 三洋電機株式会社 半導体装置およびその製造方法
JP2003229460A (ja) 2002-02-05 2003-08-15 Sanyo Electric Co Ltd Ｍｏｓｆｅｔおよびその製造方法
KR100416614B1 (ko) * 2002-03-20 2004-02-05 삼성전자주식회사 본딩패드 하부구조를 보강하기 위한 반도체 소자 및 그제조방법
JP4073876B2 (ja) 2004-01-14 2008-04-09 三菱電機株式会社 半導体装置
US7470958B2 (en) * 2005-07-28 2008-12-30 Panasonic Corporation Semiconductor device
JP5157247B2 (ja) * 2006-10-30 2013-03-06 三菱電機株式会社 電力半導体装置
JP2008130983A (ja) 2006-11-24 2008-06-05 Nec Electronics Corp 半導体装置およびその製造方法
US8278749B2 (en) * 2009-01-30 2012-10-02 Infineon Technologies Ag Integrated antennas in wafer level package
US8912646B2 (en) * 2009-07-15 2014-12-16 Silanna Semiconductor U.S.A., Inc. Integrated circuit assembly and method of making
JP2011096699A (ja) 2009-10-27 2011-05-12 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP4811827B2 (ja) 2010-02-08 2011-11-09 ルネサスエレクトロニクス株式会社 半導体装置
JP5601863B2 (ja) * 2010-03-29 2014-10-08 三菱電機株式会社 電力半導体装置
JP5745974B2 (ja) 2011-09-05 2015-07-08 三菱電機株式会社 半導体装置およびその製造方法
CN102881679B (zh) * 2012-09-24 2015-04-15 株洲南车时代电气股份有限公司 一种集成了温度和电流传感功能的igbt芯片
US9337163B2 (en) * 2012-11-13 2016-05-10 General Electric Company Low profile surface mount package with isolated tab
US20140183744A1 (en) * 2012-12-28 2014-07-03 Texas Instruments Incorporated Package substrate with bondable traces having different lead finishes
JP6065979B2 (ja) 2013-08-23 2017-01-25 三菱電機株式会社 半導体装置
US9704781B2 (en) * 2013-11-19 2017-07-11 Micron Technology, Inc. Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods
US9123626B1 (en) * 2014-02-27 2015-09-01 Texas Instruments Incorporated Integrated passive flip chip package
US20150340305A1 (en) * 2014-05-20 2015-11-26 Freescale Semiconductor, Inc. Stacked die package with redistribution layer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007059882A (ja) * 2005-07-28 2007-03-08 Matsushita Electric Ind Co Ltd 半導体装置
JP2007287919A (ja) * 2006-04-17 2007-11-01 Toyota Industries Corp 温度検出機能付き半導体装置

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9530766B2 (en) 2013-08-23 2016-12-27 Mitsubishi Electric Corporation Semiconductor device
US11916069B2 (en) 2015-02-13 2024-02-27 Rohm Co., Ltd. Semiconductor device and semiconductor module
US11670633B2 (en) 2015-02-13 2023-06-06 Rohm Co., Ltd. Semiconductor device and semiconductor module
US11495595B2 (en) 2015-02-13 2022-11-08 Rohm Co., Ltd. Semiconductor device and semiconductor module
US11257812B2 (en) 2015-02-13 2022-02-22 Rohm Co., Ltd. Semiconductor device and semiconductor module
US10637460B2 (en) 2016-06-14 2020-04-28 Macom Technology Solutions Holdings, Inc. Circuits and operating methods thereof for monitoring and protecting a device
US11728805B2 (en) 2016-06-14 2023-08-15 Macom Technology Solutions Holdings, Inc. Circuits and operating methods thereof for monitoring and protecting a device
US11038473B2 (en) 2016-10-14 2021-06-15 Macom Technology Solutions Holdings, Inc. Phase shifters for gallium nitride amplifiers and related methods
US10855230B2 (en) 2017-07-24 2020-12-01 Macom Technology Solutions Holdings, Inc. FET operational temperature determination by field plate resistance thermometry
US10790787B2 (en) 2017-07-24 2020-09-29 Macom Technology Solutions Holdings, Inc. FET operational temperature determination by gate structure resistance thermometry
US20190078941A1 (en) * 2017-09-14 2019-03-14 Macom Technology Solutions Holdings, Inc. Operational temperature determination in bipolar transistors by resistance thermometry
JP7103256B2 (ja) 2019-02-13 2022-07-20 株式会社デンソー 半導体装置
JP2020136315A (ja) * 2019-02-13 2020-08-31 株式会社デンソー 半導体装置
WO2020166251A1 (ja) * 2019-02-13 2020-08-20 株式会社デンソー 半導体装置
JP2021002683A (ja) * 2020-10-02 2021-01-07 ローム株式会社 半導体装置および半導体モジュール
JP7001785B2 (ja) 2020-10-02 2022-01-20 ローム株式会社 半導体装置および半導体モジュール

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