JPS6387761A - ガリウム砒素集積回路のｍｉｍ容量 - Google Patents

ガリウム砒素集積回路のｍｉｍ容量

Info

Publication number
JPS6387761A
JPS6387761A JP23361586A JP23361586A JPS6387761A JP S6387761 A JPS6387761 A JP S6387761A JP 23361586 A JP23361586 A JP 23361586A JP 23361586 A JP23361586 A JP 23361586A JP S6387761 A JPS6387761 A JP S6387761A
Authority
JP
Japan
Prior art keywords
gallium arsenide
insulating film
capacitance
mim
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23361586A
Other languages
English (en)
Other versions
JPH0573273B2 (ja
Inventor
Yuji Hara
原　雄二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP23361586A priority Critical patent/JPS6387761A/ja
Publication of JPS6387761A publication Critical patent/JPS6387761A/ja
Publication of JPH0573273B2 publication Critical patent/JPH0573273B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はガリウム砒素集積回路のＭＩＭ容量に関する。
〔従来の技術〕
ＭＩＭ容量は配線金属を容量の両電極として使用し、こ
れら両電極間に絶縁膜をはさみ込むことにより容量とし
ているが、従来、ガリウム砒素集積回路に用いられてい
たＭＩＭ容量はガリウム砒素基板の平坦部分に形成され
ていた。
〔発明が解決しようとする問題点〕
容量の容量値は電極の対向面積に比例し、電極間の距離
に反比例するため、容量値を大きくするには、電極の面
積を大きくするか、電極間の絶縁膜−を薄くすればよい
が、電極の面積の増大はチップ面積の増大になり、絶縁
膜を薄くすれば、ピンホールが発生しやすくなり信頼性
が低下する。そのため、従来のガリウム砒素集積回路の
ＭＩＭ容量は小面積で大きい容量値を得ることができな
いという欠点がある。
〔問題点を解決するための手段〕
本発明のガリウム砒素集積回路のＭＩＭ容量は、ガリウ
ム砒素基板上に成長し不要部分を除去して段差を設けた
絶縁膜と、この絶縁膜をマスクにして異方性エツチング
を施して前記ガリウム砒素基板に設けた窪みとの上に形
成されている。
〔実施例〕
次に、図面を参照して本発明について説明する。
第１図は本発明の一実施例の縦断面図である。
１はガリウム砒素基板２上に成長した絶縁膜であり、不
要部分を除去して段差を設けである。ガリウム砒素基板
２に、は絶縁膜１をマスクにしてウェットで異方性エツ
チングを施してＶ字型の溝がつくられている。３・５は
それぞれ容量の下側と上側との電極であり、配線金属に
用いて形成する。
４は容量（こ用いる絶縁膜である。
〔発明の効果〕
以上説明したように本発明は、ガリウム砒素基板上に成
長した絶縁膜の不要部分を除去して段差を設け、この絶
縁膜とこの絶縁膜をマスクにして異方性エツチングを施
してガリウム砒素基板に設けた窪みとの上にＭＩＭ容量
を形成することにより、従来のＭＩＭ容量より大きな電
極の対向面積を得ることができるので、小面積で大きい
容量値を得ることができる効果がある。
【図面の簡単な説明】
第１図は本発明の一実施例の縦断面図である。 １・・・・・・絶縁膜、２・・・・・・ガリウム砒素基
板、３・・・・・・下側の電極、４・・・・・・絶縁膜
、５・・・・・・上側の電極。

Claims (1)

    【特許請求の範囲】
  1. 　ガリウム砒素基板上に成長し不要部分を除去して段差
    を設けた絶縁膜と、この絶縁膜をマスクにして異方性エ
    ッチングを施して前記ガリウム砒素基板に設けた窪みと
    の上に形成したことを特徴とするガリウム砒素集積回路
    のＭＩＭ容量。
JP23361586A 1986-09-30 1986-09-30 ガリウム砒素集積回路のｍｉｍ容量 Granted JPS6387761A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23361586A JPS6387761A (ja) 1986-09-30 1986-09-30 ガリウム砒素集積回路のｍｉｍ容量

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23361586A JPS6387761A (ja) 1986-09-30 1986-09-30 ガリウム砒素集積回路のｍｉｍ容量

Publications (2)

Publication Number Publication Date
JPS6387761A true JPS6387761A (ja) 1988-04-19
JPH0573273B2 JPH0573273B2 (ja) 1993-10-14

Family

ID=16957820

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23361586A Granted JPS6387761A (ja) 1986-09-30 1986-09-30 ガリウム砒素集積回路のｍｉｍ容量

Country Status (1)

Country Link
JP (1) JPS6387761A (ja)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6251740B1 (en) 1998-12-23 2001-06-26 Lsi Logic Corporation Method of forming and electrically connecting a vertical interdigitated metal-insulator-metal capacitor extending between interconnect layers in an integrated circuit
US6341056B1 (en) 2000-05-17 2002-01-22 Lsi Logic Corporation Capacitor with multiple-component dielectric and method of fabricating same
US6342734B1 (en) 2000-04-27 2002-01-29 Lsi Logic Corporation Interconnect-integrated metal-insulator-metal capacitor and method of fabricating same
US6417535B1 (en) * 1998-12-23 2002-07-09 Lsi Logic Corporation Vertical interdigitated metal-insulator-metal capacitor for an integrated circuit
US6441419B1 (en) 1998-03-31 2002-08-27 Lsi Logic Corporation Encapsulated-metal vertical-interdigitated capacitor and damascene method of manufacturing same
US6504202B1 (en) 2000-02-02 2003-01-07 Lsi Logic Corporation Interconnect-embedded metal-insulator-metal capacitor
US6566186B1 (en) 2000-05-17 2003-05-20 Lsi Logic Corporation Capacitor with stoichiometrically adjusted dielectric and method of fabricating same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6066851A (ja) * 1983-09-22 1985-04-17 Oki Electric Ind Co Ltd 集積回路用コンデンサ及びその製造方法
JPS60178659A (ja) * 1984-02-24 1985-09-12 Toshiba Corp 半導体装置およびその製造方法
JPS6136965A (ja) * 1984-07-30 1986-02-21 Toshiba Corp 半導体メモリ装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6066851A (ja) * 1983-09-22 1985-04-17 Oki Electric Ind Co Ltd 集積回路用コンデンサ及びその製造方法
JPS60178659A (ja) * 1984-02-24 1985-09-12 Toshiba Corp 半導体装置およびその製造方法
JPS6136965A (ja) * 1984-07-30 1986-02-21 Toshiba Corp 半導体メモリ装置

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6441419B1 (en) 1998-03-31 2002-08-27 Lsi Logic Corporation Encapsulated-metal vertical-interdigitated capacitor and damascene method of manufacturing same
US6251740B1 (en) 1998-12-23 2001-06-26 Lsi Logic Corporation Method of forming and electrically connecting a vertical interdigitated metal-insulator-metal capacitor extending between interconnect layers in an integrated circuit
US6417535B1 (en) * 1998-12-23 2002-07-09 Lsi Logic Corporation Vertical interdigitated metal-insulator-metal capacitor for an integrated circuit
US6504202B1 (en) 2000-02-02 2003-01-07 Lsi Logic Corporation Interconnect-embedded metal-insulator-metal capacitor
US6342734B1 (en) 2000-04-27 2002-01-29 Lsi Logic Corporation Interconnect-integrated metal-insulator-metal capacitor and method of fabricating same
US6341056B1 (en) 2000-05-17 2002-01-22 Lsi Logic Corporation Capacitor with multiple-component dielectric and method of fabricating same
US6566186B1 (en) 2000-05-17 2003-05-20 Lsi Logic Corporation Capacitor with stoichiometrically adjusted dielectric and method of fabricating same

Also Published As

Publication number Publication date
JPH0573273B2 (ja) 1993-10-14

Similar Documents

Publication Publication Date Title
KR960026873A (ko) 집적회로. 집적회로용 캐패시터 및 캐패시터 제조 방법
JPS6387761A (ja) ガリウム砒素集積回路のｍｉｍ容量
KR950004516A (ko) 반도체 기억장치의 제조방법
KR980005441A (ko) 반도체 소자의 제조 방법
KR970059797A (ko) 액정표시장치의 제조방법
JPH0247862A (ja) 半導体集積回路装置
JPS61187278A (ja) 半導体装置
JPH0547446Y2 (ja)
KR950026042A (ko) 적층 캐패시터 제조방법
KR0151263B1 (ko) 반도체 메모리 소자의 커패시터 제조방법
JPH0419809Y2 (ja)
JPS61170057A (ja) 縦型キヤパシタ−
JPH0113405Y2 (ja)
KR980003738A (ko) 액정표시장치의 스토리지 캐패시터와 그 제조방법
JPS6381842A (ja) 半導体装置の製造方法
JPH03175486A (ja) 薄膜トランジスタ基板
JPS63204742A (ja) 半導体装置の製造方法
JPS61198660A (ja) 半導体集積回路のｍｉｍ容量
JPS6320105Y2 (ja)
KR100225848B1 (ko) 커패시터 및 커패시터의 제조 방법
JPS63299157A (ja) 容量素子
JPH04179127A (ja) 半導体装置
KR880008449A (ko) 디램의쎌캐패시터의 제조방법
JPH02119170A (ja) 半導体装置の製造方法
KR920013703A (ko) 고용량의 캐패시턴스를 갖는 반도제 장치 및 그 제조방법