JPS63164249U - - Google Patents

Info

Publication number
JPS63164249U
JPS63164249U JP1987074267U JP7426787U JPS63164249U JP S63164249 U JPS63164249 U JP S63164249U JP 1987074267 U JP1987074267 U JP 1987074267U JP 7426787 U JP7426787 U JP 7426787U JP S63164249 U JPS63164249 U JP S63164249U
Authority
JP
Japan
Prior art keywords
type
field effect
effect transistor
mos field
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987074267U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS63164249U publication Critical patent/JPS63164249U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0883—Combination of depletion and enhancement field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type
    • H03K19/09443—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors
    • H03K19/09445—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors with active depletion transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Memories (AREA)

Description

【図面の簡単な説明】
添付図面の第１図、第２図および第３図はこの
考案による集積回路装置の一部分を、好ましい製
造方法の各段階にて例示している概略断面図、第
４図および第５図はこの考案の回路応用を例示し
ている図である。 １０……集積回路装置、１２……基板、１４…
…フイールド酸化物、１６……ゲート酸化物層、
１８……ホトレジスタマスク、２０，２２，２４
……Ｎ形領域、２６……ソース領域、２８……ド
レイン領域、３０……ゲート、３１，３２，３３
，３４……チヤネル、３６，３８……電極、４０
……ゲート電極、４２……絶縁層、１００……イ
ンバータ回路、Ｑ１，Ｑ２……トランジスタ、１
０２……出力端子、１０４……入力端子、１１０
……ブツシユプルバツフア回路、Ａ，Ｂ，Ｃ，Ｄ
……トランジスタ、１１２……入力端子、１１４
，１１６……出力端子。

Claims (1)

  1. 【実用新案登録請求の範囲】 (1) 第１の導電型の単一の半導体基板上に複数
    のＭＯＳ電界効果トランジスタを有するインバー
    タ回路を含んだ集積回路を製造する方法であつて
    、 複数のトランジスタ場所に半導体材料本体を準
    備し、 第１、第２、第３及び第４の場所群を同定し、 イオンインプランテーシヨンに対して前記第２
    及び第４の場所群を選択的にマスキングし、前記
    第１及び第３の場所群はマスクせずに残し、 導電性変更物質のイオン源に対して前記半導体
    材料の最初の露出を行つて、前記第１及び第３の
    場所群に前記イオンを植え込み、 イオンインプランテーシヨンに対して前記第１
    及び第４の場所群を選択的にマスキングし、前記
    第２及び第３の場所群はマスクせずに残し、 導電性変更物質のイオン源に対して前記半導体
    材料の２回目の露出を行つて、前記第２及び第３
    の場所群にイオンを植え込み、 各場所に１つのＭＯＳ電界効果トランジスタを
    形成し、それによりしきい値電圧が異なることに
    よつて区別される４つの異なる形式のＭＯＳ電界
    効果トランジスタがそれぞれ４つの場所群の１つ
    に対応して形成され、 前記第１の形式のＭＯＳ電界効果トランジスタ
    のドレインからドレイン電圧への接続を形成し、
    かつ前記第１の形式の前記ＭＯＳ電界効果トラン
    ジスタのソースから出力端子への接続を形成し、 前記第２の形式のＭＯＳ電界効果トランジスタ
    のドレインからドレイン電圧への接続を形成し、
    かつ前記第２の形式の前記ＭＯＳ電界効果トラン
    ジスタのソースから、そのそれぞれのゲート及び
    前記第１の形式の前記ＭＯＳ電界効果トランジス
    タのゲートへの接続を形成し、 前記第４の形式の第１のＭＯＳ電界効果トラン
    ジスタのドレインから、前記第１の形式の前記Ｍ
    ＯＳ電界効果トランジスタのソースへの接続を形
    成し、かつ前記第４の形式の前記第１のＭＯＳ電
    界効果トランジスタのソースから、ソース電圧へ
    の接続を形成し、そして 前記第４の形式の第２のＭＯＳ電界効果トラン
    ジスタのドレインから、前記第２の形式の前記Ｍ
    ＯＳ電界効果トランジスタのソースへの接続を形
    成し、前記第４の形式の前記第２のＭＯＳ電界効
    果トランジスタのソースから、ソース電圧への接
    続を形成し、さらに、前記第４の形式の前記第２
    のＭＯＳ電界効果トランジスタのゲートから、前
    記第４の形式の前記ＭＯＳ電界効果トランジスタ
    のゲート及び入力端子への接続を形成する、 ようにした集積回路を製造する方法。 (2) 前記半導体材料の前記最初の露出を行う際
    の前記イオン源を選択すると共に、第２の導電型
    のものであるべき半導体材料の前記２回目の露出
    を行う際の前記イオン源を選択し、そして半導体
    材料の前記最初の露出を行う際のイオンの照射量
    を、半導体材料の前記２回目の露出を行う際のイ
    オンの照射量とは異なるように選定する実用新案
    登録請求の範囲第１項記載の集積回路を製造する
    方法。 (3) 出発半導体材料はＰ型導電型であるように
    選択され、イオンはＮ型物質のものであるように
    選択され、デプリーシヨン形ＭＯＳ電界効果トラ
    ンジスタのチヤンネルにおける半導体材料をＰ型
    導電型からＮ型導電型に変換するに充分であるよ
    うに、イオン植え込み照射を行うことによつて、
    デプリーシヨン形ＭＯＳ電界効果トランジスタが
    形成される実用新案登録請求の範囲第２項記載の
    集積回路を製造する方法。 (4) 前記第１の場所に対するイオン照射量は、
    ２．４ボルトから０ボルトの範囲にあるしきい値
    電圧を有するわずかにデプリーシヨン形である領
    域を形成するように調整され、前記第２の場所に
    対するイオン照射量は、２．４ボルトから４．３
    ボルトの範囲にあるしきい値電圧を有する標準の
    デプリーシヨン形である領域を形成するように調
    整され、前記第３の場所に対するイオン照射量は
    、４．３ボルトから５．３ボルトの範囲にあるし
    きい値電圧を有する高いデプリーシヨン形の領域
    を形成するように調整され、そして前記第４の場
    所は、０ボルトから１．５ボルトの範囲にあるし
    きい値電圧を有する標準のエンハンスメント形の
    領域を形成するように調整される実用新案登録請
    求の範囲第３項記載の集積回路を製造する方法。
JP1987074267U 1977-07-18 1987-05-18 Pending JPS63164249U (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/816,363 US4135102A (en) 1977-07-18 1977-07-18 High performance inverter circuits

Publications (1)

Publication Number Publication Date
JPS63164249U true JPS63164249U (ja) 1988-10-26

Family

ID=25220399

Family Applications (4)

Application Number Title Priority Date Filing Date
JP8760778A Pending JPS5496383A (en) 1977-07-18 1978-07-18 High performance ic and method of fabricating same
JP1982113491U Granted JPS58103153U (ja) 1977-07-18 1982-07-28 ２進論理信号を反転するための集積回路
JP1987074267U Pending JPS63164249U (ja) 1977-07-18 1987-05-18
JP3083041A Expired - Lifetime JPH0795564B2 (ja) 1977-07-18 1991-03-25 集積回路を製造する方法

Family Applications Before (2)

Application Number Title Priority Date Filing Date
JP8760778A Pending JPS5496383A (en) 1977-07-18 1978-07-18 High performance ic and method of fabricating same
JP1982113491U Granted JPS58103153U (ja) 1977-07-18 1982-07-28 ２進論理信号を反転するための集積回路

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP3083041A Expired - Lifetime JPH0795564B2 (ja) 1977-07-18 1991-03-25 集積回路を製造する方法

Country Status (6)

Country Link
US (1) US4135102A (ja)
JP (4) JPS5496383A (ja)
DE (1) DE2831522A1 (ja)
FR (1) FR2398388A1 (ja)
GB (1) GB2001197B (ja)
IT (1) IT1097846B (ja)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5443551A (en) * 1977-09-14 1979-04-06 Hitachi Ltd Monolithic semiconductor integrated circuit
US4417162A (en) * 1979-01-11 1983-11-22 Bell Telephone Laboratories, Incorporated Tri-state logic buffer circuit
WO1980001528A1 (en) * 1979-01-11 1980-07-24 Western Electric Co Tri-state logic buffer circuit
DE3016050C2 (de) * 1980-04-25 1985-08-29 Siemens AG, 1000 Berlin und 8000 München Verfahren zur Herstellung von Fotolackstrukturen für integrierte Halbleiterschaltungsanordnungen
JPS639885B2 (ja) * 1980-12-05 1988-03-02 Gni Pi Splavov Tsvet Metall
US4491748A (en) * 1981-04-16 1985-01-01 International Business Machines Corporation High performance FET driver circuit
US4409501A (en) * 1981-07-20 1983-10-11 Motorola Inc. Power-on reset circuit
IT1201859B (it) * 1986-12-10 1989-02-02 Sgs Microelettronica Spa Circuito logico cmos
JP2819302B2 (ja) * 1989-04-26 1998-10-30 富士通株式会社 半導体装置の製造方法
JPH02153574A (ja) * 1989-05-24 1990-06-13 Hitachi Ltd 半導体集積回路装置の製造法
JPH04211517A (ja) * 1990-03-19 1992-08-03 Toshiba Corp 電界効果トランジスタ回路
JP3361874B2 (ja) * 1994-02-28 2003-01-07 三菱電機株式会社 電界効果型半導体装置
JP2000124325A (ja) * 1998-10-16 2000-04-28 Nec Corp 半導体装置およびその製造方法
JP2007281027A (ja) * 2006-04-03 2007-10-25 Renesas Technology Corp 半導体装置とその製造方法
KR101539667B1 (ko) * 2008-06-18 2015-07-28 삼성전자주식회사 인버터 소자 및 그 동작 방법
US8791738B2 (en) * 2011-08-19 2014-07-29 Marvell World Trade Ltd. Start-up circuit
JP6713647B2 (ja) * 2016-05-10 2020-06-24 国立大学法人広島大学 炭化珪素半導体装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5211199B1 (ja) * 1970-05-27 1977-03-29
JPS4860583A (ja) * 1971-11-26 1973-08-24
US3775693A (en) * 1971-11-29 1973-11-27 Moskek Co Mosfet logic inverter for integrated circuits
JPS4979182A (ja) * 1972-12-04 1974-07-31
JPS5631744B2 (ja) * 1972-12-04 1981-07-23
US3851189A (en) * 1973-06-25 1974-11-26 Hughes Aircraft Co Bisitable digital circuitry
US3898105A (en) * 1973-10-25 1975-08-05 Mostek Corp Method for making FET circuits
DE2356446A1 (de) * 1973-11-12 1975-05-28 Licentia Gmbh Integrierte schaltung mit feldeffekttransistoren
US3868274A (en) * 1974-01-02 1975-02-25 Gen Instrument Corp Method for fabricating MOS devices with a multiplicity of thresholds on a semiconductor substrate
US3913026A (en) * 1974-04-08 1975-10-14 Bulova Watch Co Inc Mos transistor gain block
US3969633A (en) * 1975-01-08 1976-07-13 Mostek Corporation Self-biased trinary input circuit for MOSFET integrated circuit
JPS5198938A (ja) * 1975-02-26 1976-08-31
JPS51102581A (ja) * 1975-03-07 1976-09-10 Sanyo Electric Co
US3995172A (en) * 1975-06-05 1976-11-30 International Business Machines Corporation Enhancement-and depletion-type field effect transistors connected in parallel

Also Published As

Publication number Publication date
JPS5496383A (en) 1979-07-30
DE2831522A1 (de) 1979-02-01
JPH0795564B2 (ja) 1995-10-11
DE2831522C2 (ja) 1991-06-06
JPH05267598A (ja) 1993-10-15
GB2001197B (en) 1982-05-26
JPH0210678Y2 (ja) 1990-03-16
IT7825818A0 (it) 1978-07-17
JPS58103153U (ja) 1983-07-13
FR2398388B1 (ja) 1984-11-16
FR2398388A1 (fr) 1979-02-16
GB2001197A (en) 1979-01-24
IT1097846B (it) 1985-08-31
US4135102A (en) 1979-01-16

Similar Documents

Publication Publication Date Title
JPS63164249U (ja)
US4472871A (en) Method of making a plurality of MOSFETs having different threshold voltages
JP3470133B2 (ja) 半導体装置の製造方法
Plummer et al. A monolithic 200-V CMOS analog switch
KR960036093A (ko) 플래쉬 이이피롬 셀 및 그 제조방법
GB1447236A (en) Methods of manufacturing integrated circuits including field effect transistors
JPS6225452A (ja) Ｃｍｏｓトランジスタの製造法
TW466704B (en) Integrated circuit
JPS55148466A (en) Cmos semiconductor device and its manufacture
JPS604596B2 (ja) 相補形ｍｏｓ集積回路の製造方法
JP2000183306A (ja) 半導体記憶装置
JPS62293767A (ja) 半導体集積回路
JPH05206387A (ja) 半導体集積回路
JPS5583265A (en) Semiconductor device and method of fabricating the same
JPH03155156A (ja) 半導体装置の製造方法
JPS61131476A (ja) 半導体装置
JPH0487660U (ja)
JPS5552267A (en) Semiconductor meomory
JPH03155157A (ja) 半導体装置の製造方法
JPS63164313A (ja) 半導体装置の製造方法
JPS6418262A (en) Depletion mode metal-oxide semiconductor device
JP3162937B2 (ja) Ｃｍｏｓ半導体装置の製造方法
JPH01123457A (ja) 半導体装置の製造方法
JPH05218437A (ja) 縦型ｍｏｓ電界効果トランジスタ
JPH02122315A (ja) 半導体装置