JPS5552267A - Semiconductor meomory - Google Patents

Semiconductor meomory

Info

Publication number
JPS5552267A
JPS5552267A JP12490478A JP12490478A JPS5552267A JP S5552267 A JPS5552267 A JP S5552267A JP 12490478 A JP12490478 A JP 12490478A JP 12490478 A JP12490478 A JP 12490478A JP S5552267 A JPS5552267 A JP S5552267A
Authority
JP
Japan
Prior art keywords
layer
diffusion
channel
substrate
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12490478A
Other languages
Japanese (ja)
Other versions
JPS6320023B2 (en
Inventor
Shinji Morozumi
Tatsuji Asakawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP12490478A priority Critical patent/JPS5552267A/en
Publication of JPS5552267A publication Critical patent/JPS5552267A/en
Publication of JPS6320023B2 publication Critical patent/JPS6320023B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0925Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising an N-well only in the substrate

Abstract

PURPOSE:To improve the degree of integration while maintaining the low power operation of a CMOS by realizing the role of load by depletion layer control at low power and at high speeds. CONSTITUTION:A P<-->-epitaxial layer 22 is formed on an N<+>-substrate 21. Next, the diffused layer of an N<->-part 24 for P-channel transistors and a P<->-part 23 is formed. The P<->-part which forms the substrate of an N-channel is biased to the ground potential GND through a P<+>-diffusion 25. The entire substrate is biased to positive potential VDD through an N<+>-diffusion 33. A MOS transistor is formed by N<+>-diffusion layers 29 and 30 which become a source and a drain on the N-channel side, P<+>-diffusion layers 31 and 32 on the P-channel side, gate oxide films 35 and 36, and gate electrodes 38 and 39. A device is formed of the N<+>-diffusion layers 28, 29, 30 and 33 which form the source and the drain, an N<+>-diffusion layer 26 formed at the same time and an N<+>-diffusion layer 27 formed deeper than the layer 26. A gate film 34 and a gate electrode 37 control the conductive layer of the N-channel.
JP12490478A 1978-10-11 1978-10-11 Semiconductor meomory Granted JPS5552267A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12490478A JPS5552267A (en) 1978-10-11 1978-10-11 Semiconductor meomory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12490478A JPS5552267A (en) 1978-10-11 1978-10-11 Semiconductor meomory

Publications (2)

Publication Number Publication Date
JPS5552267A true JPS5552267A (en) 1980-04-16
JPS6320023B2 JPS6320023B2 (en) 1988-04-26

Family

ID=14896978

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12490478A Granted JPS5552267A (en) 1978-10-11 1978-10-11 Semiconductor meomory

Country Status (1)

Country Link
JP (1) JPS5552267A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6088458A (en) * 1983-10-20 1985-05-18 Toshiba Corp Semiconductor memory device
JPS6187361A (en) * 1984-08-22 1986-05-02 ナ−ムロ−ゼ フエンノ−トチヤツプ フイリツプス グロエイラムペンフアブリ−ケン Cmosram having combined bipolar transistor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5226179A (en) * 1975-08-22 1977-02-26 Seiko Epson Corp Semi-conductor unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5226179A (en) * 1975-08-22 1977-02-26 Seiko Epson Corp Semi-conductor unit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6088458A (en) * 1983-10-20 1985-05-18 Toshiba Corp Semiconductor memory device
JPH0582064B2 (en) * 1983-10-20 1993-11-17 Tokyo Shibaura Electric Co
JPS6187361A (en) * 1984-08-22 1986-05-02 ナ−ムロ−ゼ フエンノ−トチヤツプ フイリツプス グロエイラムペンフアブリ−ケン Cmosram having combined bipolar transistor

Also Published As

Publication number Publication date
JPS6320023B2 (en) 1988-04-26

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