JPS6159360U - - Google Patents

Info

Publication number
JPS6159360U
JPS6159360U JP1985100415U JP10041585U JPS6159360U JP S6159360 U JPS6159360 U JP S6159360U JP 1985100415 U JP1985100415 U JP 1985100415U JP 10041585 U JP10041585 U JP 10041585U JP S6159360 U JPS6159360 U JP S6159360U
Authority
JP
Japan
Prior art keywords
conductivity type
power supply
supply node
memory cell
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1985100415U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS6159360U publication Critical patent/JPS6159360U/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H01L27/0738—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors in combination with resistors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)

Description

【図面の簡単な説明】
第１図は本考案に従つて構成されたメモリセル
を使用しているＰＡＭの一部のブロツク回路図、
第２図は第１図のメモリセルの電気回路図、第３
図は第２図の回路の基板上の配置図、第４図は第
３図の−線における立断面図、第５図は本考
案のメモリセルに用いられる負荷インピーダンス
装置におけるゲート相互接続部の実施例の断面図
、第６図は負荷インピーダンス装置の他の実施例
によるゲート相互接続部の断面図、第７Ａ図、第
７Ｂ図、第８Ａ図、第８Ｂ図、第９Ａ図、第９Ｂ
図、第１０Ａ図および第１０Ｂ図は本考案に用い
られる負荷インピーダンス装置の他の実施例の断
面図である。 １，２…データノード、１０…メモリセル、２
０…真性多結晶シリコン半導体層、２２…第１導
電路、２４…第２導電路、２８…真性−外因性接
合、ＤＤ…ドレイン電源ノード、ＳＳ…ソー
ス電源ノード、Ｒ１，Ｒ２…インピーダンス装置
、Ｑ１，Ｑ２，Ｑ３，Ｑ４…絶縁ゲート電界効果
トランジスタ、Ｄ，…相補データバス、ＲＡ１
，ＲＡ２…行アドレス線。

Claims (1)

  1. 【実用新案登録請求の範囲】 (1) ドレイン電源ノードと、ソース電源ノード
    と、第１と第２の相補データ入出力ノードと、第
    １と第２の絶縁ゲート電界効果トランジスタを有
    する集積回路２進メモリセルであつて、前記トラ
    ンジスタのチヤンネルはそれぞれ前記第１と第２
    の相補データ入出力ノードを前記ソース電源ノー
    ドに電気的に接続し、前記第１トランジスタのゲ
    ートが前記第２相補データ入出力ノードに電気的
    に結合され、前記第２トランジスタのゲートが前
    記第１相補データ入出力ノードに電気的に結合さ
    れている前記集積回路２進メモリセルにおいて、
    前記第１、第２相補データノードをそれぞれ前記
    ドレイン電源ノードと電気的に接続する第１と第
    ２のインピーダンス装置をそなえ、各該インピー
    ダンス装置は導電路を画定する実質的に真性な半
    導体材料の基体と、該真性基体の少なくとも１つ
    の区画領域内に配置された外因性導電形不純物の
    ドープ領域を含み、前記真性基体内に少なくとも
    １つの真性−外因性接合が前記外因性ドープ領域
    の境界により画定され、前記各インピーダンス装
    置が少なくともその一部で前記ドレイン電源ノー
    ドから前記相補データ入出力ノードの１つに至る
    直列の電気的通路を形成していることを特徴とす
    る集積回路２進メモリセル。 (2) 実用新案登録請求の範囲第１項において、
    前記ドレイン電源ノードが充電時前記ソース電源
    ノードの電位に対して正の電位を有し、かつ前記
    外因性不純物ドープ領域がＮ導電形であり、前記
    真性半導体材料がＰ導電形であることを特徴とす
    る集積回路２進メモリセル。 (3) 実用新案登録請求の範囲第２項において、
    実質的に真性な半導体材料の前記基体が全体に亘
    りＰ導電形不純物のドープ領域を含み、前記Ｐ導
    電形不純物濃度の大きさがＮ導電形不純物濃度の
    大きさにくらべて小さいことを特徴とする集積回
    路２進メモリセル。 (4) 実用新案登録請求の範囲第１項において、
    前記ドレイン電源ノードが充電時前記ソース電源
    ノードの電位に対して負の電位を有し、前記外因
    性不純物ドープ領域がＰ導電形であり、前記実質
    的真性半導体材料がＮ導電形であることを特徴と
    する集積回路２進メモリセル。 (5) 実用新案登録請求の範囲第４項において、
    前記実質的真性半導体材料の前記基体がその全体
    に亘りＮ導電形不純物のドープ領域を含み、前記
    Ｎ導電形不純物濃度の大きさがＰ導電形不純物濃
    度の大きさにくらべ小さいことを特徴とする集積
    回路２進メモリセル。
JP1985100415U 1976-11-22 1985-07-01 Pending JPS6159360U (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US74381076A 1976-11-22 1976-11-22

Publications (1)

Publication Number Publication Date
JPS6159360U true JPS6159360U (ja) 1986-04-21

Family

ID=24990283

Family Applications (6)

Application Number Title Priority Date Filing Date
JP13978177A Pending JPS5389382A (en) 1976-11-22 1977-11-21 Ic memory and method of producing same
JP57182678A Pending JPS5886763A (ja) 1976-11-22 1982-10-18 半導体インピ−ダンス構造とその製作方法
JP1985060174U Pending JPS60181055U (ja) 1976-11-22 1985-04-22 半導体インピーダンス構造
JP1985100415U Pending JPS6159360U (ja) 1976-11-22 1985-07-01
JP3200925A Expired - Lifetime JP2692439B2 (ja) 1976-11-22 1991-08-09 集積回路２進メモリセル
JP3200909A Expired - Lifetime JP2696110B2 (ja) 1976-11-22 1991-08-09 半導体インピーダンス装置

Family Applications Before (3)

Application Number Title Priority Date Filing Date
JP13978177A Pending JPS5389382A (en) 1976-11-22 1977-11-21 Ic memory and method of producing same
JP57182678A Pending JPS5886763A (ja) 1976-11-22 1982-10-18 半導体インピ−ダンス構造とその製作方法
JP1985060174U Pending JPS60181055U (ja) 1976-11-22 1985-04-22 半導体インピーダンス構造

Family Applications After (2)

Application Number Title Priority Date Filing Date
JP3200925A Expired - Lifetime JP2692439B2 (ja) 1976-11-22 1991-08-09 集積回路２進メモリセル
JP3200909A Expired - Lifetime JP2696110B2 (ja) 1976-11-22 1991-08-09 半導体インピーダンス装置

Country Status (5)

Country Link
JP (6) JPS5389382A (ja)
DE (1) DE2751481C2 (ja)
FR (2) FR2382744A1 (ja)
GB (2) GB1597726A (ja)
IT (1) IT1090938B (ja)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4453175A (en) * 1979-09-19 1984-06-05 Tokyo Shibaura Denki Kabushiki Kaisha MOS Static RAM layout with polysilicon resistors over FET gates
EP0032608A1 (en) * 1980-01-22 1981-07-29 Mostek Corporation Column line powered static ram cell
JPS57130461A (en) * 1981-02-06 1982-08-12 Hitachi Ltd Semiconductor memory storage
US4446613A (en) * 1981-10-19 1984-05-08 Intel Corporation Integrated circuit resistor and method of fabrication
JPS61134054A (ja) * 1984-12-04 1986-06-21 Nec Corp 半導体装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5011644A (ja) * 1973-06-01 1975-02-06

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3576478A (en) * 1969-07-22 1971-04-27 Philco Ford Corp Igfet comprising n-type silicon substrate, silicon oxide gate insulator and p-type polycrystalline silicon gate electrode
GB1318856A (en) * 1971-03-18 1973-05-31 Ferranti Ltd Semiconductor devices
JPS5710578B2 (ja) * 1972-06-20 1982-02-26
GB1391959A (en) * 1972-07-20 1975-04-23 Ferranti Ltd Semiconductor devices
GB1501114A (en) * 1974-04-25 1978-02-15 Rca Corp Method of making a semiconductor device
CH581904A5 (ja) * 1974-08-29 1976-11-15 Centre Electron Horloger
DE2760086C2 (ja) * 1976-07-26 1988-02-18 Hitachi, Ltd., Tokio/Tokyo, Jp

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5011644A (ja) * 1973-06-01 1975-02-06

Also Published As

Publication number Publication date
FR2382771B1 (ja) 1985-04-19
GB1597725A (en) 1981-09-09
DE2751481C2 (de) 1986-10-23
GB1597726A (en) 1981-09-09
FR2382744A1 (fr) 1978-09-29
JPS5886763A (ja) 1983-05-24
JPH06188389A (ja) 1994-07-08
JP2696110B2 (ja) 1998-01-14
FR2382744B1 (ja) 1984-01-06
JP2692439B2 (ja) 1997-12-17
FR2382771A1 (fr) 1978-09-29
IT1090938B (it) 1985-06-26
JPS5389382A (en) 1978-08-05
JPS60181055U (ja) 1985-12-02
JPH0613577A (ja) 1994-01-21
DE2751481A1 (de) 1978-06-08

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