GB1597726A - Extremely low current load device for integrated circuit - Google Patents

Description

PATENT SPECIFICATION

( 11) ( 21) Application No 39787/78 ( 22) Filed 21 No 1977 ( 62) Divided out of No 1597725 1 597 726 ( 19) ( 31) Convention Application No 743810 ( 32) Filed 22 Nov 1976 in ( 33) United States of America (US) ( 44) Complete Specification Published 9 Sep 1981 ( 51) INT CL 3 HO O C 7/00 ( 52) Index at Acceptance H 1 K 1 CA 1 FJ 9 A 9 C 2 9 D 1 9 F 9 N 2 9 N 3 9 R 2 FJ ( 54) EXTREMELY LOW CURRENT LOAD DEVICE FOR INTEGRATED CIRCUIT ( 71) We, MOSTEK CORPORATION, a corporation organised under the laws of the State of Delaware, United States of America, and of 1215 West Crosby Road, Carrollton, Dallas County, Texas, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:This invention relates to a semiconductor structure and a method for the production thereof.

According to the present invention there is provided a semiconductor structure compnsing:

a monocrystalline semiconductor substrate of a first conductivity type starting material, a body of polycrystalline semiconductor material disposed above the substrate, the polycrystalline body being at least partially doped with impurities, including a region of substantially undoped or lightly doped semiconductor material defining a first conductive path and a region of relatively heavily doped semiconductor material defining a second conductive path, the first and second conductive paths defining a series electrical path for the flow of current through the polycrystalline body and defining a junction at the interface of said first and second conductive paths, the first conductive path having a level of impurity doping substantially lower than the level of impurity doping of the second conductive path, the junction being characterised by a substantially differentiated impurity concentration level to achieve a very high direct current impedance.

Preferably the structure includes an insulated gate field effect transistor formed on the substrate, the transistor including source and drain regions of semi-conductor material of a second conductivity type disposed within the substrate and defining a channel region of the first conductivity type in the substrate therebetween, and an insulated gate disposed over the channel region, and wherein the first and second conductive paths are connected to conduct current from a first power supply node through the channel to a second power supply node whenever the channel becomes conductive in response to an electrical potential applied to the gate, the magnitude of the impurity concentration in the first conductive path being substantially less than the magnitude of the impurity concentration in the second conductive path.

The invention also provides a method for producing such a semiconductor structure comprising:

forming a relatively thick oxide layer over portions of the substrate defining a field area; forming a relatively thin oxide layer over portions of the substrate defining an active area; depositing a layer of polycrystalline semiconductor material over the oxide layers; selectively removing portions of the polycrystalline semiconductor layer to define the first and second conductive paths; selectively removing the thin oxide layer from portions of the active area to define the sites of drain and source regions; and selectively doping impurities of the second conductivity type into the portions of the polycrystalline semiconductor layer defining the second conductive path and into the portions of the substrate defining the source and drain regions.

The semiconductor structure of this invention may be used to form a memory cell of a random access memory, and this particular application of the invention will now be described with reference to the accompanying drawings.

CA 1 597 726 Figure 1 is a block circuit diagram of a portion of a random access memory which utilizes a memory cell constructed according to the teachings of the present invention; Figure 2 is an electrical circuit diagram of the memory cell shown in Figure 1; Figure 3 is a substrate layout diagram of the circuit shown in Figure 2; Figure 4 is an elevation view, in section, taken along the line IV-IV of Figure 3.

Figure 5 is a sectional view of a preferred embodiment of a gate interconnect which includes a load impedance device constructed according to the teachings of the present invention; Figure 6 is a sectional view of a gate interconnect portion including an alternate embodiment of a load impedance device; Figures 7 A, 7 B, 8 A, 9 A, 9 B, JOA and JOB are sectional views of alternate embodiments of impedance load devices constructed according to the teachings of the present invention.

In the description which follows, the present invention is described in combination with a random access memory of the type fabricated on a single monolithic semiconductor chip using insulated gate field effect transistor technology The structure as disclosed herein may be fabricated on a single semiconductor chip and is primarily intended for such fabrication.

Referring now to Figure 1 and Figure 2 of the drawing, a portion of a random access memory which utilizes circuitry constructed according to the teachings of the present invention is illustrated In Figure 1, a portion of a random access memory includes a plurality of static memory cells 10 which are part of an array of many such cells arranged in rows and columns in the conventional manner The memory cells 10 are disposed in the same column and accordingly are connected to complementary data buses, D, D Since the memory cells 10 are disposed in separate rows, the cells are addressed or enabled by separate row lines RA, and RA 2, respectively The row address line RA, enables all of the memory cells in one row while address line RA 2 enables all the memory cells in a second row.

A sense amplifier and level shifter is indicated generally by the reference numeral 12 and is connected to the column buses D and D The sense amp 12 may be of any conventional type, for example, that which is disclosed and claimed by U S Patent 3,967,252 Write control circuits 14 and 16 are connected to drive the column buses D and D, respectively, during a write cycle in the conventional manner Column enable means (not illustrated) may be provided to connect different pairs of column buses to a single sense amp, or a separate sense amp may be provided for each pair of column buses.

An electrical schematic diagram of the memory cell 10 is illustrated in Figure 2 of the drawing The binary memory cell 10 comprises first and second complementary data input-output nodes 1 and 2 which provide a direct current impedance path and relatively higher direct current impedance path corresponding to each binary logic state First and second impedance means, R 1 and R 2, electrically connect a drain supply node VDD to the first and second data nodes 1, 2 respectively The structure of the impedance means R 1 and R 2 will be described in detail hereinafter The memory cell 10 also includes a pair of cross coupled insulated gate field effect transistors Q 1 and

Q 2 The data nodes 1, 2 are cross-coupled by the gates of the transistors Q 1 and Q 2, respectively, and are connected by enabling transistors Q 3 and Q 4 to the column buses D and D, respectively The gates of the enabling transistors Q 3 and Q 4 are connected to the corresponding row address line RA 1.

The channel between the drain and source terminals of transistors Q 1 and Q 2 electrically connect each data node 1, 2 to a source power supply node Vss when conducting.

To understand the operation of the circuit of Figure 2, assume that the row address line RA, is low (logic " O ") so that the enabling transistors Q 3 and Q 4 of memory cell 10 which are connected to the row address line RA, are turned off This allows the column buses D and D to assume a voltage level of VDD less one threshold in this implementation because there are no current paths to the source voltage Vss In a typical circuit, VDD may be five volts and the threshold may be about 2 5 volts, in which case the column buses D and D would be about 2 5 volts In other implementations, D and D may assume voltage levels as high as VDD or as low as or slightly more than one threshold above Vss In this state, no current will flow through the column buses D and D because each is an open circuit in the absence of a current path througn an enabled cell As a result the data output nodes 1, 2 are at a voltage substantially equal to VDD or Vss, respectively, from the nodes 1, 2 to Vss.

Assume that a logic " O " has been stored in the memory cell 10 so that the transitor Q O is turned on and data node 1 is substantially at Vss, and that transistor Q 2 is turned off and the data node 2 is substantially at VDD Then when the row address line RA, goes high, that is, is charged to a bias potential corresponding to a logic " 1 ", the memory cell 10 is enabled as the transistors Q 3, Q 4 turn on This results in a current path to Vss through the transistor Q O and Q 3 and the column bus D The transistor Q 2 is turned off so that no current path is estab1 597 726 lished from the column bus D to ground As a result, the data node 2 remains substantially at VDD, or five volts If, on the other hand, a logic " 1 " is stored in the address memory cell 10, the transistor Q, is turned off and transistor Q 2 is turned on Current through Q 2 and Q 4 then causes the bus D to decrease from about 5 volts to a lower level while the voltage of the column bus D and data node 1 remain at the precharge level of volts.

It will be noted that the data output nodes 1, 2 swing between VDD and Vss depending upon the logic content of the cell These voltage levels must be maintained to preserve the logic content of the cell 10 In the memory cell 10, these reference potentials are maintained at the data nodes 1, 2 by the load impedance devices RI and R 2 which connect the nodes to the drain supply node VDD.

Referring now to Figures 3 and 4 of the drawing, a substrate layout of the memory cell 10 is illustrated According to the teachings of the present invention, each of the load impedance devices R 1 and R 2 include a body 20 of substantially pure intrinsic semiconductor material defining a first conductive path 22 and a diffusion of extrinsic conductivity impurities disposed within a region o the intrinsic body 20 defining a second conductive path 24 An intrinsic-extrinsic junction 28 is defined by the interface of the extrinsic diffusion path 24 and the undoped intrinsic path 22 The intrinsic path 22 and the extrinsic path 24 define a series electrical path from the drain supply node VDD to the corresponding data node 1, 2 As used herein, the phrase "intrinsic semiconductor material" means elemental semiconductor material which is undoped or lightly doped.

The memory cell 10 is disposed upon a substrate 30 of an extrinsic semiconductor material of a first conductivity type, for example P-type mono-crystalline silicon.

Each of the field effect transistors Q 1-Q 4 include a source region (not shown) and a drain region (not shown) material of the opposite conductivity type, for example N-type, extending substantially parallel to each other in the conventional manner in an active region 36 of the substrate 30 A layer 38 of insulation is disposed over the surface of the substrate 30 and is formed relatively thin in the gate zone 40 which lies directly over the active region 36 The conductive path 24 serves as a gate interconnect portion for the transistor formed over the active region.

The semiconductor material which forms the conductive layer 20 is of the same elemental semiconductor type as is the substrate 30, and is preferably constructed as a continuous layer of polycrystalline silicon The extrinsic impurities diffused within the layer 20 may be either N-type or P-type In a preferred embodiment, the extrinsic impurities diffused into the layer 20 are of the opposite conductivity type relative to the conductivity type of the substrate For example, for a P-type substrate 30, the impurities diffused into the layer 20 are N-type, so that the gate strip 24, source and drain regions, and impedance devices R 1, R 2 may all be formed during a single diffusion step of an isoplanar silicon gate process.

Referring now to Figures 5 and 6, the drain supply node VDD may comprise a metallization deposit 42 which is bonded directly to a diffused gate interconnect portion 43 as shown in Figures 5, or in some instances the metallization deposit 42 may be bonded directly to the substantially pure intrinsic region 22 as shown in Figure 6 of the drawing In either of the configurations shown in Figure 5 and 6, the substrate surface area utilized for the impedance load device R 2 is extremely small with the width of the gate interconnect portion 24 being typically 5 microns and the length of the intrinsic undoped conductive path 22 being typically 8 microns An intrinsic-extrinsic junction device constructed with these dimensions may exhibit as much as 1,000 megohms impedance to the flow of direct current The impedance may be reduced by diffusing a relatively light dose 47 of impurities through the intrinsic conductive path 22 until that region is transformed into a very lightly doped extrinsic conductivity region.

Examples of mixed extrinsic-extrinsic junction devices characterized by a heavy concentration of impurities disposed in junction forming relation with a relatively light concentration of impurities, both impurity concentrations being of the same conductivity type, or being of opposite conductivity, is illustrated in Figures 7 A, 7 B, 8 A, 8 B, 9 A, 9 B, 10 A and 10 B. Referring again to Figures 3 and 4, the substrate 30 is the starting material for the process of the present invention The semiconductor substrate 30 is typically silicon and may have either N-type or P-type conductivity However, the semiconductor substrate 30 may be any conventional type used in the fabrication of insulated gate semiconductor field effect devices; the crystal orientation and doping levels being and well known.

In the discussion which follows, a process is described which utilizes a substrate chip of monocrystalline silicon which has been doped with P-type impurities and into which opposite conductivity impurities are diffused to construct an N-channel insulated gate transistor in an isoplanar silicon gate diffusion process The semiconductor subs1 597 726 trate 30 is placed in a conventional oxidizing furnace and the oxide layer 38 is thermally grown on the surface of the substrate 30 to a typical thickness of 600 angstroms Thereafter a layer of nitride is deposited over the oxide layer in a thickness of approximately 600 angstroms A photoresist mask is formed over the combined nitride and oxide layers and is patterned using conventional photolithographic techniques to provide a mask to define the active area 36 and the surrounding field areas The layer of nitride is removed from the field areas and ion impurities of the same conductivity type as the doping of the substrate are implanted therein The ions may be derived from boron compounds, such as BF 3 for P-type substrates, or from phosphorous compounds, such as PH 4 to produce N-type substrates Equipment for such ion implantation is commercially available and its use for implantation purposes is well known in the industry This ion implantation step is performed in the field area surrounding the active area 36 to reduce cross talk between adjacent transistors in the same substrate.

Next the photoresist mask is removed from the active area and a layer of thermal oxide is grown over the field area to a thickness of approximately 8,000 angstroms.

Thereafter the nitride and oxide layers are removed from the active area, and a layer 40 of gate oxide is grown over the active area 36 to a thickness of approximately 900 angstroms.

Next a layer 20 of undoped polycrystalline silicon semiconductor material is deposited over the gate oxide The polycrystalline silicon layer 20 may be formed by any suitable conventional process, such as by the decomposition of Si H 4 (silane) in a cold wall epitaxial reactor or in a hot wall furnace.

The polycrystalline silicon layer 20 is typically from 3,000 angstroms to 6,000 angstroms in thickness.

The undoped polycrstalline silicon layer is masked and photoresisted to define a gate strip 24 A diffusion-impervious layer of nitride or oxide is deposited over the undoped gate interconnect portion which is masked and photoresisted to define the mask 44 over the situs 22 of the low current load impedance device, for example R 1 or R 2.

The layer of undoped polycrystalline silicon 20 and the active area 36 is then exposed to diffusion impurities of the opposite conductivity type whereby a diffused gate 24 and diffused source and drain regions (not shown) are formed within the active region 36 by the diffusion of impurities into the gate strip 24 and into the active area 36 of the substrate on either side of the gate strip.

A nondiffused channel region is defined in the active area beneath the gate strip by the masking action of the gate 24 strip as it receives the diffusion of impurities The intrinsic-extrinsic junction 28 is formed in the layer 20 at the interface of the undoped semiconductor material 22 lying beneath the mask 44 and adjacent to the impurity diffusion.

Thereafter, an insulating oxide layer is formed to a thickness of approximately 10,000 angstroms over the chip area and is masked and photoresisted to define the location of conductive interconnects Metallization deposits are formed at the appropriate conductive interconnect locations.

The gate interconnect 20 may be electrically connected to the common power supply node by electrically connecting the undoped portion 22 of the intrinsic-extrinsic junction of the load impedance device directly to the power supply node 42 In an alternate embodiment of the impedance devices R 1, R 2 wherein first and second diffused extrinsic regions 24, 43 are formed by diffusing the interconnect portion on both sides of an intermediate interior undoped region 22, the electrical union of the gate interconnect portion 20 with the common power supply node 42 is performed by electrically connecting the diffused extrinsic region 43 directly to the power supply node 42 and electrically connecting the diffused extrinsic region 24 to the drain node of the transistor.

The impurity diffusion step may be carried out by conventional techniques, for example, by exposing the surface of the substrate at temperatures in the neighbourhood of 11000 Centigrade to a gas containing the required impurities, for example boron for P-channel devices or phosphorous for N-channel devices.

The mask 44 may be formed from silicon nitride which is an effective mask against diffusion of impurities such as boron and phosphorous Silicon nitride is pyrolytically deposited by reacting silane and ammonia with excess hydrogen over the interconnect at temperatures in the range of 4000 to 11000 Centrigrade After the diffusion step, a 10,000 angstrom oxide layer is deposited over the chip area which is further masked with photoresist applied to define the VDD metallization contact node 42 which is illustrated in Figure 5 and 6 of the drawing.

The gate interconnect portions 24, 43 of each of the transistors Q 1 and Q 2 are bonded to the drain power supply node 42 and the data node 1 is connected to the drain region of Q 1 by means of conductive interconnects (not shown) to form an integrated circuit Data node 1 is formed by forming a conductive interconnect between the drain region of Q 1 and the gate interconnect portion 24 of Q 2 Similarly, data node 2 is formed by forming a conductive interconnect between the drain region of Q 2 to the 1 597 726 corresponding gate interconnect portion of Q 1.

The direct current impedance exhibited by the extremely low current load devices R,, R 2 may be reduced somewhat by diffusing a relatively light dose of extrinsic impurities through the undoped regions 22 of the devices until the material is transformed into a lightly doped extrinsic region The intrinsicl-extrinsic junction 28 is transformed into an extrinsic-extrinsic junction 48 which is characterized by a heavy concentration of impurities disposed in junction forming relation with a relatively light concentration of impurities, both impurity concentrations being of the same conductivity type, or being of the opposite conductivity type It is essential, however, that the impurity concentration levels be substantially differentiated with respect to each other in order to achieve very high direct current impedances.

The ion implanting steps described herein may be carried out by conventional ion implantation techniques, for example as disclosed and claimed in U S Patent 3,898,105, which patent is hereby incorporated by reference.

In the operating range of 5 volts and 2 5 volts at the data nodes 1 and 2 corresponding to either a logic " 1 " or logic " O ", and in consideration of a design load factor of 40 milliwatts in standby mode, for a 4 K bit ( 4096 bits) memory, each bit consumes 01 milliwatts of power At 5 volts, no more than 2 microamps per load device must be provided by the impedance load device R 1, R 2 This establishes a value of 2 5 megohms as the lower limit of the range of the impedance of the low load devices R 1 and R.

The upper limit of the impedance range corresponding to the expected maximum leakage of the transistors Q 1 and Q 2 is found by dividing 2 5 volts by 10 nanoamps (which is the maximum leakage expected for Q 1 and Q 2) which yields 250 megohms By careful control of the purity of the undoped polysilicon region 22 and the N-type extrinsic doping of the polysilicon layer 20, the resistance of R 1 and R 2 can be controlled within the range from 2 5 to 250 megohms to provide a memory cell which consumes a minimum amount of current through a given temperature range subject to the maximum value allowable for power considerations and the maximum leakage current expected at elevated operating temperatures.

The reader's attention is drawn to our copending application No 48383/77 (Serial No 1597725).

Claims (14)

WHAT WE CLAIM IS:-

1 A semiconductor structure comprising:

a monocrystalline semiconductor substrate of a first conductivity type starting material, a body of polycrystalline semiconductor material disposed above the substrate, the polycrystalline body being at least partially doped with impurities, including a region of substantially undoped or lightly doped semiconductor material defining a first conductive path and a region of relatively heavily doped semiconductor material defining a second conductive path, the first and second conductive paths defining a series electrical path for the flow of current through the poly-crystalline body and defining a junction at the interface of said first and second conductive paths, the first conductive path having a level of impurity doping substantially lower than the level of impurity doping of the second conductive path, the junction being characterised by a substantially differentiated impurity concentration level to achieve a very high direct current impedance.

2 A semiconductor structure according to claim 1 including a region of heavily doped semiconductor material defining a third conductive path, the first, second and third conductive paths defining a series electrical path with the first conductive path interposed between the second and third conductive paths, the doping of the semiconductor material of the first conductive path consisting essentially of impurities of the first conductivity type, the doping of the semiconductor material of the second and third conductive paths consisting essentially of impurities of the conductivity type opposite of the first conductivity type.

3 A semiconductor structure according to claims 1 or 2 further including an insulated gate field effect transistor formed on the substrate, the transistor including elongated source and drain regions of semiconductor material of a second conductivity type disposed within the substrate and defining a channel region of the first conductivity type in the substrate therebetween, and an insulated gate disposed over the channel region, wherein a portion of the -second conductive path forms the gate.

4 A semiconductor structure according to claims 1 or 2 further including an insulated gate field effect transistor formed on the substrate, the transistor including source and drain regions of semiconductor material of a second conductivity type disposed with the substrate and defining a channel region of the first conductivity type in the substrate therebetween, and an insulated gate disposed over the channel region, and wherein the first and second conductive paths are connected to conduct current from a first power supply node through the channel to a second power supply node whenever the channel becomes conductive 1 597 726 in response to an electrical potential applied to the gate, the magnitude of the impurity concentration in the first conductive path being substantially less than the magnitude of the impurity concentration in the second conductive path.

A semiconductor structure according to claim 4 wherein the first power supply node, when energised, has a positive polarity providing a positive potential difference for the drain potential with respect to the source potential in response to the flow of current from the power supply node through the channel, the conductivity type of the semiconductor material comprising the source and drain regions and comprising the second conductive path being N-type.

6 A semiconductor structure according to claim 4 wherein the first power supply node, when energised has a negative polarity providing a negative potential difference for the drain potential with respect to the source potential in response to the flow of current from the power supply node through the channel, the conductivity type of the semiconductor material comprising the source and drain regions and comprising the second conductive path being P-type.

7 A semiconductor structure according to any preceding claim wherein the elemental semiconductor material of the monocrystalline substrate and the polycrystalline body consists essentially of silicon.

8 A method for producing the semiconductor structure of claim 4 comprising:

forming a relatively thick oxide layer over portions of the substrate defining a field area; forming a relatively thin oxide layer over portions of the substrate defining an active area; depositing a layer of polycrystalline semiconductor material over the oxide layers; selectively removing portions of the polycrystalline semiconductor layer to define the first and second conductive paths; selectively removing the thin oxide layer from portions of the active area to define the sites of drain and source regions; and selectively doping impurities of the second conductivity type into the portions of the polycrystalline semiconductor layer defining the second conductive path and into the portions of the substrate defining the source and drain regions.

9 A method according to claim 8, further including the step of selectivity forming a conductor over-lapping a portion of the first conductive path to form the first power supply node.

A method according to claims 8 or 9 further including the step of selectively doping the first conductive path with a relatively light dose of impurities of the first conductivity type.

11 A method according to claims 8, 9 or further including the step of forming the electrical union of the first conductive path with the first power supply node by electrically connecting the semiconductor layer portion forming the first conductive path directly to the first power supply node.

12 A method according to any of claims 8 to 11, further including the step of forming an electrical connection between the second conductive path and the first power supply node by electrically connecting a portion of the semiconductor layer forming a third conductive path directly to the first power supply node, the third conductive path being formed in a manner similar to the formation of the second conductive path, the first, second and third conductive paths defining a series electrical path with the first conductive path interposed between the second and third conductive paths.

13 A semiconductor structure according to claim 1 substantially as hereinbefore described with reference to and as shown in the accompanying drawings.

14 A method for producing a semiconductor structure according to claim 8 substantially as hereinbefore described with reference to the accompanying drawings.

For the Applicants, CARPMAELS & RANSFORD, Chartered Patent Agents, 43 Bloomsbury Square, London, WC 1 A 2 RA.

Printed for Her Majesty's Stationery Office.

by Croydon Printing Company Limited Croydon, Surrey 1981.

Published by The Patent Office 25 Southampton Buildings.

London WC 2 A IAY, from which copies may be obtained.