JPH0613577A - Semiconductor impedance device - Google Patents

Abstract

PURPOSE: To provide a semiconductor impedance device, which imparts high resistance and has a very small occupying area. CONSTITUTION: A semiconductor impedance device is provided in a single body 20 of polycrystalline semiconductor material formed on an insulating layer 38 attached on a substrate 30. The specified region of the single body 20 is doped by extrinsic impurities and forms a second conducting path 24. In the meantime, the substantially intrinsic region forms a first conducting path 22. A boundary 28 between the first conducting path and the second conducting path forms an intrinsic - extrinsic junction. Therefore, the impedance characteristic is obtained with the intrinsic - extrinsic junction. Thus, the occupying area is very small, and the negative temperature coefficient is provided. Therefore, the temperature-compensating effect can be provided. Since the device is substantially intrinsic, manufacturing is easy, and the yield is improved.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to random access memory (RA) of the type manufactured on monolithic semiconductor chips utilizing insulated gate semiconductor field effect transistor technology.
M), and more particularly to a semiconductor impedance device for conducting an extremely low current flowing from a drain power supply node to a channel of an insulated gate field effect transistor (IGFET) in a memory cell.

[0002]

2. Description of the Prior Art Digital memories use two external signals for each bit of a computer word to be stored.
It must have a separate physical memory cell that can be set to one of two different states. The cell must remain in the set state indefinitely or remain in the set state until changed to another state by another external signal. The two distinct states of the memory cell can be spontaneous states that do not require an external energy source to be held in that state. It is also possible to use a volatile memory device that requires an external bias to retain the stored state. A well-known example of such a memory element is a bistable circuit using a semiconductor device. These devices require a continuous or continuous power supply in order to prevent the deterioration or complete loss of stored information.

Large scale integrated circuit (LSI) technology has led to the construction of large arrays of such memory devices on a single chip of silicon. Typically, these memory cells using MOS technology consist of multi-component circuits with a conventional bistable structure. Since a semiconductor bistable element requires a constant power source for holding stored information, this type of memory is originally a volatile memory. In some applications, it is essential that data is not permanently lost due to power interruption. In those cases, the reserve power from the battery is used, and the battery is connected to supply power to the power supply node of the memory device when the DC power is interrupted unexpectedly, and the memory operates in the reserve mode. Power may be supplied during the operation.

The direct advantages of the semiconductor memory device are high packaging density and low power consumption. Insulated gate MOS transistors have been particularly utilized in this field of application because they require a small substrate area, thus increasing packaging density and allowing operation at very low power levels. Known memory cell circuits using IGFETs include US Pat. No. 3,967,25.
There is a cross-coupled inverter stage disclosed in No. 2. In that circuit, the gates of a pair of MOSFETs are cross-coupled to the true and complement data nodes. The information stored in the cell is adapted to be held by the impedance device. That is, the impedance device is connected to the data node and holds the gate voltage of the transistor at a predetermined level corresponding to the logic content of the cell. Each inverter of the cell consists of a drive transistor and a load impedance device. In the circuit shown in the above referenced patent, the load impedance device comprises a MOSFET. In earlier circuits,
An impedance device having a diffusion resistance of 10 to 20 Ω / □ has been typically used. But MOSFET
Can give 20,000 Ω / □, 100,0
Since a practical resistance value of about 00 to 200,000 Ω can be given, the MOSFET has come to be used.

Even with a smaller surface area than conventional diffusion resistors, MOS technology allows the implementation of more complex circuits than other methods on a single monolithic chip. In application to low current load devices, depletion MOS
Connecting the gate of the FET to the source reduces the occupied substrate area. However, in the application to extremely low current load,
A depletion transistor with its gate connected to its source is 6.45 × in the load range of the microampere range.
It occupies several times the area of 10 ⁻⁴ mm ² (1 square mil).

The static random access memory cell shown in US Pat. No. 3,967,252 includes two cross-coupled inverters and two transfer resistors, two load devices and four transistors. Exists. In a 1K static RAM, 102
Four memory cells occupy about 40% of the total chip area, but in a 4K static RAM, 4096 cells occupy only a slightly higher percentage of the chip. In order to make the chip area as small as possible and the power consumption as small as possible, the two load devices in the static cell of each inverter must have a relatively small area and use an extremely low current. One drawback of using a depletion transistor as a load device is that the substrate effect due to reverse gate bias generally increases as the physical size of the active area decreases. Another drawback of using MOS devices as load resistors is that the resistance exhibited by MOS devices is essentially limited by the substrate effect associated with the reverse bias voltage from the source to the substrate. This device is 100KΩ to 200K
For certain applications that provide practical resistance values in the order of Ω but have very low power consumption, it is desirable to use a load device that exhibits a resistance in the range of 1 MΩ to 100 MΩ.

[0007]

DISCLOSURE OF INVENTION Problems to be Solved by the Invention
A very low current load device exhibiting a resistance much greater than that provided by the S load device, which occupies a relatively small surface area of the substrate and is not adversely affected by reverse bias conditions. It is an object to provide an impedance device.

[0008]

A semiconductor impedance device according to the present invention is an intrinsic-extrinsic device created by the boundary between a substantially pure intrinsic semiconductor material and an extrinsic impurity diffusion region located within the region of the intrinsic semiconductor material. A semiconductor structure having a sexual junction. The intrinsic semiconductor material is of the same simple semiconductor type as the substrate, but its conductivity is substantially smaller than that of the extrinsic semiconductor material. Extrinsic semiconductor material is N
It may be a shape or a P shape.

The present invention can be implemented in combination with an IGFET binary memory cell having true and complement data input / output nodes that provide a DC impedance path corresponding to each binary logic state. In that case, for a typical drain power supply voltage V _DD value (eg, 5V DC), the total leakage current of each electrically cross-coupled transistor with the data node is in the picoampere range, but the intrinsic-extrinsic junction impedance. The current conducted by the device is in the nanoamp range. Therefore, this low current load impedance device can provide a current sufficient to overcome the leakage at the P-N junction in the memory cell, thereby retaining the gate bias and retaining the logic content of the cell. The temperature coefficient of this impedance device is characterized as having the same polarity as the temperature coefficient of the memory cell junction, so that the low current load device "tracks" the temperature change in the leakage current of the memory cell transistor. Therefore, the power consumed by the memory cell can be designed to have a minimum value within a certain operating temperature range. It should be noted that conventional high resistance diffused resistors do not allow minimum current design in the same temperature range. The reason is that the leakage current at the drain of the memory cell transistor increases with temperature, while the current through the conventional diffusion resistor decreases.

In the device of the present invention, a very low current load device is constructed by depositing a layer of substantially intrinsic semiconductor material on the surface of an insulating layer, thereby forming a drain diffusion node of an IGFET and a drain power supply. A conductive interconnection can be made to the node. A drain diffusion node by diffusing impurities through a mask formed in a selected surface region of the intrinsic interconnect layer until the intrinsic semiconductor material below the areas exposed by the mask is converted to an extrinsic conductivity type. An intrinsic-extrinsic junction is formed at a selected position between the drain power supply node and the drain power supply node.

In the preferred embodiment, each impedance device is formed in an isoplanar silicon gate process as an integral part of a polycrystalline silicon strip interconnecting the drain power node to one of the selected data nodes. A portion of the polycrystalline silicon strip extends from the selected data node to form a gate at which that data node is cross-coupled.

The DC impedance due to the intrinsic-extrinsic junction of silicon approaches 1,000 MΩ when reverse biased.
This impedance can be reduced by diffusing a relatively small amount of impurities through the intrinsic semiconductor region until the region is transformed into a lightly doped extrinsic region. According to this method, the intrinsic-extrinsic junction is converted into an extrinsic-extrinsic junction characterized in that the high-concentration impurity regions are arranged in a relationship forming a junction with the relatively low-concentration impurity regions. It In that case, both impurity concentrations may be the same conductivity type or opposite conductivity types.

[0013]

DETAILED DESCRIPTION OF THE INVENTION The present invention is described below in combination with a RAM of the type fabricated on a single monolithic chip using insulated gate field effect transistor technology. The structures disclosed herein can be fabricated on a single semiconductor chip and are primarily intended for such fabrication.

1 and 2 show a portion of a RAM using a circuit constructed according to the present invention.

Although the portion of the RAM of FIG. 1 contains a plurality of static memory cells 10, these are portions of an array of many such cells arranged in a matrix in a conventional manner. The memory cells 10 are arranged in the same column and have complementary data buses D, D. Is joined to. (Note that the underline after the English character represents its complement and has the same meaning as overline.) Since the memory cells 10 are arranged in different rows, these cells are different row lines RA ₁
And RA ₂ respectively are addressed or enabled. The row address line RA ₁ enables all the memory cells in the first row, and the row address line RA ₂ enables all the memory cells in the second row.

A sense amplifier and level shifter is indicated generally by the reference numeral 12 and is associated with column buses D and D.
It is connected to the. Sense amplifier 12 may be of any conventional type, such as that disclosed in US Pat. No. 3,967,252. Write control circuits 14 and 16 operate on column buses D and D, respectively, in the usual manner during the write cycle.
Is connected to drive. A column enabler (not shown) may be provided to connect different pairs of column buses to a single sense amplifier, or a separate sense amplifier for each pair of column buses. Good.

FIG. 2 shows an electrical schematic diagram of the memory cell 10. Binary memory cell 10 has first and second complementary data input / output nodes 1 and 2, which are DC impedance paths corresponding to binary logic states and DC impedance paths of relatively high impedance. Is making. The first and second impedance devices R ₁ and R ₂ connect the drain power supply node V _DD to the first and second data nodes 1 and 2, respectively. The structure of the impedance devices R ₁ and R ₂ will be described in detail later. Memory cell 10 further includes a pair of cross-coupled insulated gate field effect transistors Q ₁ and Q ₂ . Data nodes ₁ and ₂ are cross-coupled by the gates of transistors Q ₁ and Q ₂ , respectively, and column buses D and D, respectively, by enablement transistors Q ₃ and Q ₄ .
It is connected to the. The gates of enablement transistors Q ₃ and Q ₄ are connected to the corresponding row address line RA ₁ . The channels between the drain and source terminals of the transistors Q ₁ and Q ₂ electrically connect the respective data nodes 1 and 2 to the source power supply node V _ss when in the conductive state.

[0018] To understand the operation of the circuit of FIG. 2, there row address line RA ₁ is in a low level (logic "0", the memory cell 1 connected Accordingly to the row address line RA ₁
Assume that 0 enable transistors Q ₃ and Q ₄ are in the off state. As a result, in this device the column buses D and D _Will take a voltage level V _DD less than one threshold. The reason is the source voltage V _ss
This is because there is no current path to. In a typical circuit, V _DD may be 5V and the threshold may be about 2.5V,
In that case the row buses D and D Is about 2.5V. In other devices, D and D It takes the same whether taken height voltage level or V _ss and a slightly higher voltage level than the comparable or V _ss least one threshold, and V _DD is. In this state, the column buses D and D No current flows. The reason is that there is no current path due to the enabled cells and each column bus is open circuit. As a result, the data output nodes 1 and 2 have a voltage substantially equal to V _DD or V _ss from the nodes 1 and 2 to V _ss , respectively.

Since a logical "0" is stored in memory cell 10 and transistor Q ₁ is on, data node 1 is substantially at V _ss and transistor Q 1 is at
₂ is off so that data node 2 is effectively V _DD
It is assumed that In this case, the row address line RA ₁
There becomes a high level, i.e., the memory cell 10 along with the once charged to a voltage corresponding to a logical "1" the transistor Q _3, Q ₄ are turned on is operable. This creates a current path through transistors Q ₁ and Q ₃ and column bus D to V _ss . Since the transistor Q ₂ is off, the column bus D There is no current path from the ground to the ground. As a result, data node 2 remains substantially held at V _DD , ie 5V. If, on the other hand if a logical "1" is stored in the address memory cell 10, the transistor Q ₁ is in the off state, the transistor Q ₂ is in the ON state. In that case, the current through Q ₂ and Q ₄ is the bus D From about 5V to a low level, column bus D and data node 1 are held at a precharge level of 5V.

The data output nodes 1 and 2 take either value of V _DD or V _ss according to the logical content of the cell. These voltage levels must be maintained in order to maintain the logical content of cell 10. In memory cell 10, these reference voltages are held at data nodes ₁ and ₂ by load impedance devices R ₁ and R ₂ connecting data nodes 1 and 2 to drain power supply node V _DD .

Next, FIGS. 3 and 4 show the arrangement of the memory cell 10 on the substrate. According to the invention, the load impedance devices R ₁ and R ₂ each include a substrate 20 of substantially pure intrinsic semiconductor material and a second substrate 20 each of which defines a first conductive path 22.
And a diffusion region of extrinsic conductive impurities disposed within a region of the intrinsic semiconductor material substrate 20 that defines the conductive path 24 of the.
An intrinsic-extrinsic junction 28 is formed by the interface between the extrinsic conductive path 24 and the undoped intrinsic conductive path (intrinsic semiconductor region) 22. Intrinsic conduction path 22 and extrinsic conduction path 2
4 forms a series current path from the drain power supply node V _DD to the corresponding data nodes 1 and 2. As used herein, the term "intrinsic semiconductor material" shall mean a non-doped elemental semiconductor material that has never been subjected to impurity diffusion or implantation.

The memory cell 10 is arranged on a substrate 30 of extrinsic semiconductor material of the first conductivity type, for example P-type single crystal silicon. The field effect transistor Q ₁ to Q ₄ has the opposite conductivity type, for example, the source regions of N-type material (not shown) and a drain region (not shown), these regions usual methods The active area 36 of the substrate 30
Extend substantially parallel to each other. The insulating layer 38 is disposed on the surface of the substrate 30, and is formed relatively thin in the gate region 40 immediately above the active region 36. Extrinsic conductive path 24 forms the gate interconnect for transistors formed on the active region.

The semiconductor material forming the conductive layer 20 is the substrate 3
It is preferably of the same single semiconductor type as 0, and is preferably constructed as a continuous layer of polycrystalline silicon. Conductive layer 20
The extrinsic impurities diffused in may be N-type or P-type.
In the preferred embodiment, the extrinsic impurities diffused into the conductive layer 20 are of a conductivity type opposite to that of the substrate 30. For example, for the P-type substrate 30, the impurity diffused in the conductive layer 20 is N-type, and therefore the gate strip (abbreviated as gate strip 24) forming the extrinsic conductive path 24, the source and drain regions, and the impedance. Devices R ₁ and R ₂ can all be formed in a single diffusion step of the isoplanar silicon gate process.

5 and 6, the drain power supply node V _DD may have a metal deposit 42 directly bonded to the diffusion gate interconnect 43 as shown in FIG. . Or in some cases, as shown in FIG. 6, a metal deposit 42 may be directly bonded to the substantially pure intrinsic semiconductor region 22 defining the first conductive path.

In both of the structures shown in FIGS. 5 and 6, the surface area of the substrate used for the impedance load device R ₂ is very small and the extrinsic conductive path 2
The typical width of the 4 gate interconnect is 5μ and the typical length of the undoped intrinsic conductive path 22 is 8μ. Intrinsic-extrinsic junction devices formed with these dimensions exhibit a large impedance of 1000 MΩ for direct current. A relatively small amount of impurities 47 is added to the intrinsic conductive path 22.
The impedance can be reduced by diffusing the region until it is converted to a very lightly doped extrinsic conductivity type region. In a mixed-type extrinsic-extrinsic bonding apparatus, which is characterized in that a high-concentration impurity region and a relatively low-concentration impurity region are arranged in a relationship forming a junction, both impurity concentrations have the same conductivity. 7A, 7B, 8A, 8B, 9A, 9B, 9A, 9B, 9A, 9B, and 9A and 9B.
10A and 10B, and FIGS. 10A and 10B.

Referring again to FIGS. 3 and 4, substrate 30 is the starting material for the process of the present invention device. A typical semiconductor substrate 30 is silicon, and the conductivity type may be N type or P type. However, the semiconductor substrate 30 may be of any conventional type used in the fabrication of insulated gate semiconductor field effect transistor devices, the crystal orientation and doping levels of which are well known and conventional.

In the following discussion, a single crystal silicon substrate chip doped with P-type impurities is further incorporated therein to form an N-channel insulated gate transistor by an isoplanar silicon gate process. A method of using the substrate chip in which the impurities are diffused will be described. The semiconductor substrate 30 is placed in a conventional oxidation furnace, and an oxide layer 38 having a typical thickness of 600Å is thermally grown on the surface of the substrate 30. Then, a nitride layer with a thickness of about 600Å is deposited on the oxide layer. A photoresist mask is then formed on both the combined nitride and oxide layers, and the mask is patterned by conventional photolithographic techniques, thereby defining active areas 36 and surrounding field areas. I can make a mask. The nitride layer is removed from the field region, and an ionic impurity having the same conductivity type as the doping of the substrate is implanted therein. The ions can be extracted from boron compounds such as BF ₃ for P-type substrates and phosphorus compounds such as PH ₄ to make N-type substrates. Equipment for ion implantation in that case is commercially available, and its use in performing implantation is well known in the industry. This ion implantation process step is performed in the active region 36.
To the field region around the, thereby reducing crosstalk between adjacent transistors in the same substrate.

When the photoresist mask is removed from the active area, a layer of thermal oxide is then grown on the field area to a thickness of about 8,000 Å. Both nitride and oxide layers are then removed from the active region and gate oxide layer 40 is grown on active region 36 to a thickness of about 900Å.

Next, a layer 20 of undoped polycrystalline silicon intrinsic semiconductor material (hereinafter referred to as polycrystalline silicon layer) is deposited on the gate oxide. The polycrystalline silicon layer 20 can be formed by any suitable conventional method, such as by decomposition of SiH ₄ (silane) in a cold wall epitaxial reactor or in a hot wall furnace. A typical thickness of the polycrystalline silicon layer 20 is 3,000Å to 6,000.
It is 0Å.

Undoped polycrystalline silicon layer 20
Are masked and photoresist processed to define gate strips 24. Depositing a nitride or oxide diffusion barrier on the undoped gate interconnect,
It is masked and photoresist treated to define a mask 44 over the location of intrinsic conductive path 22 for low current load impedances, eg R ₁ or R ₂ .

Next, the undoped polycrystalline silicon layer 20 and the active region 36 layer is subject to impurity diffusion of the opposite conductivity type to that region 36, whereby the impurities are exposed to the gate strip 24 and both sides of the gate strip. By diffusing into the active region 36, a diffusion gate and both diffusion source and diffusion regions (not shown) are formed. The non-diffused channel region is formed in the active region under the gate strip due to the masking action of the gate strip 24 when undergoing impurity diffusion. Intrinsic-exogenous junction 28
Is formed at the boundary between the region 22 of undoped semiconductor material below the mask 44 of the polycrystalline silicon layer 20 and the impurity diffusion region adjacent thereto.

Next, an insulating oxide layer having a thickness of about 10,000Å is formed on the chip area, and is masked and photoresist-treated to form conductive interconnection points. A metal deposit is formed at the appropriate conductive interconnect location.

By electrically connecting the undoped intrinsic semiconductor region 22 of the intrinsic-extrinsic junction of the load impedance device directly to the power node 42, the polysilicon layer 20 forming the gate interconnect is electrically connected to the common power node. Connected. The gate interconnects 24, 43, which in the alternative embodiment of the impedance devices R ₁ , R ₂ are first and second diffusion extrinsic regions, diffuse to the interconnects on either side of the intermediate undoped intrinsic semiconductor region 22. It is formed by In that embodiment, the electrical coupling between the gate connection (ie polycrystalline silicon layer 20) and the common power node (ie metal deposit 42) is such that the second diffusion extrinsic region 43 is directly electrically connected to the common power node. By electrically connecting the first diffused extrinsic region 24 to the drain node of the transistor.

The process steps for impurity diffusion include, for example, the necessary impurities on the surface of the substrate at temperatures around 1100 ° C., such as boron for P-channel devices and phosphorus for N-channel devices, by conventional techniques. It is done by exposing to gas.

The mask 44 is formed of silicon nitride, which is an effective mask for diffusion of impurities such as boron and phosphorus. Silicon nitride contains silane and ammonia together with excess hydrogen at 400 ° C to 1100 ° C.
Is deposited on the interconnect region 20 by a thermal decomposition reaction in the temperature range of. After this diffusion step, a 1,000 Å oxide layer is deposited on the chip area to further form the V _DD node metal deposit 42 shown in FIGS. 5 and 6. Masked by the photoresist applied to the.

The gate interconnects 24 and 43 of each transistor Q ₁ and Q ₂ are bonded to the drain power node, and the data node 1 is connected to the drain region of Q _{1 by} a conductive interconnect material (not shown). Integrated circuit is formed. The data node 1 is constructed by forming a conductive interconnect between the drain region of Q ₁ and the gate interconnect 24 of Q ₂ . Similarly, by forming a conductive interconnect between the drain region of Q ₂ and the corresponding gate interconnect of Q ₁ , data node 2
Is configured.

The DC impedance of the ultra low current load devices R ₁ , R ₂ is such that the extrinsic region is lightly doped with relatively small amounts of extrinsic impurities through the undoped intrinsic semiconductor region 22 of these devices. Can be reduced somewhat by spreading until converted to. At this time, the intrinsic-extrinsic junction 28 is converted into the extrinsic-extrinsic junction 48, and the latter is characterized in that the high-concentration impurity region and the relatively low-concentration impurity region are arranged in a junction formation relationship. And In that case, both impurity concentrations may be the same conductivity type or opposite conductivity types. However, in order to realize the extremely high DC impedance, it is essentially important that the impurity concentration levels thereof are substantially different from each other.

The ion implantation steps described herein are conventional ion implantation techniques, eg, US Pat. No. 3,898,105.
It is carried out by the technique disclosed in No.

40 mW in standby mode in the 5 V and 2.5 V operating ranges at data nodes 1 and 2 corresponding to either a logical "1" or a logical "0".
In consideration of the design load level of 4K bits (4096
(Bit) memory, each bit consumes 0.01 mW of power. At 5V, impedance load devices R ₁ and R ₂
Therefore, a current of 2 μA or less must be supplied per load device. Therefore, the lower limit of the impedance range of the low load devices R ₁ and R ₂ is 2.5 MΩ. The upper limit of the impedance range corresponding to the maximum expected leakage of transistors Q ₁ and Q ₂ is 2.5V
It can be seen that dividing by 0 nA (maximum leakage current expected for Q ₁ and Q ₂ ) gives 250 MΩ. By carefully controlling the N Katachigaiin of doping purity and polycrystalline silicon layer 20 of the undoped polycrystalline silicon region 22, in order to realize a memory cell current consumption is minimized within a certain temperature range, R ₁ and the resistance value of R _2, 2.5 to the resistance value of R ₁ and R ₂ from the condition of maximum expected leakage current value at the maximum allowable power value and the elevated operating temperature can be controlled in the range of 250Emuomega.

[Brief description of drawings]

FIG. 1 is an RA using a memory cell of an application example of the present invention.
The block diagram of a part of M.

FIG. 2 is an electric circuit diagram of the memory cell of FIG.

FIG. 3 is a layout diagram of the circuit of FIG. 2 on a substrate.

4 is a vertical cross-sectional view taken along the line IV-IV in FIG.

FIG. 5 is a cross-sectional view of a preferred embodiment of a gate interconnect having a load impedance device constructed in accordance with the present invention.

FIG. 6 is a cross-sectional view of a gate interconnect according to another embodiment of a load impedance device.

7A and 7B are cross-sectional views of another embodiment of the load impedance device constructed according to the present invention.

8A and 8B are cross-sectional views of yet another embodiment of a load impedance device configured according to the present invention.

9 (A) and 9 (B) are cross-sectional views of yet another embodiment of the load impedance device constructed according to the present invention.

10A and 10B are cross-sectional views of yet another embodiment of a load impedance device constructed according to the present invention.

[Explanation of symbols]

 20 intrinsic polycrystalline silicon semiconductor layer 22 first conductive path 24, 43 second conductive path 28 intrinsic-extrinsic junction

Front Page Continuation (72) Inventor Tsui Chiu Chi Yang 1633 Camaro Drive, Carrollton, Texas, USA

Claims (1)

[Claims] 1. A semiconductor impedance device provided on an insulating layer deposited on the surface of a substrate of single crystal semiconductor material, wherein the semiconductor impedance device has a substantially intrinsic portion defining a first conductive path by a portion thereof on the insulating layer. A base of polycrystalline semiconductor material is integrally patterned, and an extrinsic impurity doped region of a predetermined conductivity type defining a second conductive path is formed in a predetermined region of the base. An intrinsic-extrinsic junction is defined by a boundary between the substrate and the doped region, and the first conductive path and the second conductive path form a series electrical path for a current passing through the intrinsic-extrinsic junction. Semiconductor impedance device characterized by being.